CN107863964B - Accurately control the fully differential charge transfer circuit of common mode charge amount - Google Patents
Accurately control the fully differential charge transfer circuit of common mode charge amount Download PDFInfo
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- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Abstract
The present invention relates to a kind of fully differential charge transfer circuits for accurately controlling common mode charge amount comprising the first numerical model analysis control type charge transfer circuit and the second numerical model analysis control type charge transfer circuit；It further include the first common mode charge detection circuit, common mode feed forward circuit, the second common mode charge detection circuit, detection processing circuit, common mode charge adjustment circuit, M adjustment registers and controller calibration；The present invention can automatically detect the common mode charge error in charge-domain pipelined analog-digital converter, and the common mode charge error is accurately compensated, to overcome common mode charge error to further increase the conversion performance of existing charge-domain pipelined analog-digital converter to the limitation of the dynamic property of existing charge-domain pipelined analog-digital converter.
Description
Technical field
The present invention relates to a kind of signal circuit of analog-digital converter, especially one kind to accurately control common mode charge amount
Fully differential charge transfer circuit, specifically have a talk about in charge-domain pipelined analog-digital converter accurately control common mode electricity
The fully differential charge transfer circuit of lotus amount, belongs to the technical field of microelectronics.
Background technique
With the continuous development of Digital Signal Processing, the digitlization of electronic system and it is integrated be inexorable trend.So
And the signal in reality is mostly the analog quantity of consecutive variations, need to become digital signal by analog-to-digital conversion can be input to number
It is handled and is controlled in system, thus analog-digital converter (ADC) is indispensable group in following Design of Digital System
At part.In application fields such as broadband connections, digital high-definition television and radars, system requirements analog-digital converter has very simultaneously
High sampling rate and resolution ratio.Requirement of the portable terminal product of these application fields for analog-digital converter not only wants high
Sampling rate and high-resolution, power consumption should also minimize.
Currently, can be achieved at the same time high sampling rate and high-resolution analog-digital converter structure as pipeline organization modulus
Converter.Pipeline organization is a kind of transformational structure of multistage, and every level-one uses the analog-digital converter of the basic structure of low precision,
Processing of the input signal Jing Guo level-one grade, finally by every grade of the high-precision output of result combination producing.Its basic thought is exactly
The conversion accuracy generally required is evenly distributed to every level-one, the transformation result of every level-one merges available final
Transformation result.Since pipeline organization analog-digital converter can realize best trade-off on speed, power consumption and chip area,
Therefore higher speed and lower power consumption are still able to maintain when realizing the analog-to-digital conversion of degree of precision.
The mode of the realization pipeline organization analog-digital converter of existing comparative maturity is the flowing water based on switched capacitor technique
Cable architecture.The work of sampling hold circuit and each height grade circuit is also all necessary in production line analog-digital converter based on the technology
Use the operational amplifier of high-gain and wide bandwidth.The use of these high-gains and wide bandwidth operational amplifier limits switch electricity
The speed and precision for holding production line analog-digital converter becomes the major limiting bottleneck of such performance of analog-to-digital convertor raising, and
In the case that precision is constant analog-digital converter power consumption levels with speed the linear ascendant trend of raising.It reduces based on switch electricity
The power consumption levels of the production line analog-digital converter of capacitive circuit, most straightforward approach are exactly to reduce or eliminate high-gain and ultra wide band
The use of wide operational amplifier.
Charge-domain pipelined analog-digital converter is exactly a kind of mould without using high-gain and the operational amplifier of ultra wide bandwidth
There is low power consumption characteristic to be able to achieve high speed and high-precision again simultaneously for number converter, the structural module converter.Charge-domain flowing water
Line analog-digital converter uses charge-domain signal processing technology.In circuit, signal is indicated in the form of charge packet, the size of charge packet
Represent different size of semaphore, storage, transmission, plus/minus, comparison etc. of the different size of charge packet between different memory nodes
Signal processing function is realized in processing.Carry out the different size of charge packet of drive control in different storages by using periodic clock
Signal processing between node can realize analog-digital conversion function.However, its outstanding problem faced be its performance vulnerable to
The influence of common mode charge error and generate penalty.
In the factors for influencing common mode charge, the influence of the charge transfer circuit module between sub- grade circuit to Guan Chong
It wants.Realization for high efficiency charge transfer circuit, existing technical implementation way are typically include following document: US2007/
The patent document of 0279507A1 proposes a kind of substantially enhanced charge transfer circuit, can greatly improve charge transmission technology.It is public
The number of opening is that the file of CN102394650A proposes a kind of artifact dynamic auxiliary type charge transfer circuit, can inhibit PVT fluctuation to electricity
The influence of common mode charge error caused by lotus is transmitted.The file of Publication No. CN101882929A proposes a kind of total for input
The numerical model analysis compensation technique of mould error, to solve influence of the common-mode error caused by input signal to charge-domain ADC performance.
It therefore is the precision for further promoting charge-domain pipelined ADC, design accurately controls the differential charge transmission of common mode charge amount
Circuit is meaningful.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of common mode charge amount that accurately controls is provided
Fully differential charge transfer circuit can improve the performance of charge-domain pipelined analog-digital converter, securely and reliably.
According to technical solution provided by the invention, the fully differential charge transmission electricity for accurately controlling common mode charge amount
Road, including the first numerical model analysis control type charge transfer circuit and the second numerical model analysis control type charge transfer circuit；Also wrap
Include the first common mode charge detection circuit, common mode feed forward circuit, the second common mode charge detection circuit, detection processing circuit, common mode electricity
Lotus adjustment circuit, M adjustment registers and controller calibrations；
Differential input endQ in,p , differential input endQ in,n It is connected respectively to the differential charge of the first common mode charge detection circuit
The output end of input terminal, the first common mode charge detection circuit is connected to the input terminal of common mode feed forward circuit；Common mode feed forward circuit
Output end Vf is connected to the first common mode adjustment signal input terminal FF of the first numerical model analysis control type charge transfer circuit, the simultaneously
First common mode adjustment signal input terminal FF of two numerical model analysis control type charge transfer circuits；First numerical model analysis control type charge
The output end of transmission circuit, the second numerical model analysis control type charge transfer circuit output end be connected respectively to the second common mode charge
The output end of the differential charge input terminal of detection circuit, the second common mode charge detection circuit is connected to the input of detection processing circuit
End；The output end of detection processing circuit is connected to the detection signal input part of controller calibration；The position the M compensation codes of controller calibration
Output end is connected to the signal input part of M adjustment registers, and the signal output end of M adjustment registers is connected to common mode charge
The control signal input of adjustment circuit；It is mixed that the control signal output of common mode charge adjustment circuit is connected to the first digital-to-analogue simultaneously
Close the second common mode adjustment signal input terminal FB, the second numerical model analysis control type charge transfer circuit of control type charge transfer circuit
The second common mode adjustment signal input terminal FB.
Controller calibration can control into calibration mode or normal mode of operation；
Initially enter calibration mode, controller calibration is by the first modulus mixing control type charge transfer circuit, the second digital-to-analogue
The corresponding differential input end of mixing control type charge transfer circuit is connected to input reference voltage；And then the first common mode electricity is opened
Lotus detection circuit and the second common mode charge detection circuit, the output of the second common mode charge detection circuit are successively detected processing electricity
Road carries out statistical disposition, then carries out operation by controller calibration, carries out assignment to M adjustment registers；Common mode charge adjustment
Circuit generates offset voltage Vadj according to the M digit numeric code of M adjustment registers, under the action of the offset voltage Vadj,
Control the first numerical model analysis control type charge transfer circuit, the second numerical model analysis control type charge transfer circuit exports altogether accordingly
The mould quantity of electric charge；Finally, controller calibration opens common mode feed forward circuit, and make the first numerical model analysis control type charge transfer circuit
Differential charge input terminal, the second numerical model analysis control type charge transfer circuit differential charge input terminal reconnect difference it is defeated
Enter endQ in,N , differential input endQ in,P ；
Complete it is above-mentioned after, calibration control control enter normal transmission mode；After entering normal transmission mode, calibration control
Device and detection processing circuit enter suspend mode.
Second common mode charge detection circuit includes the first electric charge detector, the second electric charge detector, third electric charge detector
And the 4th electric charge detector；
First electric charge detector, the 4th electric charge detector are separately connected differential charge output endQ out,p , fully differential charge it is defeated
OutletQ outKn ；The output end of first electric charge detector is connect with one end of sampling switch S1, the other end and electricity of sampling switch S1
Hold one end of C1 and one end connection of sampling switch S2, the output end of the other end of sampling switch S2 and the second electric charge detector
Connection, the input terminal and reference signal of the second electric charge detectorR pConnection, the input terminal and reference signal of third electric charge detector
The output end of Rn connection, third electric charge detector is connect with one end of sampling switch S3, the other end and capacitor of sampling switch S3
The output end of one end of C2 and one end connection of sampling switch S4, the other end of sampling switch S4 and the 4th electric charge detector connects
It connects, the other end of capacitor C1 is connect with the positive input terminal of one end of sampling switch S5 and fully-differential amplifier, and capacitor C2's is another
One end is connect with the negative input end of sampling switch S6 and fully-differential amplifier, the other end and sampling switch S5 of sampling switch S6
Other end connection, and another termination voltage VSet of the other end of sampling switch S5 and sampling switch S6；
First electric charge detector, the 4th electric charge detector, sampling switch S1, sampling switch S4 connection second clock Φ2, the
Two electric charge detectors, third electric charge detector, sampling switch S2, sampling switch S3, sampling switch S5 and sampling switch S6 connect
Meet the first clock Φ1, the first clock Φ1With second clock Φ2It is mutually non-overlapping.
Common mode feed forward circuit includes PMOS current mirroring circuit, Differential Input to, current-mirror bias circuit；
The PMOS current mirroring circuit includes PMOS tube M3 and PMOS tube M4, the gate terminal and PMOS tube of the PMOS tube M3
The drain electrode end of M3, the gate terminal of PMOS tube M4 are connected, and the source terminal interconnection of PMOS tube M3, PMOS tube M4 are followed by power supply；
The gate terminal of PMOS tube M3, the drain electrode end of PMOS tube M3 are connected with the drain electrode end for resetting metal-oxide-semiconductor Ms1, the drain electrode of PMOS tube M4
It holds and is connected with the drain electrode end for resetting metal-oxide-semiconductor Ms2；The gate terminal for resetting metal-oxide-semiconductor Ms1 and the gate terminal for resetting metal-oxide-semiconductor Ms2 are connected to
Second clock Ф2；
Differential Input is to including metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2；The drain electrode end of the metal-oxide-semiconductor M1 and the source for resetting metal-oxide-semiconductor Ms1
It is extreme to be connected；The drain electrode end of the metal-oxide-semiconductor M2 is connected with the source terminal for resetting metal-oxide-semiconductor Ms2；The source terminal of the metal-oxide-semiconductor M1 is logical
It crosses source resistance R1 to be connected with the drain electrode end of metal-oxide-semiconductor M5, and the source terminal of metal-oxide-semiconductor M2 passes through source resistance R2's and metal-oxide-semiconductor M5
Drain electrode end is connected；The gate terminal of metal-oxide-semiconductor M5 is connected with the drain electrode end of the gate terminal of metal-oxide-semiconductor M8, metal-oxide-semiconductor M8, the source electrode of metal-oxide-semiconductor M5
End is connect with the drain electrode end of metal-oxide-semiconductor M6, the drain electrode end ground connection of metal-oxide-semiconductor M6, the source terminal ground connection of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M6
Extremely it is connected with the drain electrode end of the gate terminal of metal-oxide-semiconductor M7, metal-oxide-semiconductor M7, source terminal, the source terminal of metal-oxide-semiconductor M8 of metal-oxide-semiconductor M7 is equal
Ground connection.The drain electrode of metal-oxide-semiconductor M8 terminates bias current Ib1, and the drain electrode of metal-oxide-semiconductor M7 terminates bias current Ib2；
The gate terminal of metal-oxide-semiconductor M1 receives the first output error signal CM, and the gate terminal of metal-oxide-semiconductor M2 and the second output error are believed
Number CMn is connected, and the drain electrode end of metal-oxide-semiconductor M2 is connect with the source terminal of reset metal-oxide-semiconductor Ms2.
Advantages of the present invention: it can automatically detect the common mode charge error in charge-domain pipelined analog-digital converter, and right
The common mode charge error is accurately compensated, to overcome common mode charge error to move existing charge-domain pipelined analog-digital converter
The limitation of state property energy, further increases the conversion performance of existing charge-domain pipelined analog-digital converter.
Detailed description of the invention
Fig. 1 is the structure principle chart for the fully differential charge transfer circuit that the present invention accurately controls common mode charge amount.
Fig. 2 is a kind of realization principle figure of numerical model analysis control type charge transfer circuit in the present invention.
Fig. 3 is the circuit diagram of common mode charge detection circuit in the present invention.
Fig. 4 is the circuit diagram of common mode feed forward circuit in the present invention.
Fig. 5 is the circuit diagram of common mode adjustment circuit in the present invention.
Fig. 6 is the circuit diagram of detection processing circuit in the present invention.
Description of symbols: the first common mode charge of 1- detection circuit, 2- common mode feed forward circuit, the control of the first numerical model analysis of 3-
Type charge transfer circuit, 4- the second numerical model analysis control type charge transfer circuit, the second common mode charge of 5- detection circuit, 6- common mode
The substantially enhanced charge of charge adjustment circuit, 7- detection processing circuit, 8-M adjustment registers, 9- controller calibration, 10- passes
Transmit electricity road, 11- mirror image control circuit, the first electric charge detector of 12-, the second electric charge detector of 13-, 14- third electric charge detector,
The 4th electric charge detector of 15-, 16- Full differential operational amplifier, 17- output buffering operational amplifier, 18-DAC module, 19-K:1
16 digit counters that selector, the first 8:1 selector of 20-, 21- tape pulse are swallowed, 22-16:1 selector, 23- signal fusing electricity
Road, 24- read-out controller, 25- window signal generator, 26- scanning sequence generator, 27- swallows control circuit, 28- resets
Signal generating circuit, the first 8:1 selector of 29-, 30-16 digit counter and 31- error amplifier.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
, BCT at different levels the error of the common mode charge of each level production line grade circuit of charge-domain ADC is from three aspects: 1)
The pass break-point voltage of (numerical model analysis control type charge transfer circuit) changes bring common mode charge error with PVT；2), input is total
Common mode charge error caused by mould level fluctuation；3), the capacitance mismatch in each assembly line grade circuit and reference voltage become with PVT
Common mode charge fluctuating error caused by changing.
As shown in Figure 1, the present invention includes the first common mode charge detection circuit 1, common mode feed forward circuit 2, the first numerical model analysis
Control type charge transfer circuit 3, the second common mode charge detection circuit 5, is total to second numerical model analysis control type charge transfer circuit 4
Mould charge adjustment circuit 6, detection processing circuit 7, M adjustment registers 8 and controller calibration 9, wherein M are being greater than 1 just
Integer.
Specifically, differential input endQ in,p , differential input endQ in,n It is connected respectively to the first common mode charge detection circuit 1
The output end of differential charge input terminal, the first common mode charge detection circuit 1 is connected to the input terminal of common mode feed forward circuit 2；Common mode
The output end Vf of feed forward circuit 2 is connected to the first common mode adjustment letter of the first numerical model analysis control type charge transfer circuit 3 simultaneously
The first common mode adjustment signal input terminal FF of number input terminal FF, the second numerical model analysis control type charge transfer circuit 4；First digital-to-analogue
The output end of the output end, the second numerical model analysis control type charge transfer circuit 4 that mix control type charge transfer circuit 3 connects respectively
It is connected to the differential charge input terminal of the second common mode charge detection circuit 5, the output end of the second common mode charge detection circuit 5 is connected to
The input terminal of detection processing circuit 7；The output end of detection processing circuit 7 is connected to the detection signal input part of controller calibration 9；
The position the M compensation codes output end of controller calibration 9 is connected to the signal input part of M adjustment registers 8, M adjustment registers 8
Signal output end is connected to the control signal input of common mode charge adjustment circuit 6；The control signal of common mode charge adjustment circuit 6
Output end is connected to the second common mode adjustment signal input terminal FB of the first numerical model analysis control type charge transfer circuit 3, the simultaneously
Second common mode adjustment signal input terminal FB of two numerical model analysis control type charge transfer circuits 4.
In the embodiment of the present invention, there are two types of operating modes, as calibration mode and normal transmission mode for foregoing circuit tool.When
When start-up operation, calibration mode is initially entered, controller calibration 9 is by the first modulus mixing control type charge transfer circuit 3, second
The corresponding differential input end of numerical model analysis control type charge transfer circuit 4 is connected to input reference voltage；And then first is opened
Common mode charge detection circuit 1 and the second common mode charge detection circuit 5, the output of the second common mode charge detection circuit 5 successively by
Detection processing circuit 7 carries out statistical disposition, then carries out operation by controller calibration 9, carries out assignment to M adjustment registers 8；
The each operation of controller calibration 9 only generates 1 bit value, therefore the assignment controller calibration 9 for completing 1 M adjustment register 8 needs
It calculates M times, the way of search that M operation follows is binary search mode；Common mode charge adjustment circuit 6 is adjusted according to M
The M digit numeric code of register 8 generates offset voltage Vadj, and under the action of the offset voltage Vadj, the first digital-to-analogue of control is mixed
Close control type charge transfer circuit 3, the corresponding output common mode quantity of electric charge of the second numerical model analysis control type charge transfer circuit 4；Most
Afterwards, controller calibration 9 opens common mode feed forward circuit 2, and makes the differential electrical of the first numerical model analysis control type charge transfer circuit 3
The differential charge input terminal reconnect differential input end of lotus input terminal, the second numerical model analysis control type charge transfer circuit 4Q in,N , differential input endQ in,P .At this point, completing calibration, i.e., calibration mode terminates, into normal transmission mode.Entering normal pass
After defeated mode, controller calibration 9 and detection processing circuit 7 enter suspend mode to reduce power consumption.It is being in normal mode of operation
When, the first common mode charge detection circuit 1 and common mode feed forward circuit 2 are in running order.
As shown in Fig. 2, the first numerical model analysis control type charge transfer circuit 3 and the second numerical model analysis control type charge transmit
Circuit 4 uses identical circuit structure, and the first numerical model analysis control type charge transfer circuit 3 includes substantially enhanced charge
Transmission circuit 10, mirror image control circuit 11, error amplifier 31 and common mode feedforward adjustment NMOS tube M1FF。
Specifically, substantially enhanced charge transfer circuit 10 is by charge pass transistor MT, NMOS tube M21, NMOS tube M22With
PMOS tube M23Composition；NMOS tube M21Source electrode ground connection, NMOS tube M21Grid connect input charge signalQ IN , NMOS tube M21Leakage
Pole meets NMOS tube M22Source electrode and common mode feedforward adjustment NMOS tube M1FFDrain electrode, NMOS tube M21Substrate connect control voltage VBD；
NMOS tube M22Drain electrode meet charge pass transistor MTGrid and PMOS tube M23Drain electrode；PMOS tube M23Source electrode and PMOS
Pipe M23Substrate connect supply voltage；Charge pass transistor MTSource electrode connect with the gate terminal of NMOS tube M21, charge transmission
Transistor MTDrain electrode be output charge signalQ OUT ；Common mode feedforward adjustment NMOS tube M1FFSource electrode and common mode feedforward adjustment NMOS
Pipe M1FFSubstrate be grounded, common mode feedforward adjustment NMOS tube M1FFGrid meet the first common mode adjustment signal Vf.Described first is total
Mould adjustment signal Vf is exported by common mode feed forward circuit 2.
The mirror image control circuit 11 is by NMOS tube M21R, NMOS tube M22RWith PMOS tube M23RComposition；NMOS tube M21RSource
Pole ground connection, NMOS tube M21RGrid meet the positive input signal end of error amplifier 31, NMOS tube M21RDrain electrode meet NMOS tube M22R
Source electrode, NMOS tube M21RSubstrate connect control voltage VBD；NMOS tube M22RDrain electrode meet PMOS tube M23RDrain electrode；PMOS tube M23R
Source electrode and PMOS tube M23RSubstrate connect supply voltage；The negative input signal of error amplifier 31 terminates offset voltage Vadj,
The output signal end of error amplifier is that substrate meets control voltage VBD。
As shown in figure 3, the first common mode charge detection circuit 1 and the second common mode charge detection circuit 5 use identical circuit
Structure, wherein the first common mode charge detection circuit 1 is realized using fully differential structure.It is with the second common mode charge detection circuit 5
Example, the second common mode charge detection circuit 5 include the first electric charge detector 12, the second electric charge detector 13, third electric charge detector
14 and the 4th electric charge detector 15, the first electric charge detector 12, the 4th electric charge detector 15 be separately connected differential charge output
EndQ out,p , fully differential charge output endQ outKn ；The output end of first electric charge detector 12 is connect with one end of sampling switch S1,
The other end of sampling switch S1 is connect with one end of one end of capacitor C1 and sampling switch S2, the other end of sampling switch S2 with
The output end of second electric charge detector 13 connects, the input terminal and reference signal of the second electric charge detector 13R pConnection, third electricity
The input terminal of lotus detector 14 is connect with reference signal Rn, the output end of third electric charge detector 14 and one end of sampling switch S3
Connection, the other end of sampling switch S3 are connect with one end of one end of capacitor C2 and sampling switch S4, and sampling switch S4's is another
One end is connect with the output end of the 4th electric charge detector 15, the other end of capacitor C1 and one end of sampling switch S5 and fully differential
The positive input terminal of amplifier 13 connects, the other end and sampling switch S6 of capacitor C2 and the negative input end of fully-differential amplifier 13
Connection, the other end of sampling switch S6 is connect with the other end of sampling switch S5, and the other end of sampling switch S5 and sampling
Another termination voltage VSet of switch S6.
First electric charge detector 12, the 4th electric charge detector 15, sampling switch S1, sampling switch S4 connection second clock
Φ2, the second electric charge detector 13, third electric charge detector 14, sampling switch S2, sampling switch S3, sampling switch S5 and adopt
Sample switch S6 the first clock of connection Φ1, the first clock Φ1With second clock Φ2It is mutually non-overlapping.
Specifically, for the sampling of charge signal, according to traditional switching capacity voltage sample, then MOS sampling switch
One end of pipe can be directly connected to differential charge memory node, once sampling switch other end is injected and is let out there are a charge
Channel is put, then stored charge can pass through MOS sampling switch pipe and sampling switch other end on differential charge memory node
Circuit occur charge share effect, make the charge on differential charge memory nodeQ outKp WithQ out,n It changes, so as to cause
Detection error.
To avoid the detection error, in the embodiment of the present invention, charge signal is detected by using electric charge detector,
Guarantee charge-storage node there is no charge injection and leakage path, realizes accurate sampling and amplification to charge signal.Right
Charge signalQ out,p , charge signalQ out,n And reference signalR p, reference signalR nIt is detected after obtaining voltage signal, is led to
It crosses corresponding sampling switch and capacitor C1, capacitor C2 is further sampled, obtain differential voltage signalV i+ andV i, warp
It crosses 16 zoom comparison of fully-differential amplifier and obtains the first output error signal CM and the second output error signal CMn.
The concrete principle figure of the 4th electric charge detector 15 is shown in dotted line frame in Fig. 3, is one by clock control
Source follower circuit, certainly, the first electric charge detector 12, the second electric charge detector 13, third electric charge detector 14 and the 4th electricity
Lotus detector 15 uses identical circuit structure.4th electric charge detector 15 includes NMOS tube M31, NMOS tube M32 and NMOS
The source terminal of pipe M33, NMOS tube M31 are grounded, and the drain electrode end of NMOS tube M31 is connect with the source terminal of NMOS tube M32, NMOS tube
The drain electrode end of M32 is connect with the source terminal of NMOS tube M33, and the drain electrode end of NMOS tube M33 connects to power supply, the grid of NMOS tube M31
It is extremely connect with bias voltage Vb, the gate terminal and second clock Ф of NMOS tube M322The gate terminal of connection, NMOS tube M33 receives
Charge signalQ Out, n .The drain electrode end of NMOS tube M31 forms output end after connecting with the source terminal of NMOS tube M22.
In the embodiment of the present invention, as second clock Ф2When being high, the 4th electric charge detector 15 is on normal detection shape
State, charge signalQ out,n Variation will be responded by source follower, obtain output voltage signalV outn；As second clock Ф2
When being low, the 4th electric charge detector 15 is off off position, output voltage signalV outnIt is pulled to ground.In view of source with
With the pressure drop that device can generate, NMOS tube M33 is realized using Low threshold NMOS tube.For fully-differential amplifier 13, use is existing
Highly developed differential-voltage comparator can be completed.
As shown in figure 4, being a kind of realization circuit diagram of common mode feed forward circuit 2 of the present invention, the common mode feed forward circuit 2
Including PMOS current mirroring circuit, Differential Input to, current-mirror bias circuit.
The PMOS current mirroring circuit includes PMOS tube M3 and PMOS tube M4, the gate terminal and PMOS tube of the PMOS tube M3
The drain electrode end of M3, the gate terminal of PMOS tube M4 are connected, and the source terminal interconnection of PMOS tube M3, PMOS tube M4 are followed by power supply；
The gate terminal of PMOS tube M3, the drain electrode end of PMOS tube M3 are connected with the drain electrode end for resetting metal-oxide-semiconductor Ms1, the drain electrode of PMOS tube M4
It holds and is connected with the drain electrode end for resetting metal-oxide-semiconductor Ms2；The gate terminal for resetting metal-oxide-semiconductor Ms1 and the gate terminal for resetting metal-oxide-semiconductor Ms2 are connected to
Second clock Ф2。
Differential Input is to including metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2；The drain electrode end of the metal-oxide-semiconductor M1 and the source for resetting metal-oxide-semiconductor Ms1
It is extreme to be connected；The drain electrode end of the metal-oxide-semiconductor M2 is connected with the source terminal for resetting metal-oxide-semiconductor Ms2；The source terminal of the metal-oxide-semiconductor M1 is logical
It crosses source resistance R1 to be connected with the drain electrode end of metal-oxide-semiconductor M5, and the source terminal of metal-oxide-semiconductor M2 passes through source resistance R2's and metal-oxide-semiconductor M5
Drain electrode end is connected；The gate terminal of metal-oxide-semiconductor M5 is connected with the drain electrode end of the gate terminal of metal-oxide-semiconductor M8, metal-oxide-semiconductor M8, the source electrode of metal-oxide-semiconductor M5
End is connect with the drain electrode end of metal-oxide-semiconductor M6, the drain electrode end ground connection of metal-oxide-semiconductor M6, the source terminal ground connection of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M6
Extremely it is connected with the drain electrode end of the gate terminal of metal-oxide-semiconductor M7, metal-oxide-semiconductor M7, source terminal, the source terminal of metal-oxide-semiconductor M8 of metal-oxide-semiconductor M7 is equal
Ground connection.The drain electrode of metal-oxide-semiconductor M8 terminates bias current Ib1, and the drain electrode of metal-oxide-semiconductor M7 terminates bias current Ib2.
The gate terminal of metal-oxide-semiconductor M1 receives the first output error signal CM, and the gate terminal of metal-oxide-semiconductor M2 and the second output error are believed
Number CMn is connected, and the drain electrode end of metal-oxide-semiconductor M2 is connect with the source terminal of reset metal-oxide-semiconductor Ms2.In the embodiment of the present invention, input difference pair
Metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 is operated in linear zone, and metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 form NMOS current mirror, metal-oxide-semiconductor M7 and metal-oxide-semiconductor
M8 forms NMOS electric current.
Detection processing circuit 7 selects the result of the second common mode charge detection circuit 5, then according to the processing of setting
Method is handled, and is stored the result into its internal register.When common mode is calibrated, controller calibration 9 is posted for two in reading
The value of storage, by the value of marking signal SGN, come judge common-mode point detected common mode charge height, thus adjust
Corresponding control voltage, to achieve the purpose that common mode charge is calibrated.
As shown in figure 5, the circuit diagram of common mode charge adjustment circuit 7,7 basic structure of common mode charge adjustment circuit is similar
Operational amplifier 17, voltage output tune are buffered in a LDO circuit, including a working state control switch M51, an output
Whole PMOS tube M50 adjusts the M-bit DAC module of output voltage for carrying out the resistance string of partial pressure output offset voltage VadjK
18, for the capacitor C52 for carrying out decoupling filtering to outputting reference signal VadjK, for buffering operational amplifier 17 to output
Stablize the resistance R51 and capacitor C51 of compensation.
When initially entering normal mode of operation, control signal sets 1, and working state control switch M51 conducting is slow due to exporting
The negative feedback of operational amplifier 17 is rushed, reference voltage VREF is under the control of voltage output adjustment PMOS tube M50 through resistance
String partial pressure obtains initial voltage output VR (0), while DAC module 18 can also generate an adjustment electric current Ic to ground, adjusts
Whole electric current Ic flows through least significant end resistance to ground, and the voltage of Yi ⊿ V=Ic × R324 can be thus superimposed on the resistance, defeated
Voltage VR=VR (0)+⊿ V of reference signal output circuit is arrived out.After VR changes, according to electric resistance partial pressure relationship, output compensation
Voltage VadjK can accordingly increase the voltage of Yi ⊿ V, therefore, as long as M adjustment codes of control can realize change output base
The purpose of quasi- voltage.DAC module 26 generates adjustment electric current Ic according to M adjustment codes, and the specific process for generating adjustment electric current Ic is
Known to those skilled in the art, details are not described herein again.For other road common mode adjustment circuits 7, above description can be referred to, this
Place repeats no more.
As shown in fig. 6, being the functional block diagram of detection processing circuit 7 of the present invention, detection processing circuit 7 includes 16 meters
Count 16 digit counter, 21, K:1 selectors 19, the first 8:1 selector 29, the 2nd 8:1 choosing that 30, tape pulses of device are swallowed
Device 20 is selected, 16:1 selector 22, one are swallowed the scanning sequence of reset signal generating circuit 28, one of pulse control circuit 27, one
26, one, column generator, 25, one, window signal generator signal contrast circuit 23 and a read-out controller 24.
Specifically: input reset signal is connected to the first reset terminal of 16 digit counters 21 that tape pulse is swallowed and resets letter
The reset terminal of number generation circuit 28；K input terminal of K:1 selector 19 is connected respectively to the second common mode charge detection circuit 5
Output end, the output end of K:1 selector 19 are connected to the data input pin of the 2nd 8:1 selector 20；2nd 8:1 selector 20
Control signal is connected to common mode selection control signal, and the enable end of the 2nd 8:1 selector 20 is connected to tape pulse is swallowed 16
Second reset terminal of digit counter 21；The third input terminal for 16 digit counters 21 that tape pulse is swallowed, which is connected to, swallows pulse control
4th input terminal of the output end of circuit 27,16 digit counters 21 that tape pulse is swallowed is connected to input clock, and tape pulse is swallowed
16 digit counters 21 output end be connected to 16:1 selector 22 data input pin and read-out controller 24 data input
End；The control signal input of 16:1 selector 22 is connected to the output end of scanning sequence generator 26,16:1 selector 22
Data output end is connected to the first data input pin of signal contrast circuit 23；Second data input pin of signal contrast circuit 23
It is connected to the output end of window signal generator 25, output end, that is, output identification signal SGN of signal contrast circuit 18；Read control
18 output ends of device processed, that is, output status signal B3；The output end of reset signal generating circuit 28 is connected to swallows pulse control simultaneously
The reset of the reset signal input terminal of circuit 27 processed, the reset signal input terminal of scanning sequence generator 26 and 16 digit counters 30
Signal input part；The first input end of 16 digit counters 30 is connected to input clock, and low 4 output ends of 16 digit counters 30 connect
It is connected to the control signal input for swallowing pulse control circuit 27, the most-significant byte output end of 16 digit counters 30 is connected to the first 8:1
23 data signal input of selector；The output end of first 8:1 selector 23 is connected to the data of reset signal generating circuit 28
Input terminal.
16 digit counters 30 are basic counter, and when inputting reset signal becomes 1 from 0,16 digit counters 30 are started counting.
The output of its most-significant byte is used to control reset generation circuit 22 after selecting by the first 8:1 selector 29, as long as the first 8:1 selector
29 output is high level, and reset signal generating circuit 28 is output reset signal, and above-mentioned reset signal is reset signal
Generation circuit 28 is generated and is exported；Pulse control circuit 27 is swallowed in low 4 inputs of 16 digit counters 30.
16 digit counters 21 that tape pulse is swallowed will be in count status, it is necessary to while meeting following three conditions: 1), again
Position signal is high level；2) control wave, is swallowed to be between high period；3), the signal that the 2nd 8:1 selector 20 is selected
For high level.When some signal that the 2nd 8:1 selector 20 is selected is high level, some common mode charge of explanation detects electricity
The output of road 4 is height.
2 job order of detection processing circuit is as follows: 1), reset signal from 0 become 1, start 16 digit counters 30；
2) it, swallows pulse control circuit 27 also to start to work, output one divides with master clock 16, and the clock of duty ratio position 0.5；,
3), 16 digit counters 21 that tape pulse is swallowed start counting, but the numerical value of 16 counters 15 that the tape pulse is swallowed is 16
The 1/16(of 30 count value of digit counter is swallowed due to pulse to be caused)；4) (the first 8:1 selector after, 16 digit counters 30 meter is full
29 outputs become high level), 28 output reset signal of reset signal generating circuit and swallows pulse control electricity at 16 digit counters 30
Road 27 is reset, and exports low level；5), scanning sequence generator 26 is started to work, and exports 4 bit scan pulses, it is sequentially output 0 ~
15 totally 16 states, so that each all scanned output in 16 digit counters 21 that tape pulse is swallowed, and read in four times
Enter into Read Controller 24；6), window signal generator 25 generates a watch window signal, the signal and scanning sequence phase
Cooperation, for judging whether a certain position is high level in 16 digit counters 21 that tape pulse is swallowed, if 16 that tape pulse is swallowed
That chosen in counter 21 by window signal is high level, then marking signal SGN is high level, otherwise is low level.
16 digit counters 21 that 16 digit counters 30, tape pulse are swallowed, K:1 selector 19, the first 8:1 selector 29, the 2nd 8:1 selection
Device 20,16:1 selector 22 swallow pulse control circuit 27, reset signal generating circuit 28, scanning sequence generator 26, window
Signal generator 25, signal contrast circuit 23 and read-out controller 24 can use existing common circuit structure, specifically
For known to those skilled in the art, details are not described herein again.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (1)
1. a kind of fully differential charge transfer circuit for accurately controlling common mode charge amount, including the first numerical model analysis control type charge
Transmission circuit (3) and the second numerical model analysis control type charge transfer circuit (4)；It is characterized in that: further including the first common mode charge
Detection circuit (1), common mode feed forward circuit (2), the second common mode charge detection circuit (5), detection processing circuit (7), common mode charge
Adjustment circuit (6), M adjustment registers (8) and controller calibration (9)；
Differential input endQ in,p , differential input endQ in,n The differential charge for being connected respectively to the first common mode charge detection circuit (1) is defeated
Enter end, the output end of the first common mode charge detection circuit (1) is connected to the input terminal of common mode feed forward circuit (2)；It is fed before common mode
The output end Vf on road (2) is connected to the first common mode adjustment signal of the first numerical model analysis control type charge transfer circuit (3) simultaneously
The first common mode adjustment signal input terminal FF of input terminal FF, the second numerical model analysis control type charge transfer circuit (4)；First digital-to-analogue
Mix the output end of control type charge transfer circuit (3), the output end point of the second numerical model analysis control type charge transfer circuit (4)
It is not connected to the differential charge input terminal of the second common mode charge detection circuit (5), the output of the second common mode charge detection circuit (5)
End is connected to the input terminal of detection processing circuit (7)；The output end of detection processing circuit (7) is connected to controller calibration (9)
Detect signal input part；The position the M compensation codes output end of controller calibration (9) is connected to the signal input of M adjustment registers (8)
End, the signal output end of M adjustment registers (8) are connected to the control signal input of common mode charge adjustment circuit (6)；Common mode
The control signal output of charge adjustment circuit (6) is connected to the first numerical model analysis control type charge transfer circuit (3) simultaneously
The second common mode adjustment signal of second common mode adjustment signal input terminal FB, the second numerical model analysis control type charge transfer circuit (4)
Input terminal FB；
Controller calibration (9) can control into calibration mode or normal mode of operation；
Calibration mode is initially entered, controller calibration (9) counts the first numerical model analysis control type charge transfer circuit (3), second
The corresponding input terminal IN of mould mixing control type charge transfer circuit (4) is connected to input reference voltage；And then it is total to open first
Mould charge detection circuit (1) and the second common mode charge detection circuit (5), the output of the second common mode charge detection circuit (5) according to
Secondary detected processing circuit (7) carries out statistical disposition, then operation is carried out by controller calibration (9), to M adjustment registers
(8) assignment is carried out；Common mode charge adjustment circuit (6) generates offset voltage according to the M digit numeric code of M adjustment registers (8)
Vadj, under the action of the offset voltage Vadj, the first numerical model analysis control type charge transfer circuit (3) of control, the second number
The corresponding output common mode quantity of electric charge of mould mixing control type charge transfer circuit (4)；Finally, before controller calibration (9) opens common mode
Current feed circuit (2), and make the input terminal IN of the first numerical model analysis control type charge transfer circuit (3), the control of the second numerical model analysis
The input terminal IN of type charge transfer circuit (4) reconnects differential input endQ in,n , differential input endQ in,p ；
Complete it is above-mentioned after, controller calibration (9) control enter normal transmission mode；After entering normal transmission mode, calibration control
Device (9) processed and detection processing circuit (7) enter suspend mode；
Second common mode charge detection circuit (5) includes the first electric charge detector (12), the second electric charge detector (13), third charge
Detector (14) and the 4th electric charge detector (15)；
First electric charge detector (12), the 4th electric charge detector (15) are separately connected differential charge output endQ out,p , fully differential electricity
Lotus output endQ out,n ；The output end of first electric charge detector (12) is connect with one end of sampling switch S1, and sampling switch S1's is another
One end is connect with one end of one end of capacitor C1 and sampling switch S2, the other end of sampling switch S2 and the second electric charge detector
(13) output end connection, the input terminal and reference signal of the second electric charge detector (13)R pConnection, third electric charge detector
(14) input terminal is connect with reference signal Rn, and the output end of third electric charge detector (14) and one end of sampling switch S3 connect
It connects, the other end of sampling switch S3 is connect with one end of one end of capacitor C2 and sampling switch S4, and sampling switch S4's is another
End is connect with the output end of the 4th electric charge detector (15), the other end of capacitor C1 and one end of sampling switch S5 and fully differential
The positive input terminal of amplifier (16) connects, and bearing for the other end of capacitor C2 and sampling switch S6 and fully-differential amplifier (16) is defeated
Enter end connection, the other end of sampling switch S6 connect with the other end of sampling switch S5, and the other end of sampling switch S5 and
Another termination voltage VSet of sampling switch S6；
First electric charge detector (12), the 4th electric charge detector (15), sampling switch S1, sampling switch S4 connection second clock
Φ2, the second electric charge detector (13), third electric charge detector (14), sampling switch S2, sampling switch S3, sampling switch S5 with
And sampling switch S6 the first clock of connection Φ1, the first clock Φ1With second clock Φ2It is mutually non-overlapping；
Common mode feed forward circuit (2) includes PMOS current mirroring circuit, Differential Input to, current-mirror bias circuit；
The PMOS current mirroring circuit includes the gate terminal and PMOS tube M3 of PMOS tube M3 and PMOS tube M4, the PMOS tube M3
Drain electrode end, the gate terminal of PMOS tube M4 are connected, and the source terminal interconnection of PMOS tube M3, PMOS tube M4 are followed by power supply；PMOS tube
The gate terminal of M3, PMOS tube M3 drain electrode end be connected with the drain electrode end for resetting metal-oxide-semiconductor Ms1, the drain electrode end of PMOS tube M4 with answer
The drain electrode end of position metal-oxide-semiconductor Ms2 is connected；When the gate terminal for resetting metal-oxide-semiconductor Ms1 and the gate terminal for resetting metal-oxide-semiconductor Ms2 are connected to second
Clock Ф1；
Differential Input is to including metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2；The drain electrode end of the metal-oxide-semiconductor M1 and the source terminal for resetting metal-oxide-semiconductor Ms1
It is connected；The drain electrode end of the metal-oxide-semiconductor M2 is connected with the source terminal for resetting metal-oxide-semiconductor Ms2；The source terminal of the metal-oxide-semiconductor M1 passes through source
Electrode resistance R1 is connected with the drain electrode end of metal-oxide-semiconductor M5, and the source terminal of metal-oxide-semiconductor M2 passes through the drain electrode of source resistance R2 and metal-oxide-semiconductor M5
End is connected；The gate terminal of metal-oxide-semiconductor M5 is connected with the drain electrode end of the gate terminal of metal-oxide-semiconductor M8, metal-oxide-semiconductor M8, the source terminal of metal-oxide-semiconductor M5 with
The drain electrode end of metal-oxide-semiconductor M6 connects, the drain electrode end ground connection of metal-oxide-semiconductor M6, the source terminal ground connection of metal-oxide-semiconductor M8, the gate terminal of metal-oxide-semiconductor M6
It is connected with the drain electrode end of the gate terminal of metal-oxide-semiconductor M7, metal-oxide-semiconductor M7, the source terminal of metal-oxide-semiconductor M7, the source terminal of metal-oxide-semiconductor M8 are grounded；
The drain electrode of metal-oxide-semiconductor M8 terminates bias current Ib1, and the drain electrode of metal-oxide-semiconductor M7 terminates bias current Ib2；
The gate terminal of metal-oxide-semiconductor M1 receives the first output error signal CM, the gate terminal of metal-oxide-semiconductor M2 and the second output error signal
CMn is connected, and the drain electrode end of metal-oxide-semiconductor M2 is connect with the source terminal for resetting metal-oxide-semiconductor Ms2.
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| CN104092462B (en) * | 2014-06-17 | 2017-02-15 | 中国电子科技集团公司第五十八研究所 | Charge coupling production line analog-digital converter having digital background calibration function |
| CN104038225B (en) * | 2014-06-17 | 2017-04-19 | 中国电子科技集团公司第五十八研究所 | Charge coupling production line analog-digital converter having self-adaption error calibration function |
| CN104270152B (en) * | 2014-10-13 | 2017-12-22 | 中国电子科技集团公司第五十八研究所 | The insensitive common mode charge control devices of PVT for charge coupling assembly line analog to digital converter |
| CN108141203B (en) * | 2015-09-29 | 2021-11-30 | 美高森美半导体无限责任公司 | Noise reduction in non-linear signal processing |
| CN106656183B (en) * | 2016-12-20 | 2020-03-31 | 中国电子科技集团公司第五十八研究所 | Input common-mode error feedforward compensation circuit of pipeline analog-to-digital converter |
| US9755655B1 (en) * | 2017-03-08 | 2017-09-05 | Xilinx, Inc. | Dynamic quantizers having multiple reset levels |
| CN106953637B (en) * | 2017-03-09 | 2020-03-27 | 黄山学院 | Charge domain amplitude error calibration circuit and DDS circuit adopting same |
| CN107241098B (en) * | 2017-05-24 | 2020-10-16 | 东南大学 | Offset calibration circuit of comparator in asynchronous successive approximation type analog-to-digital converter |
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