CN107861304A - Array base palte, the preparation method of array base palte and display device - Google Patents
Array base palte, the preparation method of array base palte and display device Download PDFInfo
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- CN107861304A CN107861304A CN201711297517.1A CN201711297517A CN107861304A CN 107861304 A CN107861304 A CN 107861304A CN 201711297517 A CN201711297517 A CN 201711297517A CN 107861304 A CN107861304 A CN 107861304A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
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- Thin Film Transistor (AREA)
Abstract
A kind of array base palte, including substrate and the grid line being arranged on substrate, data wire, grid line intersects to set with data wire forms pixel cell arranged in arrays, oxide thin film transistor is provided with each pixel cell, pixel electrode, public electrode and the first insulating barrier between pixel electrode and public electrode, wherein, pixel electrode in adjacent pixel unit is inverted each other with public electrode, pixel electrode in each pixel cell is connected by corresponding oxide thin film transistor with grid line and data wire, public electrode in each pixel cell is connected to same common signal line.The present invention also provides the preparation method and display device of a kind of array base palte.Pixel electrode in the present invention in adjacent pixel unit is inverted each other with public electrode, and the public electrode in each pixel cell is connected to same common signal line, can be inverted with frame and be realized dot inversion, can be reduced power consumption simultaneously, be improved image quality.
Description
Technical field
The present invention relates to display technology field, especially with regard to a kind of array base palte, the preparation method of array base palte and aobvious
Show device.
Background technology
As electronic product is towards light, thin, miniaturization fast development, various portable electric products are nearly all with liquid crystal
Show that device (Liquid Crystal Display, LCD) is used as display panel, particularly in shot with video-corder, notebook computer, platform
On the products such as formula computer, intelligent television, mobile terminal or personal digital assistant device, liquid crystal display has been important is grouped
Part.
During the display of liquid crystal display, it is constant that the driving voltage of liquid crystal molecule can not be fixed on some value, no
Then because positive and negative charge gathers polarization phenomena can occur for liquid crystal molecule, gradually lose optically-active characteristic.Therefore, in order to avoid liquid crystal
The characteristic of molecule is destroyed, and the driving voltage of liquid crystal molecule must carry out reversal, when carrying out reversal upper and lower two
Layer electrode pressure difference absolute value be fixed, the GTG showed is the same, but liquid crystal molecule steering completely on the contrary, so as to
Cause the movement of positive and negative charge accumulation locations on liquid crystal molecule, that is, cause Dipole moment to change, prevent liquid crystal molecule from polarizing.It is common
Reversal mode have four kinds：Frame reversion, row reversion, column inversion and dot inversion, wherein, frame reversion refers to be shown generally at
One frame is refreshed by positive voltage, then next frame is refreshed by negative voltage, and row reversion refers to that two field picture odd-numbered line in previous frame adds just
Voltage, even number line add negative voltage, then the polarity of voltage of parity rows exchanges during next frame, and the reversal process and row of column inversion are anti-
Turn similar, dot inversion is the polarity of voltage of the neighbor pixel in each two field picture on the contrary, dot inversion mode is advantageous to eliminate friendship
Crosstalk and film flicker are pitched, thus picture quality is best, but because dot inversion is inverted using every 2 points as a unit, relatively
The power consumption of other mapping modes is higher.
The content of the invention
, can be simultaneously it is an object of the invention to provide a kind of array base palte, the preparation method of array base palte and display device
Reduce power consumption, improve image quality.
The present invention provides a kind of array base palte, and the array base palte includes the grid of substrate and setting on the substrate
Line, data wire, the grid line intersects to set with the data wire forms pixel cell arranged in arrays, each pixel list
Oxide thin film transistor, pixel electrode, public electrode and positioned at the pixel electrode and the common electrical are provided with member
The first insulating barrier between pole, wherein, the pixel electrode in adjacent pixel unit is inverted each other respectively with public electrode, each pixel
Pixel electrode in unit is connected by corresponding oxide thin film transistor with the grid line and the data wire, each pixel list
Public electrode in member is connected to same common signal line.
In one embodiment, the side of the substrate is sequentially provided with the first metal layer, gate insulation layer, semiconductor channel
Layer, second metal layer, the second insulating barrier, first transparency electrode layer, first insulating barrier and second transparency electrode layer, described
Grid formed with the grid line and the oxide thin film transistor in one metal level, formed in the second metal layer
State data wire and the common signal line, it is exhausted formed with being located at described first in each pixel cell in the first transparency electrode layer
Pixel electrode and public electrode below edge layer, in the second transparency electrode layer formed with each pixel cell positioned at described the
Pixel electrode and public electrode above one insulating barrier.
In one embodiment, the public electrode in the first transparency electrode layer and pixel electrode are in matrix form staggered row
It is interconnected between row and public electrode, the position of the public electrode in the second transparency electrode layer and the described first transparent electricity
The position of pixel electrode in the layer of pole corresponds, the position and described first of the pixel electrode in the second transparency electrode layer
The position of public electrode in transparent electrode layer corresponds, and the public electrode in the second transparency electrode layer is interconnected.
In one embodiment, second insulating barrier is provided with first in the opening position of the corresponding common signal line and led to
Hole, the public electrode in the first transparency electrode layer is interconnected and passes through the first through hole to be connected with the common signal line
Connect, first insulating barrier is formed through second successively with opening position of second insulating barrier in the corresponding common signal line
Through hole, the public electrode in the second transparency electrode layer are interconnected and pass through second through hole and the common signal line
Connection.
In one embodiment, the public electrode in the first transparency electrode layer and pixel electrode are planar knot
Structure, public electrode and pixel electrode in the second transparency electrode layer are list structure.
In one embodiment, in the pixel electrode and public electrode of same pixel cell, positioned at first insulating barrier
The width of the electrode of lower section is less than the width of the electrode above first insulating barrier, and on first insulating barrier
The data wire of the projection covering both sides corresponding position of the electrode of side in the direction of the width.
In one embodiment, the slit number of the public electrode in the second transparency electrode layer is more than positioned at described
The slit number of pixel electrode in second transparency electrode layer.
In one embodiment, source electrode and the leakage of the oxide thin film transistor are also formed with the second metal layer
Pole, the pixel electrode positioned at the first transparency electrode layer pass through the third through-hole through second insulating barrier and described second
Source electrode or drain electrode connection in metal level, the pixel electrode positioned at the second transparency electrode layer is by sequentially passing through described first
The fourth hole of insulating barrier and second insulating barrier connects with the source electrode in the second metal layer or drain electrode.
The present invention also provides a kind of preparation method of array base palte, including：
One substrate is provided；
The first metal layer of patterning is formed on the substrate, and the first metal layer includes grid line and sull
The grid of transistor；
Form gate insulation layer；
Form the semiconductor channel layer of patterning；
The second metal layer of patterning is formed, the second metal layer includes data wire, common signal line and the oxidation
The source electrode of thing thin film transistor (TFT) and drain electrode, the data wire intersect with the grid line；
The second insulating barrier of patterning is formed, second insulating barrier includes exposing the source electrode in the second metal layer
Or drain electrode through hole and expose the through hole of the common signal line in the second metal layer；
The first transparency electrode layer of patterning is formed, it is in the staggered public affairs of matrix form that the first transparency electrode layer, which includes,
Common electrode and pixel electrode, each public electrode are interconnected and by corresponding through holes and the common signal in the second metal layer
Line is connected, and each pixel electrode is connected by corresponding through hole with the source electrode in the second metal layer or drain electrode；
The first insulating barrier of patterning is formed, first insulating barrier includes exposing being located at institute in the second metal layer
The through hole of source electrode or drain electrode where stating each public electrode of first transparency electrode layer in pixel cell and expose described the
The through hole of common signal line in two metal levels；
The second transparency electrode layer of patterning is formed, it is in the staggered public affairs of matrix form that the second transparency electrode layer, which includes,
A pair of the position 1 of pixel electrode in common electrode and pixel electrode, the position of public electrode and the first transparency electrode layer
Should, the position of pixel electrode and the position of the public electrode in the first transparency electrode layer correspond, each public electrode phase
Intercommunicated and be connected by corresponding through hole with the common signal line, each pixel electrode passes through corresponding through hole and second gold medal
Belong to the source electrode in layer or drain electrode connection.
The present invention also provides a kind of display device, and the display device includes array base palte as described above or as described above
Array base palte preparation method made from array base palte.
The array base palte of the present invention, the preparation method and display device of array base palte, the interior setting of each pixel cell are aerobic
Compound thin film transistor (TFT), pixel electrode, public electrode and the first insulating barrier between pixel electrode and public electrode, its
In, the pixel electrode in adjacent pixel unit is inverted each other with public electrode, and the public electrode in each pixel cell is connected to
One common signal line, so as to realize dot inversion with frame reversion, power consumption can be reduced simultaneously, improves image quality.
Brief description of the drawings
Fig. 1 is the structural representation of array base palte in one embodiment of the invention.
Fig. 2 is the two neighboring pixel cell of array base palte cuing open at oxide thin film transistor in one embodiment of the invention
Face schematic diagram.
Fig. 3 A are direction of an electric field schematic diagram of first pixel cell in positive polarity frame in one embodiment of the invention.
Fig. 3 B are direction of an electric field schematic diagram of second pixel cell in positive polarity frame in one embodiment of the invention.
Fig. 3 C are direction of an electric field schematic diagram of first pixel cell in negative polarity frame in one embodiment of the invention.
Fig. 3 D are direction of an electric field schematic diagram of second pixel cell in negative polarity frame in one embodiment of the invention.
Fig. 4 is polarity schematic diagram of each pixel cell of array base palte in one embodiment of the invention under frame turn around condition.
Fig. 5 is the structural representation of first transparency electrode layer in one embodiment of the invention.
Fig. 6 is the structural representation of second transparency electrode layer in one embodiment of the invention.
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to embodiment, structure, feature and its effect of the present invention, describe in detail as after.
Fig. 1 is the structural representation of array base palte in one embodiment of the invention.Fig. 2 is array base in one embodiment of the invention
Diagrammatic cross-section of the two neighboring pixel cell of plate at oxide thin film transistor.As shown in Figures 1 and 2, battle array of the invention
Row substrate includes substrate 4 and the grid line (Gate line) 1, the data wire (Date line) 2 that are arranged on substrate 4, grid line 1 with
Data wire 2, which intersects to set, forms pixel cell arranged in arrays, and sull crystalline substance is provided with each pixel cell
Body pipe 6, pixel electrode, public electrode and the first insulating barrier 9 between pixel electrode and public electrode, wherein, it is adjacent
Pixel electrode in pixel cell is inverted each other respectively with public electrode, and the pixel electrode in each pixel cell passes through corresponding oxygen
Compound thin film transistor (TFT) 6 is connected with grid line 1 and data wire 2, and the public electrode in each pixel cell is connected to same common signal
Line.Herein, in a manner of pixel electrode 32 is located at the top of the first insulating barrier 9, public electrode 31 is located at the lower section of the first insulating barrier 9
The pixel electrode of composition is referred to as " the first pixel cell 3 ", with pixel electrode 52 positioned at the in the pixel cell of upper (Top pixel)
The public electrode that the mode that the lower section of one insulating barrier 9, public electrode 51 are located at the top of the first insulating barrier 9 is formed is at upper (Top com)
Pixel cell be referred to as " the second pixel cell 5 ", then the first pixel cell 3 be staggered with the second pixel cell 5 in matrix form
Mode be arranged on substrate 4, the pixel electrode 52 of the pixel cell 5 of pixel electrode 32 and second of the first pixel cell 3 is each other
It is inverted, the public electrode 51 of the public electrode 31 of the first pixel cell 3 and the second pixel cell 5 is inverted each other, the first pixel list
The public electrode 51 of the pixel cell 5 of public electrode 31 and second of member 3 is connected to same common signal line (not shown).
The structure of array base palte according to embodiments of the present invention, when carrying out frame reversion, it is assumed that each pixel during positive polarity frame
Electrode (pixel) plus 5V voltages, public electrode (com) add 0V voltages by same common signal line, each pixel electricity during negative polarity frame
Pole adds -5V voltages, and public electrode adds 0V voltages by same common signal line, then, the first pixel cell 3 (Top pixel) is just
Polarity frame obtains the electric field in direction as shown in Figure 3A, and obtains the electric field in direction as shown in Figure 3 C, the second pixel in negative polarity frame
Unit 5 (Top com) obtains the electric field in direction as shown in Figure 3 B in positive polarity frame, and obtains side as shown in Figure 3 D in negative polarity frame
To electric field.It can be seen that from direction of an electric field, direction of an electric field and second pixel cell 5 of first pixel cell 3 in positive polarity frame
Direction of an electric field in negative polarity frame is identical, and the first pixel cell 3 exists in the direction of an electric field of negative polarity frame and the second pixel cell 5
Direction of an electric field during positive polarity frame is identical, the direction of an electric field of the first pixel cell 3 and the second pixel cell 5 under identical polar frame
On the contrary, in this way, when the pixel electrode of each pixel cell all feeds malleation by data wire 2 and carries out frame reversion, such as with first
The direction of an electric field of pixel cell 3 is positive polarity, then the direction of an electric field of the second pixel cell 5 is negative polarity, due to the first pixel list
Member 3 is alternately arranged with the second pixel cell 5 in matrix form, see on the whole obtain it is as shown in Figure 4 in FFS (Fringe
Field Switching, fringe field switching technology) polarization state under framework, that is to say, that what data wire 2 was fed is that frame is anti-
Turn voltage, acquisition be dot inversion effect, so as to reduce power consumption, improve image quality.Further, since the first pixel cell 3
It is alternately arranged with the second pixel cell 5 in matrix form so that pixel electrode is exposed to towards liquid crystal alignment layer with public electrode
Side, for the exposure of only pixel electrode or the only structure of public electrode exposure, it is more conducive to ion and is moved along electrode, it is right
The image retention improvement of liquid crystal display is preferable.
Please continue to refer to Fig. 1 and Fig. 2, next the interlayer structure of the array base palte of the embodiment of the present invention is illustrated.
The side of substrate 4 is sequentially provided with the first metal layer, gate insulation layer 7, semiconductor channel layer 62, second metal layer,
Two insulating barriers 8, first transparency electrode layer, the first insulating barrier 9 and second transparency electrode layer, formed with grid line 1 in the first metal layer
And the grid 61 of oxide thin film transistor 6, the wherein grid 61 of oxide thin film transistor 6 can be wherein the one of grid line 1
Part is formed, formed with data wire 2 and common signal line (not shown) in second metal layer, in first transparency electrode layer formed with
Formed in each pixel cell in the pixel electrode 52 and public electrode 31 of the lower section of the first insulating barrier 9, second transparency electrode layer
Have in each pixel cell positioned at the pixel electrode 32 and public electrode 51 of the top of the first insulating barrier 9.
In one embodiment, incorporated by reference to Fig. 5 and Fig. 6, public electrode 31 and pixel electrode in first transparency electrode layer
52 are staggered in matrix form and are interconnected between public electrode 31, the position of the public electrode 51 in second transparency electrode layer
Corresponded with the position of the pixel electrode 52 in first transparency electrode layer, the position of the pixel electrode 32 in second transparency electrode layer
Put and corresponded with the position of the public electrode 31 in first transparency electrode layer, the phase of public electrode 31 in second transparency electrode layer
It is intercommunicated, so that the public electrode of adjacent pixel unit is inverted each other respectively with pixel electrode.
In one embodiment, the second insulating barrier 8 is provided with first through hole in the opening position of corresponding common signal line and (schemed not
Show), the public electrode 31 in first transparency electrode layer is interconnected and is connected by first through hole with common signal line, and first is exhausted
Edge layer 9 is formed through the second through hole (not shown) successively with the second insulating barrier 8 in the opening position of corresponding common signal line, and second is saturating
Public electrode 51 in prescribed electrode layer is interconnected and is connected by the second through hole with common signal line, so that saturating positioned at first
The flood public electrode 31 of prescribed electrode layer can receive with the flood public electrode 51 of second transparency electrode layer as an entirety
Identical signal.
In one embodiment, as shown in figs. 5 and 6, the public electrode 31 and pixel in first transparency electrode layer
Electrode 52 is planar structure, and the public electrode 51 in second transparency electrode layer and pixel electrode 32 are list structure, are passed through
Adjusting aperture opening ratio, strip width, the quantity of slit (slit) and width can be to the first pixel cell 3 and the second pixel cell 5
Light transmittance TR be finely adjusted so that it is consistent that the first pixel cell 3 and the second pixel cell 5 reach brightness, in the present embodiment,
The slit number of public electrode 51 in second transparency electrode layer is more than the pixel electrode 32 being located in second transparency electrode layer
Slit number.Also, can be in aperture opening ratio identical bar by adjusting the light transmittance of the first pixel cell 3 and the second pixel cell 5
Under part, make the light transmittance of the embodiment of the present invention and the exposure of only pixel electrode or only the light transmittance phase of the structure of public electrode exposure
When.
In one embodiment, in the pixel electrode and public electrode of same pixel cell, positioned at the lower section of the first insulating barrier 9
The width of electrode be less than the width of the electrode positioned at the top of the first insulating barrier 9, and the electrode positioned at the top of the first insulating barrier 9 exists
The data wire 2 of projection covering both sides corresponding position on width.Because the electrode above the first insulating barrier 9 is compared
For electrode positioned at the lower section of the first insulating barrier 9 further from data wire 2, the pixel electrode and public electrode in same pixel cell are total
When area keeps constant, the width of electrode of the increase above the first insulating barrier 9, while reduce and be located under the first insulating barrier 9
The width of the electrode of side, can effectively reduce electric capacity, so as to play a part of reducing power consumption.
Please continue to refer to Fig. 2, source electrode 64 and the drain electrode 63 of oxide thin film transistor 6 are also formed with second metal layer,
Pixel electrode 52 positioned at first transparency electrode layer passes through the source in the third through-hole and second metal layer of the second insulating barrier 8
Pole 64 or the connection of drain electrode 63, the pixel electrode 32 positioned at second transparency electrode layer is by sequentially passing through the first insulating barrier 9 and second
Source electrode 64 or the connection of drain electrode 63 in the fourth hole and second metal layer of insulating barrier 8, in the present embodiment, sull is brilliant
The grid 61 of body pipe 6 is connected with grid line 1, and the source electrode 64 of oxide thin film transistor 6 is connected with data wire 2, and sull is brilliant
The drain electrode 63 of body pipe 6 is connected with pixel electrode 52, pixel electrode 32.It is intelligible, due to existing between source electrode 64 and drain electrode 63
Similitude, in other embodiments of the invention, source electrode 64 63 can also exchange with drain electrode, i.e. oxide thin film transistor 6
Source electrode 64 is connected with pixel electrode 52, pixel electrode 32, and the drain electrode 63 of oxide thin film transistor 6 is connected with data wire 2.
The present invention also provides a kind of preparation method of array base palte, incorporated by reference to Fig. 2, Fig. 5 and Fig. 6, the embodiment of the present invention
The preparation method of array base palte comprises the following steps：
Step 1 a, there is provided substrate 4；
Step 2, the first metal layer of patterning is formed on substrate 4, the first metal layer includes grid line 1 and oxide is thin
The grid 61 of film transistor 6；
Step 3, form gate insulation layer 7；
Step 4, form the semiconductor channel layer 62 of patterning；
Step 5, the second metal layer of patterning is formed, second metal layer includes data wire 2, (figure is not for common signal line
Show) and oxide thin film transistor 6 source electrode 64 and drain electrode 63, data wire 2 intersects with grid line 1；
Step 6, forms the second insulating barrier 8 of patterning, and the second insulating barrier 8 includes exposing the source in second metal layer
Pole 64 or drain 63 through hole and expose the through hole of the common signal line in second metal layer；
Step 7, forms the first transparency electrode layer of patterning, and first transparency electrode layer includes being staggered in matrix form
Public electrode 31 and pixel electrode 52, each public electrode 31 is interconnected and passes through corresponding through hole and the public affairs in second metal layer
Signal wire connection altogether, each pixel electrode 52 are connected by corresponding through hole with the source electrode 64 in second metal layer or drain electrode 63；
Step 8, forms the first insulating barrier 9 of patterning, and the first insulating barrier 9 includes exposing in second metal layer being located at
Source electrode 64 in the place pixel cell of each public electrode 31 of first transparency electrode layer or drain 63 through hole and expose the
The through hole of common signal line in two metal levels；
Step 9, forms the second transparency electrode layer of patterning, and second transparency electrode layer includes being staggered in matrix form
Public electrode 51 and pixel electrode 32, the position and the position of the pixel electrode 52 in first transparency electrode layer of public electrode 51
Correspond, the position of pixel electrode 32 corresponds with the position of the public electrode 31 in first transparency electrode layer, each public
Electrode 51 is interconnected and is connected by corresponding through hole with common signal line, and each pixel electrode 32 passes through corresponding through hole and second
Source electrode 64 or the connection of drain electrode 63 in metal level.
In above-mentioned steps, in addition to step 1 and step 3, each step is corresponding to be entered by one of light shield (Mask)
Row patterning, namely, it is necessary to 7 light shields, relatively only pixel electrode exposure or only for the structure of public electrode exposure, without increasing
Add light shield quantity, do not increase processing procedure cost.
The present invention also provides a kind of display device, and display device includes array base palte as described above or battle array as described above
Array base palte made from the preparation method of row substrate.
The array base palte of the present invention, the preparation method and display device of array base palte, the interior setting of each pixel cell are aerobic
Compound thin film transistor (TFT), pixel electrode, public electrode and the first insulating barrier between pixel electrode and public electrode, its
In, the pixel electrode in adjacent pixel unit is inverted each other with public electrode, and the public electrode in each pixel cell is connected to
One common signal line, so as to realize dot inversion with frame reversion, power consumption can be reduced simultaneously, improves image quality.Further, since first
Pixel cell is alternately arranged with the second pixel cell in matrix form so that pixel electrode is exposed to towards liquid crystal with public electrode
Oriented layer side, for the exposure of only pixel electrode or the only structure of public electrode exposure, ion is more conducive to along electrode
It is mobile, it is preferable to the image retention improvement of liquid crystal display.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification
For the equivalent embodiment of equivalent variations, as long as being the technical spirit pair according to the present invention without departing from technical solution of the present invention content
Any simple modification, equivalent change and modification that above example is made, in the range of still falling within technical solution of the present invention.
Claims (10)
1. a kind of array base palte, the array base palte includes grid line, the data wire of substrate and setting on the substrate, described
Grid line intersects to set with the data wire forms pixel cell arranged in arrays, and oxidation is provided with each pixel cell
Thing thin film transistor (TFT), pixel electrode, public electrode and first exhausted between the pixel electrode and the public electrode
Edge layer, it is characterised in that the pixel electrode in adjacent pixel unit is inverted each other respectively with public electrode, in each pixel cell
Pixel electrode is connected by corresponding oxide thin film transistor with the grid line and the data wire, the public affairs in each pixel cell
Common electrode is connected to same common signal line.
2. array base palte as claimed in claim 1, it is characterised in that the side of the substrate be sequentially provided with the first metal layer,
Gate insulation layer, semiconductor channel layer, second metal layer, the second insulating barrier, first transparency electrode layer, first insulating barrier and
Two transparent electrode layers, the grid formed with the grid line and the oxide thin film transistor in the first metal layer are described
Formed with the data wire and the common signal line in second metal layer, formed with each pixel in the first transparency electrode layer
Pixel electrode and public electrode in unit below first insulating barrier, formed with each in the second transparency electrode layer
Pixel electrode and public electrode in pixel cell above first insulating barrier.
3. array base palte as claimed in claim 2, it is characterised in that public electrode and picture in the first transparency electrode layer
Plain electrode is staggered in matrix form and is interconnected between public electrode, the public electrode in the second transparency electrode layer
Position and the position of the pixel electrode in the first transparency electrode layer correspond, the pixel in the second transparency electrode layer
The position of electrode and the position of the public electrode in the first transparency electrode layer correspond, in the second transparency electrode layer
Public electrode be interconnected.
4. array base palte as claimed in claim 2, it is characterised in that second insulating barrier is in the corresponding common signal line
Opening position be provided with first through hole, the public electrode in the first transparency electrode layer is interconnected and passes through the first through hole
It is connected with the common signal line, first insulating barrier is with second insulating barrier in the position of the corresponding common signal line
Locate to be formed through the second through hole successively, the public electrode in the second transparency electrode layer is interconnected and by described second led to
Hole is connected with the common signal line.
5. array base palte as claimed in claim 2, it is characterised in that the public electrode in the first transparency electrode layer
It is planar structure with pixel electrode, the public electrode in the second transparency electrode layer and pixel electrode are list structure.
6. the array base palte as described in claim 1 or 5, it is characterised in that the pixel electrode and common electrical of same pixel cell
In extremely, the width of the electrode below first insulating barrier is less than the width of the electrode above first insulating barrier
Degree, and the data of the projection covering both sides corresponding position of the electrode above first insulating barrier in the direction of the width
Line.
7. array base palte as claimed in claim 5, it is characterised in that the public electrode in the second transparency electrode layer
Slit number be more than be located at the second transparency electrode layer in pixel electrode slit number.
8. array base palte as claimed in claim 2, it is characterised in that the oxide is also formed with the second metal layer
The source electrode of thin film transistor (TFT) and drain electrode, the pixel electrode positioned at the first transparency electrode layer pass through through second insulating barrier
Third through-hole and the second metal layer in source electrode or drain electrode connect, positioned at the pixel electrode of the second transparency electrode layer
By sequentially passing through the fourth hole of first insulating barrier and second insulating barrier and the source electrode in the second metal layer
Or drain electrode connection.
A kind of 9. preparation method of array base palte, it is characterised in that including：
One substrate is provided；
The first metal layer of patterning is formed on the substrate, and the first metal layer includes grid line and sull crystal
The grid of pipe；
Form gate insulation layer；
Form the semiconductor channel layer of patterning；
The second metal layer of patterning is formed, it is thin that the second metal layer includes data wire, common signal line and the oxide
The source electrode of film transistor and drain electrode, the data wire intersect with the grid line；
The second insulating barrier of patterning is formed, second insulating barrier includes exposing source electrode or the leakage in the second metal layer
The through hole of pole and the through hole for exposing the common signal line in the second metal layer；
The first transparency electrode layer of patterning is formed, it is in the staggered common electrical of matrix form that the first transparency electrode layer, which includes,
Pole and pixel electrode, each public electrode are interconnected and connected by corresponding through hole with the common signal line in the second metal layer
Connect, each pixel electrode is connected by corresponding through hole with the source electrode in the second metal layer or drain electrode；
The first insulating barrier of patterning is formed, first insulating barrier includes exposing in the second metal layer positioned at described the
The through hole of source electrode or drain electrode where each public electrode of one transparent electrode layer in pixel cell and expose second gold medal
Belong to the through hole of the common signal line in layer；
The second transparency electrode layer of patterning is formed, it is in the staggered common electrical of matrix form that the second transparency electrode layer, which includes,
Pole and pixel electrode, the position of public electrode and the position of the pixel electrode in the first transparency electrode layer correspond, as
The position of plain electrode and the position of the public electrode in the first transparency electrode layer correspond, and each public electrode is interconnected
And be connected by corresponding through hole with the common signal line, each pixel electrode passes through in corresponding through hole and the second metal layer
Source electrode or drain electrode connection.
10. a kind of display device, it is characterised in that the display device includes the battle array as any one of claim 1 to 8
Array base palte made from the preparation method of row substrate or array base palte as claimed in claim 9.
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| CN201711297517.1A CN107861304B (en) | 2017-12-08 | 2017-12-08 | Array substrate, manufacturing method of array substrate and display device |
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| US20080002079A1 (en) * | 2006-06-02 | 2008-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic appliance |
| CN102156359A (en) * | 2010-06-13 | 2011-08-17 | 京东方科技集团股份有限公司 | Array base plate, liquid crystal panel, liquid crystal display and driving method |
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN103941503A (en) * | 2013-12-31 | 2014-07-23 | 上海中航光电子有限公司 | TFT array substrate and display device |
| CN105974693A (en) * | 2016-07-27 | 2016-09-28 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and driving method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080002079A1 (en) * | 2006-06-02 | 2008-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic appliance |
| CN102156359A (en) * | 2010-06-13 | 2011-08-17 | 京东方科技集团股份有限公司 | Array base plate, liquid crystal panel, liquid crystal display and driving method |
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN103941503A (en) * | 2013-12-31 | 2014-07-23 | 上海中航光电子有限公司 | TFT array substrate and display device |
| CN105974693A (en) * | 2016-07-27 | 2016-09-28 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and driving method |
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