CN107861304B - Array substrate, manufacturing method of array substrate and display device - Google Patents
Array substrate, manufacturing method of array substrate and display device Download PDFInfo
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- CN107861304B CN107861304B CN201711297517.1A CN201711297517A CN107861304B CN 107861304 B CN107861304 B CN 107861304B CN 201711297517 A CN201711297517 A CN 201711297517A CN 107861304 B CN107861304 B CN 107861304B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
An array substrate comprises a substrate, grid lines and data lines, wherein the grid lines and the data lines are arranged on the substrate, the grid lines and the data lines are arranged in a crossed mode to form pixel units which are arranged in a matrix mode, an oxide thin film transistor, a pixel electrode, a common electrode and a first insulating layer located between the pixel electrode and the common electrode are arranged in each pixel unit, the pixel electrode and the common electrode in adjacent pixel units are inverted, the pixel electrode in each pixel unit is connected with the grid lines and the data lines through the corresponding oxide thin film transistor, and the common electrode in each pixel unit is connected to the same common signal line. The invention also provides a manufacturing method of the array substrate and a display device. The pixel electrodes and the common electrodes in the adjacent pixel units are mutually inverted, and the common electrodes in the pixel units are connected to the same common signal line, so that the dot inversion can be realized by frame inversion, the power consumption can be reduced, and the image quality can be improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.
Background
With the rapid development of light weight, thinness and miniaturization of electronic products, Liquid Crystal Displays (LCDs) are used as Display panels in most of various portable electronic products, and are important components in video cameras, notebook computers, desktop computers, smart televisions, mobile terminals or personal digital processors.
In the display process of the liquid crystal display, the driving voltage of the liquid crystal molecules cannot be fixed at a certain value, otherwise, the liquid crystal molecules are polarized due to accumulation of positive and negative charges, and gradually lose optical rotation characteristics. Therefore, in order to prevent the characteristics of the liquid crystal molecules from being damaged, the driving voltage of the liquid crystal molecules must be changed in polarity, and the absolute value of the voltage difference between the upper and lower electrodes is fixed during the polarity change, so that the expressed gray scales are the same, but the liquid crystal molecules are completely reversed in direction of rotation, thereby causing the position of positive and negative charges accumulated on the liquid crystal molecules to move, i.e., causing the electric dipole moment to change, and preventing the polarization of the liquid crystal molecules. There are four common polarity inversion schemes: the method comprises frame inversion, row inversion, column inversion and dot inversion, wherein the frame inversion means that the whole display is refreshed by positive voltage in the previous frame, the next frame is refreshed by negative voltage, the row inversion means that positive voltage is applied to odd rows and negative voltage is applied to even rows in the previous frame of an image, the voltage polarity of odd and even rows in the next frame is interchanged, the polarity conversion process of the column inversion is similar to that of the row inversion, the dot inversion means that the voltage polarities of adjacent pixel points in each frame of the image are opposite, and the dot inversion mode is favorable for eliminating cross crosstalk and picture flicker, so that the image quality is the best.
Disclosure of Invention
The invention aims to provide an array substrate, a manufacturing method of the array substrate and a display device, which can reduce power consumption and improve image quality.
The invention provides an array substrate which comprises a substrate, and a grid line and a data line which are arranged on the substrate, wherein the grid line and the data line are arranged in a crossed manner to form pixel units which are arranged in a matrix manner, each pixel unit is internally provided with an oxide thin film transistor, a pixel electrode, a common electrode and a first insulating layer positioned between the pixel electrode and the common electrode, the pixel electrode and the common electrode in adjacent pixel units are inverted, the pixel electrode in each pixel unit is connected with the grid line and the data line through the corresponding oxide thin film transistor, and the common electrode in each pixel unit is connected to the same common signal line.
In one embodiment, a first metal layer, a gate insulating layer, a semiconductor channel layer, a second metal layer, a second insulating layer, a first transparent electrode layer, a first insulating layer and a second transparent electrode layer are sequentially disposed on one side of the substrate, the gate line and the gate electrode of the oxide thin film transistor are formed in the first metal layer, the data line and the common signal line are formed in the second metal layer, the pixel electrode and the common electrode of each pixel unit located below the first insulating layer are formed in the first transparent electrode layer, and the pixel electrode and the common electrode of each pixel unit located above the first insulating layer are formed in the second transparent electrode layer.
In an embodiment, the common electrodes and the pixel electrodes in the first transparent electrode layer are arranged in a matrix-type staggered manner and are communicated with each other, the positions of the common electrodes in the second transparent electrode layer are in one-to-one correspondence with the positions of the pixel electrodes in the first transparent electrode layer, the positions of the pixel electrodes in the second transparent electrode layer are in one-to-one correspondence with the positions of the common electrodes in the first transparent electrode layer, and the common electrodes in the second transparent electrode layer are communicated with each other.
In an embodiment, the second insulating layer is provided with a first through hole at a position corresponding to the common signal line, the common electrodes in the first transparent electrode layer are communicated with each other and connected to the common signal line through the first through hole, the first insulating layer and the second insulating layer sequentially penetrate at a position corresponding to the common signal line to form a second through hole, and the common electrodes in the second transparent electrode layer are communicated with each other and connected to the common signal line through the second through hole.
In an embodiment, the common electrode and the pixel electrode in the first transparent electrode layer are planar structures, and the common electrode and the pixel electrode in the second transparent electrode layer are strip structures.
In an embodiment, in the pixel electrode and the common electrode of the same pixel unit, a width of the electrode located below the first insulating layer is smaller than a width of the electrode located above the first insulating layer, and a projection of the electrode located above the first insulating layer in a width direction covers the data lines at corresponding positions on both sides.
In one embodiment, the number of slits of the common electrode in the second transparent electrode layer is greater than the number of slits of the pixel electrode in the second transparent electrode layer.
In one embodiment, a source and a drain of the oxide thin film transistor are further formed in the second metal layer, the pixel electrode located in the first transparent electrode layer is connected to the source or the drain in the second metal layer through a third through hole penetrating through the second insulating layer, and the pixel electrode located in the second transparent electrode layer is connected to the source or the drain in the second metal layer through a fourth through hole sequentially penetrating through the first insulating layer and the second insulating layer.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate;
forming a patterned first metal layer on the substrate, wherein the first metal layer comprises a grid line and a grid electrode of an oxide thin film transistor;
forming a gate insulating layer;
forming a patterned semiconductor channel layer;
forming a patterned second metal layer, wherein the second metal layer comprises a data line, a common signal line and a source electrode and a drain electrode of the oxide thin film transistor, and the data line and the grid line are crossed;
forming a patterned second insulating layer including a via hole exposing a source or a drain in the second metal layer and a via hole exposing a common signal line in the second metal layer;
forming a patterned first transparent electrode layer, wherein the first transparent electrode layer comprises public electrodes and pixel electrodes which are arranged in a matrix staggered manner, the public electrodes are mutually communicated and are connected with public signal lines in the second metal layer through corresponding through holes, and the pixel electrodes are connected with a source electrode or a drain electrode in the second metal layer through corresponding through holes;
forming a patterned first insulating layer, wherein the first insulating layer comprises a through hole exposing a source electrode or a drain electrode of the second metal layer in a pixel unit where each common electrode of the first transparent electrode layer is located and a through hole exposing a common signal line of the second metal layer;
and forming a patterned second transparent electrode layer, wherein the second transparent electrode layer comprises public electrodes and pixel electrodes which are arranged in a matrix staggered manner, the positions of the public electrodes correspond to the positions of the pixel electrodes in the first transparent electrode layer one by one, the positions of the pixel electrodes correspond to the positions of the public electrodes in the first transparent electrode layer one by one, all the public electrodes are mutually communicated and are connected with the public signal line through corresponding through holes, and all the pixel electrodes are connected with the source electrode or the drain electrode in the second metal layer through corresponding through holes.
The invention also provides a display device which comprises the array substrate or the array substrate manufactured by the manufacturing method of the array substrate.
According to the array substrate, the manufacturing method of the array substrate and the display device, the oxide thin film transistor, the pixel electrode, the common electrode and the first insulating layer located between the pixel electrode and the common electrode are arranged in each pixel unit, wherein the pixel electrode and the common electrode in adjacent pixel units are inverted, and the common electrode in each pixel unit is connected to the same common signal line, so that the dot inversion can be realized through frame inversion, the power consumption can be reduced, and the image quality can be improved.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of two adjacent pixel units of the array substrate at the location of the oxide thin film transistor according to an embodiment of the invention.
Fig. 3A is a schematic view illustrating an electric field direction of the first pixel unit in the positive polarity frame according to an embodiment of the invention.
Fig. 3B is a schematic view illustrating an electric field direction of the second pixel unit in the positive polarity frame according to an embodiment of the invention.
FIG. 3C is a schematic view illustrating the direction of the electric field of the first pixel unit in the negative polarity frame according to an embodiment of the invention.
FIG. 3D is a schematic diagram illustrating an electric field direction of the second pixel unit in the negative polarity frame according to an embodiment of the invention.
Fig. 4 is a schematic polarity diagram of each pixel unit of the array substrate under a frame inversion condition according to an embodiment of the invention.
Fig. 5 is a schematic structural diagram of the first transparent electrode layer in an embodiment of the invention.
Fig. 6 is a schematic structural diagram of a second transparent electrode layer in an embodiment of the invention.
Detailed Description
To further explain the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the present invention will be made with reference to the accompanying drawings and preferred embodiments.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention. Fig. 2 is a schematic cross-sectional view of two adjacent pixel units of the array substrate at the location of the oxide thin film transistor according to an embodiment of the invention. As shown in fig. 1 and 2, the array substrate of the present invention includes a substrate 4, and a Gate line (Gate line)1 and a data line (data line)2 disposed on the substrate 4, where the Gate line 1 and the data line 2 are intersected with each other to form pixel units arranged in a matrix, each pixel unit is provided with an oxide thin film transistor 6, a pixel electrode, a common electrode, and a first insulating layer 9 located between the pixel electrode and the common electrode, where the pixel electrode and the common electrode in adjacent pixel units are respectively inverted, the pixel electrode in each pixel unit is connected to the Gate line 1 and the data line 2 through the corresponding oxide thin film transistor 6, and the common electrode in each pixel unit is connected to the same common signal line. Here, a pixel cell with a pixel electrode on Top (Top pixel) configured in such a manner that the pixel electrode 32 is located above the first insulating layer 9 and the common electrode 31 is located below the first insulating layer 9 is referred to as a "first pixel cell 3", a pixel cell having a common electrode on Top (Top com) configured in such a manner that the pixel electrode 52 is positioned below the first insulating layer 9 and the common electrode 51 is positioned above the first insulating layer 9 is referred to as a "second pixel cell 5", the first pixel units 3 and the second pixel units 5 are disposed on the substrate 4 in a matrix-type staggered arrangement manner, the pixel electrodes 32 of the first pixel units 3 and the pixel electrodes 52 of the second pixel units 5 are inverted, the common electrodes 31 of the first pixel units 3 and the common electrodes 51 of the second pixel units 5 are inverted, and the common electrodes 31 of the first pixel units 3 and the common electrodes 51 of the second pixel units 5 are connected to a same common signal line (not shown).
According to the structure of the array substrate of the embodiment of the invention, when the frame inversion is performed, assuming that the voltage of 5V is applied to each pixel electrode (pixel) in the positive polarity frame, the voltage of 0V is applied to the common electrode (com) through the same common signal line, the voltage of-5V is applied to each pixel electrode in the negative polarity frame, and the voltage of 0V is applied to the common electrode through the same common signal line, the electric field in the direction shown in fig. 3A is obtained in the positive polarity frame by the first pixel unit 3(Top pixel), the electric field in the direction shown in fig. 3C is obtained in the negative polarity frame by the second pixel unit 5(Top com), the electric field in the direction shown in fig. 3B is obtained in the positive polarity frame, and the electric field in the direction shown in fig. 3D is obtained in the negative polarity frame. It can be seen that, when the electric field direction of the first pixel unit 3 in the positive polarity frame is the same as the electric field direction of the second pixel unit 5 in the negative polarity frame, the electric field direction of the first pixel unit 3 in the negative polarity frame is the same as the electric field direction of the second pixel unit 5 in the positive polarity frame, and the electric field directions of the first pixel unit 3 and the second pixel unit 5 in the same polarity frame are opposite, and thus, when the pixel electrodes of the respective pixel units are inverted by applying a positive voltage to all of the data lines 2, the electric field direction of the second pixel unit 5 is negative if the electric field direction of the first pixel unit 3 is positive, and the polarity state in the FFS (fringe field Switching) architecture as shown in fig. 4 is obtained as a whole due to the alternating arrangement of the first pixel unit 3 and the second pixel unit 5 in the matrix form, that is, the data line 2 is supplied with a frame inversion voltage, and a dot inversion effect is obtained, thereby reducing power consumption and improving image quality. In addition, since the first pixel units 3 and the second pixel units 5 are alternately arranged in a matrix form, the pixel electrodes and the common electrodes are exposed on the side facing the liquid crystal alignment layer, and compared with a structure in which only the pixel electrodes are exposed or only the common electrodes are exposed, the structure is more favorable for ions to move along the electrodes, and has a better residual image improvement effect on the liquid crystal display.
With reference to fig. 1 and fig. 2, an interlayer structure of an array substrate according to an embodiment of the invention is described.
A first metal layer, a gate insulating layer 7, a semiconductor channel layer 62, a second metal layer, a second insulating layer 8, a first transparent electrode layer, a first insulating layer 9 and a second transparent electrode layer are sequentially disposed on one side of the substrate 4, the first metal layer is formed with a gate line 1 and a gate electrode 61 of the oxide thin film transistor 6, wherein the gate electrode 61 of the oxide thin film transistor 6 can be formed as a part of the gate line 1, the second metal layer is formed with a data line 2 and a common signal line (not shown), the first transparent electrode layer is formed with a pixel electrode 52 and a common electrode 31 of each pixel unit located below the first insulating layer 9, and the second transparent electrode layer is formed with a pixel electrode 32 and a common electrode 51 of each pixel unit located above the first insulating layer 9.
In an embodiment, please refer to fig. 5 and fig. 6, the common electrodes 31 and the pixel electrodes 52 in the first transparent electrode layer are arranged in a matrix-type staggered manner, and the common electrodes 31 are communicated with each other, the common electrodes 51 in the second transparent electrode layer are in one-to-one correspondence with the pixel electrodes 52 in the first transparent electrode layer, the pixel electrodes 32 in the second transparent electrode layer are in one-to-one correspondence with the common electrodes 31 in the first transparent electrode layer, and the common electrodes 31 in the second transparent electrode layer are communicated with each other, so that the common electrodes and the pixel electrodes of adjacent pixel units are respectively inverted.
In one embodiment, the second insulating layer 8 is provided with a first through hole (not shown) at a position corresponding to the common signal line, the common electrodes 31 in the first transparent electrode layer are communicated with each other and connected to the common signal line through the first through hole, the first insulating layer 9 and the second insulating layer 8 are sequentially communicated with each other at a position corresponding to the common signal line to form a second through hole (not shown), and the common electrodes 51 in the second transparent electrode layer are communicated with each other and connected to the common signal line through the second through hole, so that the entire layers of the common electrodes 31 in the first transparent electrode layer and the entire layers of the common electrodes 51 in the second transparent electrode layer can receive the same signal as a whole.
In an embodiment, as shown in fig. 5 and 6, the common electrode 31 and the pixel electrode 52 in the first transparent electrode layer are planar structures, the common electrode 51 and the pixel electrode 32 in the second transparent electrode layer are strip structures, and the light transmittances TR of the first pixel unit 3 and the second pixel unit 5 can be finely adjusted by adjusting the aperture ratio, the strip width, and the number and width of the slits (slit), so that the luminances of the first pixel unit 3 and the second pixel unit 5 are consistent, in this embodiment, the number of slits of the common electrode 51 in the second transparent electrode layer is greater than the number of slits of the pixel electrode 32 in the second transparent electrode layer. Moreover, by adjusting the light transmittance of the first pixel unit 3 and the second pixel unit 5, the light transmittance of the embodiment of the invention can be made equivalent to that of a structure in which only the pixel electrode is exposed or only the common electrode is exposed under the condition of the same aperture ratio.
In one embodiment, of the pixel electrode and the common electrode of the same pixel unit, the width of the electrode located below the first insulating layer 9 is smaller than the width of the electrode located above the first insulating layer 9, and the projection of the electrode located above the first insulating layer 9 in the width direction covers the data lines 2 at the corresponding positions on both sides. Since the electrode above the first insulating layer 9 is farther from the data line 2 than the electrode below the first insulating layer 9, when the total area of the pixel electrode and the common electrode in the same pixel unit remains unchanged, the width of the electrode above the first insulating layer 9 is increased, and the width of the electrode below the first insulating layer 9 is decreased, so that the capacitance can be effectively reduced, thereby reducing the power consumption.
With reference to fig. 2, a source 64 and a drain 63 of the oxide thin film transistor 6 are further formed in the second metal layer, the pixel electrode 52 located in the first transparent electrode layer is connected to the source 64 or the drain 63 in the second metal layer through a third through hole penetrating through the second insulating layer 8, the pixel electrode 32 located in the second transparent electrode layer is connected to the source 64 or the drain 63 in the second metal layer through a fourth through hole sequentially penetrating through the first insulating layer 9 and the second insulating layer 8, in this embodiment, the gate 61 of the oxide thin film transistor 6 is connected to the gate line 1, the source 64 of the oxide thin film transistor 6 is connected to the data line 2, and the drain 63 of the oxide thin film transistor 6 is connected to the pixel electrode 52 and the pixel electrode 32. It is understood that, due to the similarity between the source electrode 64 and the drain electrode 63, in other embodiments of the present invention, the source electrode 64 and the drain electrode 63 may be interchanged, that is, the source electrode 64 of the oxide thin film transistor 6 is connected to the pixel electrode 52 and the pixel electrode 32, and the drain electrode 63 of the oxide thin film transistor 6 is connected to the data line 2.
The invention further provides a manufacturing method of the array substrate, please refer to fig. 2, fig. 5 and fig. 6, the manufacturing method of the array substrate of the embodiment of the invention includes the following steps:
step one, providing a substrate 4;
step two, forming a patterned first metal layer on the substrate 4, wherein the first metal layer comprises the grid line 1 and the grid electrode 61 of the oxide thin film transistor 6;
step three, forming a gate insulating layer 7;
step four, forming a patterned semiconductor channel layer 62;
step five, forming a patterned second metal layer, wherein the second metal layer comprises a data line 2, a common signal line (not shown) and a source 64 and a drain 63 of the oxide thin film transistor 6, and the data line 2 and the gate line 1 are crossed with each other;
step six, forming a patterned second insulating layer 8, wherein the second insulating layer 8 comprises a through hole exposing the source electrode 64 or the drain electrode 63 in the second metal layer and a through hole exposing the common signal line in the second metal layer;
step seven, forming a patterned first transparent electrode layer, wherein the first transparent electrode layer comprises public electrodes 31 and pixel electrodes 52 which are arranged in a matrix staggered manner, the public electrodes 31 are communicated with each other and are connected with public signal lines in the second metal layer through corresponding through holes, and the pixel electrodes 52 are connected with a source electrode 64 or a drain electrode 63 in the second metal layer through corresponding through holes;
step eight, forming a patterned first insulating layer 9, wherein the first insulating layer 9 comprises a through hole exposing the source 64 or the drain 63 of the second metal layer in the pixel unit where each common electrode 31 of the first transparent electrode layer is located, and a through hole exposing the common signal line in the second metal layer;
step nine, forming a patterned second transparent electrode layer, wherein the second transparent electrode layer comprises public electrodes 51 and pixel electrodes 32 which are arranged in a matrix staggered manner, the positions of the public electrodes 51 correspond to the positions of the pixel electrodes 52 in the first transparent electrode layer one by one, the positions of the pixel electrodes 32 correspond to the positions of the public electrodes 31 in the first transparent electrode layer one by one, all the public electrodes 51 are mutually communicated and are connected with a public signal line through corresponding through holes, and all the pixel electrodes 32 are connected with a source electrode 64 or a drain electrode 63 in the second metal layer through corresponding through holes.
In the above steps, except for the first step and the third step, each step is correspondingly patterned by a Mask (Mask), that is, 7 masks are required, and compared with a structure in which only the pixel electrode is exposed or only the common electrode is exposed, the number of masks does not need to be increased, and the manufacturing cost is not increased.
The invention also provides a display device which comprises the array substrate or the array substrate manufactured by the manufacturing method of the array substrate.
According to the array substrate, the manufacturing method of the array substrate and the display device, the oxide thin film transistor, the pixel electrode, the common electrode and the first insulating layer located between the pixel electrode and the common electrode are arranged in each pixel unit, wherein the pixel electrode and the common electrode in adjacent pixel units are inverted, and the common electrode in each pixel unit is connected to the same common signal line, so that the dot inversion can be realized through frame inversion, the power consumption can be reduced, and the image quality can be improved. In addition, the first pixel units and the second pixel units are arranged alternately in a matrix form, so that the pixel electrodes and the common electrodes are exposed on the side facing the liquid crystal orientation layer, and compared with a structure in which only the pixel electrodes are exposed or only the common electrodes are exposed, the structure is more favorable for ions to move along the electrodes, and the improvement effect on the residual image of the liquid crystal display is better.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. An array substrate comprises a substrate, a grid line and a data line, wherein the grid line and the data line are arranged on the substrate, the grid line and the data line are arranged in a crossed mode to form pixel units which are arranged in a matrix mode, an oxide thin film transistor, a pixel electrode, a common electrode and a first insulating layer located between the pixel electrode and the common electrode are arranged in each pixel unit, the array substrate is characterized in that the pixel electrode and the common electrode in adjacent pixel units are inverted to each other, the pixel electrode in each pixel unit is connected with the grid line and the data line through the corresponding oxide thin film transistor, and the common electrode in each pixel unit is connected to the same common signal line;
a first metal layer, a gate insulating layer, a semiconductor channel layer, a second metal layer, a second insulating layer, a first transparent electrode layer, the first insulating layer and a second transparent electrode layer are sequentially arranged on one side of the substrate, the gate line and the grid electrode of the oxide thin film transistor are formed in the first metal layer, the data line and the common signal line are formed in the second metal layer, a pixel electrode and a common electrode which are positioned below the first insulating layer in each pixel unit are formed in the first transparent electrode layer, and a pixel electrode and a common electrode which are positioned above the first insulating layer in each pixel unit are formed in the second transparent electrode layer;
the second insulating layer is provided with a first through hole at a position corresponding to the public signal line, public electrodes in the first transparent electrode layer are communicated with each other and are connected with the public signal line through the first through hole, the first insulating layer and the second insulating layer sequentially penetrate through the position corresponding to the public signal line to form a second through hole, and the public electrodes in the second transparent electrode layer are communicated with each other and are connected with the public signal line through the second through hole.
2. The array substrate according to claim 1, wherein the common electrodes in the first transparent electrode layer are interlaced with the pixel electrodes in a matrix form and are connected to each other, the positions of the common electrodes in the second transparent electrode layer are in one-to-one correspondence with the positions of the pixel electrodes in the first transparent electrode layer, the positions of the pixel electrodes in the second transparent electrode layer are in one-to-one correspondence with the positions of the common electrodes in the first transparent electrode layer, and the common electrodes in the second transparent electrode layer are connected to each other.
3. The array substrate of claim 1, wherein the common electrode and the pixel electrode in the first transparent electrode layer are planar structures, and the common electrode and the pixel electrode in the second transparent electrode layer are strip structures.
4. The array substrate according to claim 1 or 3, wherein, of the pixel electrode and the common electrode of the same pixel unit, the width of the electrode located below the first insulating layer is smaller than the width of the electrode located above the first insulating layer, and the projection of the electrode located above the first insulating layer in the width direction covers the data lines at the corresponding positions on both sides.
5. The array substrate of claim 3, wherein the number of slits of the common electrode in the second transparent electrode layer is greater than the number of slits of the pixel electrode in the second transparent electrode layer.
6. The array substrate according to claim 1, wherein a source electrode and a drain electrode of the oxide thin film transistor are further formed in the second metal layer, the pixel electrode located in the first transparent electrode layer is connected to the source electrode or the drain electrode in the second metal layer through a third via hole penetrating the second insulating layer, and the pixel electrode located in the second transparent electrode layer is connected to the source electrode or the drain electrode in the second metal layer through a fourth via hole sequentially penetrating the first insulating layer and the second insulating layer.
7. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a patterned first metal layer on the substrate, wherein the first metal layer comprises a grid line and a grid electrode of an oxide thin film transistor;
forming a gate insulating layer;
forming a patterned semiconductor channel layer;
forming a patterned second metal layer, wherein the second metal layer comprises a data line, a common signal line and a source electrode and a drain electrode of the oxide thin film transistor, and the data line and the grid line are crossed;
forming a patterned second insulating layer including a via hole exposing a source or a drain in the second metal layer and a via hole exposing a common signal line in the second metal layer;
forming a patterned first transparent electrode layer, wherein the first transparent electrode layer comprises public electrodes and pixel electrodes which are arranged in a matrix staggered manner, the public electrodes are mutually communicated and are connected with public signal lines in the second metal layer through corresponding through holes, and the pixel electrodes are connected with a source electrode or a drain electrode in the second metal layer through corresponding through holes;
forming a patterned first insulating layer, wherein the first insulating layer comprises a through hole exposing a source electrode or a drain electrode of the second metal layer in a pixel unit where each common electrode of the first transparent electrode layer is located and a through hole exposing a common signal line of the second metal layer;
and forming a patterned second transparent electrode layer, wherein the second transparent electrode layer comprises public electrodes and pixel electrodes which are arranged in a matrix staggered manner, the positions of the public electrodes correspond to the positions of the pixel electrodes in the first transparent electrode layer one by one, the positions of the pixel electrodes correspond to the positions of the public electrodes in the first transparent electrode layer one by one, all the public electrodes are mutually communicated and are connected with the public signal line through corresponding through holes, and all the pixel electrodes are connected with the source electrode or the drain electrode in the second metal layer through corresponding through holes.
8. A display device comprising the array substrate according to any one of claims 1 to 6 or the array substrate manufactured by the manufacturing method of the array substrate according to claim 7.
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| CN102156359B (en) * | 2010-06-13 | 2014-05-07 | 京东方科技集团股份有限公司 | Array base plate, liquid crystal panel, liquid crystal display and driving method |
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| CN103941503B (en) * | 2013-12-31 | 2017-03-08 | 上海中航光电子有限公司 | A kind of tft array substrate and display device |
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