CN107851577B - 衬底接触蚀刻工艺 - Google Patents

衬底接触蚀刻工艺 Download PDF

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CN107851577B
CN107851577B CN201680045942.9A CN201680045942A CN107851577B CN 107851577 B CN107851577 B CN 107851577B CN 201680045942 A CN201680045942 A CN 201680045942A CN 107851577 B CN107851577 B CN 107851577B
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deep trench
plasma
substrate
dielectric liner
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CN107851577A (zh
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D·W·哈曼
T·E·里里伯瑞治
A·阿里
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Texas Instruments Inc
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Abstract

在所描述的示例中，具有深沟槽(112)的半导体器件(100)具有形成在深沟槽(112)的侧壁(122)和底部(124)上的介电衬垫(120)。两步工艺法的预蚀刻淀积步骤在半导体器件(100)的现有顶表面上以及在接近衬底(102)的顶表面(106)的介电衬垫(120)上形成保护性聚合物(136)。预蚀刻淀积步骤没有从深沟槽(112)的底部(124)移除大量的介电衬垫(120)。两步工艺法的主蚀刻步骤在深沟槽(112)的顶部处保持保护性聚合物(136)的同时，移除在深沟槽(112)的底部(124)处的介电衬垫(120)。随后移除保护性聚合物(136)。

Description

衬底接触蚀刻工艺
技术领域
本发明总体涉及半导体器件，并且更具体地涉及半导体器件中的深沟槽接触。
背景技术
半导体器件具有至少10微米深的深沟槽，其具有在深沟槽的侧壁和底部上的二氧化硅衬垫。为了与衬底进行接触，期望移除沟槽的底部处的二氧化硅衬垫而不实质上减小在深沟槽侧壁上的二氧化硅衬垫。用于移除在沟槽底部的二氧化硅衬垫以与衬底进行接触的反应离子蚀刻工艺具有高离子能量，反应离子蚀刻工艺还从在深沟槽的顶部的衬垫移除介电材料而不期望加宽深沟槽的顶部。加宽顶部须要在衬垫中更厚的淀积二氧化硅的层，这不利地增加制造成本。
发明内容
在所描述的示例中，通过在衬底中蚀刻至少10微米深的深沟槽来形成半导体器件。介电衬垫形成在深沟槽的侧壁和底部上。使用两步工艺法移除深沟槽的底部的介电衬垫。两步工艺法的预蚀刻淀积步骤在半导体器件的现有顶表面上以及在接近衬底的顶表面的介电衬垫上形成保护性聚合物。预蚀刻淀积步骤没有从深沟槽的底部移除大量的介电衬垫。两步工艺法的主蚀刻步骤在保持深沟槽的顶部处的保护性聚合物的同时移除深沟槽底部处的介电衬垫。随后，移除保护性聚合物。
附图说明
图1A至图1I是半导体器件的横截面，以示例制造顺序的连续阶段示出。
图2是示例半导体器件的横截面。
具体实施方式
附图不是按比例绘制。一些动作可以不同的顺序发生和/或与其它动作或事件同时发生。此外，不要求所示出的所有动作或事件来实施根据示例实施例的方法。
图1A至图1I是以示例制造顺序的连续阶段描绘的半导体器件的横截面。参考图1A，在诸如硅晶片或另一半导体材料的晶片的衬底102中形成半导体器件100。其它形式的衬底102(例如半导体材料的外延层)在该示例的范围内。在图1A至图1I中，衬底102被分离以更清晰地显示随后既在深沟槽的顶部又在深沟槽的底部形成的深沟槽的细节。在衬底102的顶表面106的上方形成焊盘层104。例如，焊盘层104可以包含在顶表面106处的热氧化层以及在热氧化层上的由低压化学汽相淀积(LPCVD)工艺形成的氮化硅层。在焊盘层104的上方形成硬掩膜氧化层108。例如，取决于随后形成的深沟槽的深度，硬掩膜氧化层108可以是1微米至2微米厚。可以通过使用原硅酸四乙酯(TEOS)(也被称为四乙氧基硅烷)的等离子体增强化学汽相淀积(PECVD)或通过使用高密度等离子体(HDP)工艺来形成硬掩膜氧化层108。在硬掩膜氧化层108的上方形成沟槽掩膜110以暴露用于深沟槽112的区域。沟槽掩膜110包含由光刻工艺形成的光刻胶，并且可以包含诸如有机底部抗反射涂层(BARC)的抗反射层和/或氮化硅的硬掩膜层。
参考图1B，在由沟槽掩膜110暴露的深沟槽112的区域中移除硬掩膜氧化层108和焊盘层104。可以通过RIE工艺移除硬掩膜氧化层108。随后例如通过相同的RIE工艺或通过另一种RIE工艺移除焊盘层104。此时，沟槽掩膜110可以可选地被移除或留在原处。
参考图1C，通过使用图案化的硬掩膜氧化层108作为蚀刻掩膜而从衬底102移除材料来形成深沟槽112。通过定时RIE工艺形成深沟槽112。深沟槽112具有至少10微米的深度114；深度114可以为25微米至40微米。深沟槽112具有0.5微米至3微米的宽度116。图1B的沟槽掩膜110的任何剩余部分通过RIE工艺被移除以形成深沟槽112。深沟槽112可以被稍微地锥形化，如图1C中所示。
参考图1D，在形成深沟槽112之后，可以可选地移除图1C的硬掩膜氧化层108(如图1D所示)。可替换地，在随后的制造步骤期间，硬掩膜氧化层108可以被留在原处。
参考图1E，介电衬垫120的热氧化层118被形成在深沟槽112的侧壁122和底部124上。例如，热氧化层118可以为200纳米至300纳米厚。例如通过次常压化学汽相淀积(SACVD)工艺，在热氧化层118的上形成介电衬垫120的二氧化硅层126。例如，二氧化硅层126可以为300纳米至700纳米厚。热氧化层118与二氧化硅层126结合提供介电衬垫120。介电衬垫120覆盖深沟槽112的底部124并且具有接近底部124至少300纳米的空间128，使得介电衬垫120在底部124处的厚度不大于介电衬垫120在侧壁122上的厚度。
例如，介电衬垫120的总厚度可以为500纳米至1微米，并且被选择为提供半导体器件在特定电压下的操作的期望的击穿强度。在该示例的另一个版本中，可以改变热氧化层118与二氧化硅层126的相对厚度以提供期望的工艺范围。在该示例的替换版本中，介电衬垫120可以仅包括热氧化层118，而不包括二氧化硅层126。
参考图1F，执行两步工艺法中的预蚀刻淀积工艺以在衬底102的顶表面106上方的半导体器件100的现有顶表面上形成保护性聚合物136，其延伸到接近衬底102的顶表面106的深沟槽112中的介电衬垫120上。例如，保护性聚合物136在与深沟槽112相邻的半导体器件100的顶表面上方可以为10纳米至50纳米厚。在深沟槽112的底部124处，基本上没有聚合物被形成在介电衬垫120上。在预蚀刻淀积工艺期间，基本上没有介电材料被从介电衬垫120移除。现在将描述用于形成保护性聚合物136的一种方法。半导体器件100被放置在第一腔室130中，例如晶片工艺工具的蚀刻腔室。支撑衬底102的衬底卡盘(未示出)可以被保持在0℃到35℃的温度。诸如氩气的载体气体以125标准立方厘米每分钟(sccm)至1500sccm的速率流入在半导体器件100上方的第一腔室130的第一等离子体区域132中。具有至少为2比1的氟碳原子比的氟化烃(例如全氟化烃(例如，图1F中描绘的八氟环丁烷(C4F8)))利用载体气体以10sccm至50sccm的速率流入到第一等离子区域132中。利用氟化烃，氟代甲烷(CH3F)以20sccm至80sccm的速率流入到第一等离子体区域132中。第一等离子区域132中的压力保持在35微米汞柱至65微米汞柱。射频(RF)功率被以0.5瓦特至1瓦特/衬底102的平方厘米的平均功率水平施加到在第一等离子体区域132上方的电极134，导致在第一等离子体区域132中形成等离子体。等离子体使氟化烃与氟代甲烷反应以在半导体器件100的现有顶表面上形成保护性聚合物136，其延伸到接近衬底102的顶表面106的深沟槽112中的介电衬垫120上。基本上没有聚合物被形成在深沟槽112的底部124处的介电衬垫120上。在预蚀刻淀积工艺期间，基本上没有介电材料被从介电衬垫120移除。在该示例的另一个版本中，氟化烃可以为六氟环丁烷(C4F6)、八氟环戊烷(C5F8)、全氟环己烷(C6F12)、八氟丙烷(C3F8)、八氟乙烷(C2F6)或四氟甲烷(CF4)。
参考图1G，执行两步工艺法中主蚀刻工艺以移除在深沟槽112的底部124处的介电衬垫120。主蚀刻工艺不会导致在深沟槽112的侧壁122上的介电衬垫120的实质性退化。同时，主蚀刻工艺使氟化烃与氟代甲烷反应以维持并且可能地增加保护性聚合物136。保护性聚合物136可以增加厚度，例如在与深沟槽112相邻的半导体器件100的顶表面上增加100纳米至500纳米。保护性聚合物136有利地防止在主蚀刻工艺期间从介电衬垫120中移除介电材料。现在将描述一种执行主蚀刻工艺的示例方法。半导体器件100被置于第二腔室138(可以是图1F的第一腔室130)中。支撑衬底102的衬底卡盘(未示出)可以被保持在0℃至35℃的温度。诸如氩气的载体气体以125sccm至1500sccm的速率流入在半导体器件100上方的第二腔室138的第二等离子体区域140中。具有至少为2比1的氟碳原子比的氟化烃(在图1G中指定为C4F8)利用载体气体以20sccm至80sccm的速率流入到第二等离子区域140中。利用氟化烃，氟代甲烷以5sccm至40sccm的速率流入到第二等离子体区域140中。第二等离子区域140中的压力保持在20微米汞柱至30微米汞柱。RF功率被以3瓦特至5瓦特/衬底102的平方厘米的平均功率水平施加到在第二等离子体区域140上方的电极142，导致在第二等离子体区域140中形成等离子体。等离子体产生氟自由基，其在深沟槽112的底部124处移除介电衬垫120。
侧壁122对于衬底102的顶表面106基本上竖直向上，并且没有外倾，使得将深沟槽112更接近半导体器件100的组件放置并且因此有利地减小半导体器件100的尺寸。介电衬垫120具有向上到衬底102的顶表面106基本均匀的厚度，有利地实现了更薄的二氧化硅层126，有利地降低半导体器件100的制造成本。在该示例的另一个版本中，可以在相同的腔室130和138中执行预蚀刻淀积工艺和主蚀刻工艺，可以从预蚀刻淀积工艺到主蚀刻工艺延用RF功率，可以从预蚀刻淀积工艺到主蚀刻工艺继续并且调整氟化烃与氟代甲烷的流动，使得等离子体被有利地从预蚀刻淀积工艺保持到主蚀刻工艺，消除了在主蚀刻工艺的低压下击打等离子体的需要。
参考图1H，执行灰化工艺以移除图1G的保护性聚合物136。灰化工艺不会导致在深沟槽112的侧壁122上的介电衬垫120的实质退化。现在将描述一种示例灰化工艺。半导体器件100被放置在第三腔室144中，该第三腔室144可以是图1F的第一腔室130和/或图1G的第二腔室138。诸如氩气的载体气体以500sccm至1000sccm的速率流入第二腔室138的等离子体区域146中。氧气以125sccm至500sccm的速率流入等离子区域146中。等离子区域146中的压力保持在150微米汞柱至300微米汞柱。将RF功率以0.5瓦特至1瓦特/衬底102的平方厘米的平均功率水平施加到在等离子体区域146上方的电极148，导致在等离子体区域146中形成等离子体。等离子体产生氧自由基，该氧自由基移除图1G的保护性聚合物136。在该示例的另一个版本中，可以在与主蚀刻工艺相同的腔室138中执行灰化工艺，使得在主蚀刻工艺期间淀积在腔室138的表面上的聚合物有利地在灰化工艺期间被移除，防止聚合物的建立，并且期望地提高主蚀刻工艺的一致性。
参考图1I，在深沟槽112中形成导电沟槽填充150，在底部124处接触衬底102。例如，沟槽填充150可以包含多晶体硅(称为多晶硅)，多晶硅被掺杂以与深沟槽112的底部124处的衬底102具有相同的导电类型。可以通过在半导体器件100的现有顶表面的上方形成一个或多个多晶硅层而形成沟槽填充150，其延伸到深沟槽112中并且在底部124处接触衬底102。在该层的形成过程中可以掺杂多晶硅，或可以通过离子注入掺杂多晶硅。例如通过化学机械抛光(CMP)工艺和/或回蚀工艺，随后移除在衬底102的顶表面106的上方的多晶硅。
图2是示例半导体器件的横截面。如参考图1A所描述，在衬底202中形成半导体器件200。在该示例中，衬底202包含n型掩埋层252；在衬底202之上、在衬底202以下以及围绕该n型掩埋层252的半导体材料是p型的。
深度至少为10微米的第一深沟槽212具有闭环配置并且围绕n型掩埋层252并邻接n型掩埋层252。第一深沟槽212具有邻接衬底202并从接近衬底202的顶表面206延伸到接近第一深沟槽212的底部224的第一介电衬垫220。第一深沟槽212的底部224的至少一部分没有第一介电衬垫220。p型多晶硅的第一沟槽填充250被设置在第一深沟槽212中，延伸到底部224并且与衬底202的p型半导体材料进行接触。第一深沟槽212的侧壁对于衬底202的顶表面206基本竖直向上，从而产生参考图1G所描述的优点。
半导体器件200包含延伸至n型掩埋层252的第二深沟槽254。第二深沟槽254的深度至少为10微米并且具有小于2的横向长宽比，也就是横向长度与横向宽度之比小于2。第二深沟槽254具有邻接衬底202并且从接近衬底202的顶表面206延伸到第二深沟槽254的底部258的第二介电衬垫256。第二深沟槽254的底部258的至少一部分没有第一介电衬垫220。n型多晶硅的第二沟槽填充260被设置在第二深沟槽254中，延伸到底部258并且与n型掩埋层252的n型半导体材料进行接触。第二深沟槽254的侧壁基本竖直到达衬底202的顶表面206，从而产生参考图1G所描述的优点。
在权利要求的范围内，在所描述的实施例中修改是可能的，并且其它实施例是可能的。

Claims (18)

1.一种形成半导体器件的方法，其包括以下步骤：
提供衬底；
在所述衬底中形成至少10微米深并且0.5微米至3微米宽的深沟槽；
在所述深沟槽的侧壁和底部上形成介电衬垫；
通过预蚀刻沉积等离子体工艺在所述衬底的顶部的上方形成保护性聚合物，所述保护性聚合物延伸到接近所述衬底的顶表面的所述深沟槽中的所述介电衬垫上，而不在所述深沟槽的所述底部处的所述介电衬垫上，同时没有从所述介电衬垫中移除介电材料；
通过主蚀刻等离子体工艺移除在所述深沟槽的所述底部处的所述介电衬垫，同时不从接近所述衬底的所述顶表面的所述深沟槽中的所述介电衬垫上的所述保护性聚合物中移除聚合物材料并且不从接近所述衬底的所述顶表面的所述深沟槽中的所述介电衬垫中移除介电材料；以及
随后移除所述保护性聚合物。
2.根据权利要求1所述的方法，其中所述介电衬垫主要包含二氧化硅。
3.根据权利要求2所述的方法，其中所述介电衬垫是热氧化物。
4.根据权利要求1所述的方法，其中所述介电衬垫为500纳米至1微米厚。
5.根据权利要求1所述的方法，其中所述预蚀刻沉积等离子体工艺包括：
将所述半导体器件放置在第一腔室中，所述第一腔室具有在所述半导体器件上方的第一等离子体区域；
使载体气体流入所述第一等离子体区域；
使具有至少为2比1的氟碳原子比的氟化烃流入所述第一等离子体区域；
使氟代甲烷流入所述第一等离子体区域；
将在所述第一等离子体区域中的压力保持在35微米汞柱至65微米汞柱；以及
将射频功率即RF功率施加到在所述第一等离子体区域上方的电极，导致在所述第一等离子体区域中形成第一等离子体。
6.根据权利要求5所述的方法，其中所述氟化烃为八氟环丁烷。
7.根据权利要求1所述的方法，其中通过所述预蚀刻沉积等离子体工艺在与所述深沟槽相邻的所述衬底的所述顶部的上方形成的保护性聚合物为10纳米至50纳米厚。
8.根据权利要求1所述的方法，其中所述主蚀刻等离子体工艺包括：
将所述半导体器件放置到第二腔室中，所述第二腔室具有在所述半导体器件上方的第二等离子体区域；
使载体气体流入所述第二等离子体区域；
使具有至少为2比1的氟碳原子比的氟化烃流入所述第二等离子体区域；
使氟代甲烷流入所述第二等离子体区域；
将在所述等离子体区域中的压力维持在20微米汞柱至30微米汞柱；以及
将RF功率施加到在所述等离子体区域上方的电极，导致在所述第二等离子体区域中形成等离子体。
9.根据权利要求8所述的方法，其中所述氟化烃为八氟环丁烷。
10.根据权利要求1所述的方法，其中所述主蚀刻等离子体工艺增大所述保护性聚合物的厚度。
11.根据权利要求10所述的方法，其中所述主蚀刻等离子体工艺将在与所述深沟槽相邻的所述衬底的所述顶部上方的所述保护性聚合物的厚度增加100纳米至500纳米。
12.根据权利要求1所述的方法，其中在同一腔室中执行所述预蚀刻沉积等离子体工艺和所述主蚀刻等离子体工艺。
13.根据权利要求12所述的方法，其中在所述预蚀刻沉积等离子体工艺和所述主蚀刻等离子体工艺之间的过渡期间保持RF功率以在所述过渡期间维持所述半导体器件的上方的等离子体。
14.根据权利要求1所述的方法，其中移除所述保护性聚合物包括灰法工艺。
15.根据权利要求14所述的方法，其中在同一腔室中执行所述灰法工艺和所述主蚀刻等离子体工艺。
16.根据权利要求1所述的方法，其中所述深沟槽的深度为25微米至40微米。
17.一种形成半导体器件的方法，其包括以下步骤：
提供衬底；
在所述衬底中形成至少为10微米深和0.5微米至3微米宽的深沟槽；
在所述深沟槽的侧壁和底部上形成介电衬垫；
通过预蚀刻沉积等离子体工艺在所述衬底的顶部的上方形成保护性聚合物，所述保护性聚合物延伸到接近所述衬底的顶表面的所述深沟槽中的所述介电衬垫上，而不在所述深沟槽的底部处的所述介电衬垫上，同时没有从所述介电衬垫中移除介电材料；
通过主蚀刻等离子体工艺移除在所述深沟槽的所述底部处的所述介电衬垫，同时不从接近所述衬底的所述顶表面的所述深沟槽中的所述介电衬垫上的所述保护性聚合物中移除聚合物材料并且不从接近所述衬底的所述顶表面的所述深沟槽中的所述介电衬垫中移除介电材料；以及
随后移除所述保护性聚合物，
其中所述预蚀刻沉积等离子体工艺包括：
将所述半导体器件放置在第一腔室中，所述第一腔室具有在所述半导体器件上方的第一等离子体区域；
使载体气体流入所述第一等离子体区域；
使具有至少为2比1的氟碳原子比的氟化烃流入所述第一等离子体区域；
使氟代甲烷流入所述第一等离子体区域；
将在所述第一等离子体区域中的压力保持在35微米汞柱至65微米汞柱；以及
将射频功率即RF功率施加到在所述第一等离子体区域上方的电极，导致在所述第一等离子体区域中形成第一等离子体。
18.一种形成半导体器件的方法，其包括以下步骤：
提供衬底；
在所述衬底中形成至少为10微米深和0.5微米至3微米宽的深沟槽；
在所述深沟槽的侧壁和底部上形成介电衬垫；
通过预蚀刻沉积等离子体工艺在所述衬底的顶部的上方形成保护性聚合物，所述保护性聚合物延伸到接近所述衬底的顶表面的所述深沟槽中的所述介电衬垫上，而不在所述深沟槽的底部处的所述介电衬垫上，同时没有从所述介电衬垫中移除介电材料；
通过主蚀刻等离子体工艺移除在所述深沟槽的所述底部处的所述介电衬垫，同时不从接近所述衬底的所述顶表面的所述深沟槽中的所述介电衬垫上的所述保护性聚合物中移除聚合物材料并且不从接近所述衬底的所述顶表面的所述深沟槽中的所述介电衬垫中移除介电材料；
随后移除所述保护性聚合物，
其中所述主蚀刻等离子体工艺包括：
将所述半导体器件放置到第二腔室中，所述第二腔室具有在所述半导体器件上方的第二等离子体区域；
使载体气体流入所述第二等离子体区域；
使具有至少为2比1的氟碳原子比的氟化烃流入所述第二等离子体区域；
使氟代甲烷流入所述第二等离子体区域；
将在所述等离子体区域中的压力维持在20微米汞柱至30微米汞柱；以及
将RF功率施加到在所述等离子体区域上方的电极，导致在所述第二等离子体区域中形成等离子体。
CN201680045942.9A 2015-08-06 2016-08-08 衬底接触蚀刻工艺 Active CN107851577B (zh)

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