CN107845681A - A kind of semiconductor devices and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN107845681A CN107845681A CN201610840197.9A CN201610840197A CN107845681A CN 107845681 A CN107845681 A CN 107845681A CN 201610840197 A CN201610840197 A CN 201610840197A CN 107845681 A CN107845681 A CN 107845681A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 238000009434 installation Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 66
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 62
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000005516 engineering process Methods 0.000 claims abstract description 30
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 28
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 26
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 19
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims abstract description 18
- 210000004483 pasc Anatomy 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 206010010144 Completed suicide Diseases 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 124
- 238000000034 method Methods 0.000 claims description 40
- 239000011229 interlayer Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000000407 epitaxy Methods 0.000 claims description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 5
- 239000011469 building brick Substances 0.000 claims description 5
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical group [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- 238000002955 isolation Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 239000012212 insulator Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910000990 Ni alloy Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910005487 Ni2Si Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
- 229910052753 mercury Inorganic materials 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical group O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- -1 NiSi.That is Chemical compound 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000002816 nickel compounds Chemical class 0.000 description 1
- 229910001453 nickel ion Inorganic materials 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic installation, and the preparation method comprises the steps：Semiconductor substrate is provided, forms grid on the semiconductor substrate, source electrode and drain electrode are formed in the Semiconductor substrate of the grid both sides, and silicon covering layer is formed on the source electrode and drain electrode, the source electrode and drain electrode use silicon germanium material；Formed on the silicon covering layer and contain nickel metal layer, and perform first time Technology for Heating Processing to form initial nickel silicide, and consume the part silicon covering layer；Pasc reaction layer is formed on the initial nickel silicide, and performs second of Technology for Heating Processing, to form the nickel silicide of convex liter.If if the preparation method can improve the blocked up caused growth grain defect problem of silicon covering layer or the contact problems of the excessively thin caused nickel silicide of silicon covering layer and SiGe, and the nickel suicide structure of this convex liter can improve the electrical leakage problems of PN junction.The semiconductor devices has the advantages of similar with electronic installation.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, the critical size of semiconductor devices has been contracted to below 60nm.It is same with this
When, nickel silicide (NiSi) is due to relatively low heat budget, line width independence, low sheet resistance, the consumption of low silicon and and SiGe
The advantages that technology (technology can apply compression to the raceway groove of PMOS device, so as to improve the performance of PMOS device) is compatible,
As 60nm and and lower technology node semiconductor devices candidate material.However, the nickel silicide directly contacted with SiGe
Poor heat endurance, nisiloy/SiGe (NiSi/SiGe) interface roughness can be run into and in the rapid thermal annealing for forming nickel silicide
The problem of germanium spreads.The coating that some nearest report expressions form one layer of pure silicon in silicon Germanium regions can reduce these and ask
Topic, but the thickness of silicon covering layer must be appropriate, if because silicon covering layer is too thin, can not meet the shape of nickel silicide
Into and nickel silicide be easy to contact with silicon Germanium regions, again can silicon germanium epitaxial life but with the increase of silicon covering layer thickness
Long grain defect problem substantially increases, and the problem of the bad control of silicon covering layer uniformity.
It is, therefore, desirable to provide a kind of preparation method of new semiconductor devices, to solve the above problems.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
One aspect of the present invention provides a kind of preparation method of semiconductor devices, and it comprises the steps：Semiconductor lining is provided
Bottom, grid is formed on the semiconductor substrate, formation source electrode and drain electrode in the Semiconductor substrate of the grid both sides, and
Silicon covering layer is formed on the source electrode and drain electrode, the source electrode and drain electrode use silicon germanium material；Formed on the silicon covering layer
Containing nickel metal layer, and first time Technology for Heating Processing is performed to form initial nickel silicide, and consume the part silicon covering layer；
Pasc reaction layer is formed on the initial nickel silicide, and performs second of Technology for Heating Processing, to form the nickel silicide of convex liter.
Preferably, the step of source electrode and drain electrode are formed in the Semiconductor substrate of the grid both sides includes：In the grid
Hex-shaped recess is formed in the Semiconductor substrate of pole both sides；The hex-shaped recess is being filled with silicon germanium material.
Preferably, in addition to：The step of to the pre-amorphous injection of nickel silicide progress SiGe.
Preferably, the silicon covering layer is by being epitaxially formed.
Preferably, the silicon germanium material and the silicon covering layer grow formation in same epitaxy technique
Preferably, the thickness of the silicon covering layer is 15~20nm.
Preferably, the temperature of the first time Technology for Heating Processing is 220~300 DEG C.
Preferably, the temperature changing speed of the first time Technology for Heating Processing is 1~3 DEG C/s.
Preferably, described containing nickel metal layer is nickel platinum alloy.
Preferably, the thickness containing nickel metal layer is 10~15nm.
Preferably, platinum content is 5%~15% in the nickel platinum alloy.
Preferably, the initial nickel silicide is rich nickel silicide.
Preferably, include in the step of formation pasc reaction layer on the initial nickel silicide：
Formed and cover the grid and source electrode, the interlayer dielectric layer of drain electrode, and formed and exposed in the interlayer dielectric layer
The grid, source electrode and the contact hole of drain electrode；The pasc reaction layer is formed in the contact hole bottom.
Preferably, the pasc reaction layer deposits to be formed by gas beam injection technique.
Preferably, the temperature of second of Technology for Heating Processing is 550~850 DEG C.
The preparation method of semiconductor devices proposed by the present invention, if the blocked up caused growth particle of silicon covering layer can be improved
If defect problem or the contact problems of the excessively thin caused nickel silicide of silicon covering layer and SiGe, and the nickel silicide of this convex liter
Structure can avoid nickle atom from being diffused into grid groove, improve the electrical leakage problems of PN junction.
Another aspect of the present invention provides a kind of semiconductor devices made using the above method, and the semiconductor devices includes：
Semiconductor substrate, on the semiconductor substrate formed with grid, formed in the Semiconductor substrate of the grid both sides active
Pole and drain electrode, the source electrode and drain electrode use silicon germanium material, formed with silicon covering layer and positioned at institute on the source electrode and drain electrode
State the nickel silicide on silicon covering layer.
Semiconductor devices proposed by the present invention, the contact of SiGe grain defect problem and nickel silicide with SiGe can be avoided
Problem, and reduction invades the nickel below grid or clearance wall, so as to improve knot leakage problem.
Further aspect of the present invention provides a kind of electronic installation, it include semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with it is similar the advantages of.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the step flow chart of the preparation method of semiconductor devices according to an embodiment of the present invention；
Fig. 2A~Fig. 2 K show that the preparation method of semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Step obtains the diagrammatic cross-section of semiconductor devices；
Fig. 3 shows the sectional view of semiconductor devices according to an embodiment of the present invention；
Fig. 4 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
Identical element is represented with reference.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As it was previously stated, various problems can be run into by forming nickel silicide in silicon Germanium regions, the present invention is to overcome these problems to carry
A kind of preparation method of semiconductor devices is gone out, as shown in figure 1, the preparation method includes：Step 101：Semiconductor substrate is provided,
Grid is formed on the semiconductor substrate, and source electrode and drain electrode are formed in the Semiconductor substrate of the grid both sides, and in institute
State and silicon covering layer is formed in source electrode and drain electrode, the source electrode and drain electrode use silicon germanium material；Step 102：In the silicon covering layer
Upper formation contains nickel metal layer, and performs first time Technology for Heating Processing to form initial nickel silicide, and consumes the part silicon and cover
Cap rock；Step S103：Pasc reaction layer is formed on the initial nickel silicide, and performs second of Technology for Heating Processing, to be formed
The nickel silicide of convex liter.
The preparation method of semiconductor devices proposed by the present invention, first by forming silicon covering layer in silicon Germanium regions, so
Formed afterwards on the silicon covering layer and contain nickel metal layer, such as nickel metal layer or nickel alloy layer, work is then heat-treated by first time
Skill forms initial nickel silicide, and consumes part silicon covering layer, and pasc reaction layer is then formed on the initial nickel silicide, and
The nickel silicide of convex liter is formed by second of heat treatment, in second is heat-treated, the nickel of initial nickel silicide is pulled up
React to form nickel silicide with the pasc reaction layer of top, rather than reacted with silicon covering layer downwards, therefore will not cause nickel suicide
Thing directly contacts with silicon Germanium regions, the problem of avoiding due to heat endurance difference directly caused by contact and interface roughness, meanwhile,
Due to only consuming part silicon covering layer in being heat-treated in first time, in being heat-treated second nickel be pulled up it is anti-with the silicon of top
Layer is answered to react, thus the thickness of silicon covering layer can reduce, and alleviate silicon germanium epitaxial growth particle issues and silicon covering layer thickness
The problem of uneven.In addition, the semiconductor devices formed using this preparation method also reduces nickel under grid and/or clearance wall
The problem of side's intrusion, and then reduce Exchange Settlement dew.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this hair
The technical scheme of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
The preparation method of the semiconductor devices of an embodiment of the present invention is done below with reference to Fig. 2A~Fig. 2 K and retouched in detail
State.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, formed with isolation structure in the Semiconductor substrate
201, the offset side wall 204 in the Semiconductor substrate 200 formed with grid 202 and positioned at the both sides of grid 202.
Wherein, Semiconductor substrate 200 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device is could be formed with Semiconductor substrate 200, such as
NMOS and/or PMOS etc..Equally, can also be formed with conductive member in Semiconductor substrate 200, conductive member can be transistor
Grid, source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..As an example, in this implementation
In example, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.
Isolation structure 201 in Semiconductor substrate 200, can be that shallow trench isolates (STI) structure or selective oxidation silicon
(LOCOS) isolation structure, it can be formed by method commonly used in the art, to define and separate active area.As an example,
Isolation structure is using shallow trench isolation (STI) structure.
Grid 202 can use conventional polycrystalline silicon material, and it is formed by method commonly used in the art, such as is first passed through all
As the methods of thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (ald) forms grid
Oxide layer, then in grid oxic horizon by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low
A kind of formation polycrystalline in pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG)
Silicon material layer, then by forming grid hard mask layer 203 the methods of PVD, CVD, ALD, and pass through chemical wet etching method figure
Change grid oxic horizon and polysilicon material layer to form grid 202.
It is understood that grid 202 includes grid oxic horizon and grid electrode layer, for succinct mesh in Fig. 2A~Fig. 2 K
, the structure of grid is not shown specifically.
Offset side wall 204 can use the materials such as oxide, nitride, and be formed by method commonly used in the art,
It will not be repeated here, implant operation (can be lightly doped) with LDD after offset side wall 204 are formed.
Furthermore, it is to be appreciated that the steps such as well region formation can also be included in the step, will be not described herein.
Then, as shown in Figure 2 B, patterned PSR (PMOS silicon Recess) hard mask layer 205, the PSR are formed
Hard mask layer 205 exposes source electrode and the drain region of PMOS device, and covers other regions.
PSR (PMOS silicon Recess) hard mask layer 205 can use the materials such as oxide, nitride, and
It is patterned by conventional lithographic etch process, to expose the source electrode of PMOS device and drain region, and covers other areas
Domain.
Then, as shown in Figure 2 C, it is described in mask etching with PSR (PMOS silicon Recess) hard mask layer 205
The source drain region of PMOS device, to form the groove 206 for being used for filling source-drain electrode material.
Specifically, first by being that mask is carved by dry method with PSR (PMOS silicon Recess) hard mask layer 205
Etching technique forms rectangular recess, then continues to etch the rectangular recess by anisotropic wet-etching technology to form six
Angular groove 206.
In the present embodiment, the wet-etching technology includes the wet-etching technologies such as hydrofluoric acid, phosphoric acid, described dry
Method etch process includes but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.
Exemplarily, in this embodiment, the etching is performed using dry etch process, and as an example, in the present embodiment, it is described
Dry etching is etched to, the technological parameter of the dry etching includes：Etching gas includes the gases such as CF4, CHF3, its flow point
Not Wei 50sccm~500sccm, 10sccm~100sccm, pressure is 2mTorr~50mTorr, wherein, sccm represent cube li
M/min, mTorr represents milli millimetres of mercury.
Then, as shown in Figure 2 D, the groove 206 is filled to form source electrode and drain electrode 207, and in the source electrode and drain electrode
Silicon covering layer 208 is formed on 207.
In the present embodiment, source electrode and drain electrode 207 use silicon germanium material, and it can be formed by epitaxy technique.Specifically,
Silicon germanium buffer (buffer layer) is initially formed, then forms body layer (bulk layer) on the buffer layer, so as to shape
Into source electrode and drain electrode 207.Exemplarily, in the present embodiment, in the silicon germanium material that source electrode and drain electrode 207 use, Ge content model
Enclose for 0~50%.
Preferably, in the present embodiment, SiGe (SiGe) pre-amorphous injection is also performed when forming source electrode and drain electrode 207
Step, further to reduce interface roughness, and reduce Exchange Settlement dew.
After source electrode and drain electrode 207 is formed, epitaxy technique silicon covering layer on source electrode and drain electrode 207 is continued through
208, SiGe and the nickel silicide being subsequently formed are separated by silicon covering layer 208, and provide and form the portion needed for nickel silicide
Point silicon materials, so as to overcome nickel compound directly contact with SiGe present in heat endurance, NiSi/SiGe interface roughness and
During forming nickel silicide germanium spread the problem of.Exemplarily, in the present embodiment, the thickness of silicon covering layer 208 is
15~20nm.
It is understood that in the present embodiment, source electrode and drain electrode and silicon covering layer are secondary in same epitaxy technique one
The step of growing and formed, i.e., source electrode and the drain electrode based on silicon germanium material are formed in the Semiconductor substrate of described grid both sides includes SiGe
The epitaxy growth of cushion, silicon-germanium body layer and pure silicon coating.
Then, as shown in Figure 2 E, grid hard mask layer 203 and PSR hard mask layers 205 are removed.
Specifically, grid hard mask layer 203 is removed by suitable dry method etch technology or wet etching process and PSR is covered firmly
Film layer 205.The wet-etching technology includes the wet-etching technologies such as hydrofluoric acid, phosphoric acid, the dry method etch technology bag
Include but be not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Exemplarily, exist
In this implementation, the etching is performed using dry etch process, and as an example, in the present embodiment, it is described to be etched to dry method
Etching, the technological parameter of the dry etching include：It is respectively 50sccm that etching gas, which includes gas, its flow such as CF4, CHF3,
~500sccm, 10sccm~100sccm, pressure are 2mTorr~50mTorr, wherein, sccm represents cc/min,
MTorr represents milli millimetres of mercury.
Then, as shown in Figure 2 F, form clearance wall 209 in the both sides of grid 202, and formed the covering grid, source electrode and
Drain electrode contains nickel metal layer 210.
Clearance wall 209 passes through method shape commonly used in the art using common used materials such as oxide, nitride or nitrogen oxides
Into.Can be nickel metal or nickel alloy containing nickel metal layer 210.Exemplarily, in the present embodiment, used containing nickel metal layer 210
Nickel platinum alloy, wherein platinum content are 5~15%, and thickness is 10~15nm, preferably about 12nm.
Then, as shown in Figure 2 G, first time Technology for Heating Processing is performed, to form initial nickel silicide 211, and consumes part
Silicon covering layer 208.
Exemplarily, in the present embodiment, the first time Technology for Heating Processing is low-temperature rapid thermal annealing process, its process warm
It is 220~300 DEG C to spend exemplary, and temperature changing speed is 1~3 DEG C/s.By performing low-temperature rapid thermal annealing process so that contain
Nickel metal layer 210 only forms initial silicide 211 with the reaction of part silicon covering layer 208.Due to only consuming part in this step
Silicon covering layer 208, thus can be consumed with silicon covering layer too many and nickel silicide is directly contacted with SiGe.
Further, initial silicide 211 is rich nickel silicide (for example, Ni2Si), on the one hand rich nickel silicide (for example,
Ni2Si) sheet resistance or resistivity are higher, thus also need to carry out subsequent treatment, on the other hand because initial silicide 211 is
Rich nickel silicide, thus the nickel ion required for subsequent reactions can be provided.
Then, as illustrated in figure 2h, formed and cover the grid, source electrode and the interlayer dielectric layer 212 of drain electrode, and in the layer
Between form contact hole in dielectric layer 212.
Specifically, interlayer dielectric layer 212 can use various suitable dielectric materials, such as low-K material, exemplarily,
In the present embodiment, for interlayer dielectric layer 212 using BPSG (boron-phosphorosilicate glass), it can pass through the conventional work such as CVD or spin-coating method
Skill is formed, and will not be repeated here.
Contact hole is formed in the interlayer dielectric layer 212 to be completed by conventional lithographic etch process, herein not
Repeat again.The position of the contact hole and the position correspondence of source electrode, drain electrode and/or grid.Exemplarily, in the present embodiment, exist
Source electrode, drain electrode, the contact hole of grid are formed in the interlayer dielectric layer 212.Certainly, in other embodiments, can also be only first
Form source electrode, the contact hole of drain electrode.
Then, as shown in figure 2i, pasc reaction layer 213 is formed on the top layer of interlayer dielectric layer 212 and contact hole bottom.
Exemplarily, in the present embodiment, gas beam injection technique (gas cluster implant are passed through
Technique) form pasc reaction layer 213, this technology by suitable energy accelerate silicon atom wear hit surface oxide layer and
Anisotropy injection is carried out, to reach formation pasc reaction layer on rich nickel silicide, without being formed in interlayer dielectric layer side wall.Pass
The deposition process of system such as physical vapour deposition (PVD), chemical vapor deposition, atom deposition method, molecular beam epitaxy deposition is all uncomfortable
With because they do not possess suitable energy and can worn and hit surface oxide layer.Exemplarily, in the present embodiment, pasc reaction layer
Thickness is 10~15nm.
Then, as shown in fig. 2j, second of Technology for Heating Processing is performed, to form the nickel silicide 214 of convex liter.
Exemplarily, in this embodiment, second of Technology for Heating Processing is high-temperature quick thermal annealing, and its technological temperature is 550
~850 DEG C.Pass through the high-temperature quick thermal annealing so that initial nickel silicide 211 is further anti-with the pasc reaction layer 213 of top
Should, so that rich nickel silicide is changed into low-resistance nickel silicide, such as NiSi.That is, by the high-temperature quick thermal annealing, initially
Nickel in nickel silicide 211 is reacted to form low-resistance nickel silicide, so by " pull-up " and the pasc reaction layer 213 above it
The sheet resistance of silicide is not only reduced, and can will not consume silicon covering layer 208, thus can both overcome nickel silicide
Directly contact the problem of existing with SiGe, will not make silicon covering layer thickness too thick again and cause SiGe grain defect problem increase and
Silicon covering layer problem in uneven thickness.In addition, the silicide formed by this method is evenly, and reduce in the process
Nickel invades the nickel below grid or clearance wall, so as to reduce the risk of Exchange Settlement dew.
It is understood that foregoing SiGe (SiGe) pre-amorphisation implant step is not only limited to after source-drain electrode is formed
Carry out, progress after silicide can also be formed in this step.I.e., alternatively, in the present embodiment, the nickel of convex liter is being formed
SiGe (SiGe) pre-amorphous injection can also be carried out to nickel silicide, after silicide 214 further to reduce interface roughness
Degree, and reduce Exchange Settlement dew.
Finally, as shown in figure 2k, the contact hole is filled with conductive material to form contact.
Exemplarily, in the present embodiment, with tungsten fill interlayer dielectric layer 212 in contact hole with formed source electrode,
Drain contact and gate contact.
So far, the processing step that method according to embodiments of the present invention is implemented is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs afterwards
The step of.
The preparation method for the semiconductor devices that the present embodiment proposes, can avoid SiGe grain defect problem and nickel silicide
With the contact problems of SiGe, and reduce and invade nickel below grid or clearance wall, so as to improve knot leakage problem.
Embodiment two
The present invention also provides a kind of semiconductor devices made using the above method, as shown in figure 3, the semiconductor devices bag
Include：Semiconductor substrate 300, formed with isolation structure 301 in the Semiconductor substrate 300, separate and determine by isolation structure 301
Adopted active area.Formed with grid structure 302 in Semiconductor substrate 300, offset side wall 303 is formed in the both sides of grid structure 302
With clearance wall 304, formed with source electrode, drain electrode 305 in the Semiconductor substrate of the both sides of grid structure 302, and positioned at the source
Silicon covering layer 306 on pole, drain electrode 305.The semiconductor devices also includes covering the grid structure 302 and source electrode, drain electrode
305 interlayer dielectric layer 307, formed with source contact openings, drain contact hole and gate contact hole in interlayer dielectric layer 307,
In the contact hole bottom formed with nickel silicide 309, conductive material 309, such as gold are filled with the nickel silicide
Belong to tungsten.
Wherein Semiconductor substrate 300 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device, such as NMOS are could be formed with Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In the present embodiment, Semiconductor substrate
300 constituent material selects monocrystalline silicon.
Isolation structure 301 can be that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure, its
It can be formed by method commonly used in the art, to define and separate active area.As an example, use shallow trench in isolation structure
Isolate (STI) structure.
Grid structure 302 is formed on active area and isolation structure 301, and it includes grid oxic horizon and gate electrode
Layer, gate oxide is, for example, silica, and grid electrode layer is, for example, polysilicon.
Offset side wall 303 and clearance wall 304 are using conventional spacer material, such as oxide, nitride, nitrogen oxides
Deng.Exemplarily, in the present embodiment, offset side wall 303 uses oxide, and clearance wall 304 uses nitride, such as nitrogenizes
Silicon.Source electrode, drain electrode 305 use silicon germanium material, and the wherein content of germanium is 0~50%.Nickel silicide is low-resistance NiSi.
The semiconductor devices of the present embodiment, the contact of SiGe grain defect problem and nickel silicide with SiGe can be avoided to ask
Topic, and only less nickel is invaded below grid or clearance wall, improves knot leakage problem.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, the semiconductor devices includes：Semiconductor substrate, on the semiconductor substrate formed with grid
Pole, formed with source electrode and drain electrode in the Semiconductor substrate of the grid both sides, and form silicon on the source electrode and drain electrode and cover
Cap rock, the source electrode and drain electrode use silicon germanium material, formed with silicon covering layer and positioned at the silicon on the source electrode and drain electrode
Nickel silicide on coating.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with the display portion being included in shell 401
402nd, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
The electronic installation of the embodiment of the present invention, by the semiconductor devices included can avoid SiGe grain defect problem
With the contact problems of nickel silicide and SiGe, and only less nickel is invaded below grid or clearance wall, improves Exchange Settlement
Dew problem.Therefore the electronic installation equally has the advantages of similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (17)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the steps：
Semiconductor substrate is provided, forms grid on the semiconductor substrate, the shape in the Semiconductor substrate of the grid both sides
Into source electrode and drain electrode, and silicon covering layer is formed on the source electrode and drain electrode, the source electrode and drain electrode use silicon germanium material；
Formed on the silicon covering layer and contain nickel metal layer, and perform first time Technology for Heating Processing to form initial nickel silicide,
And consume the part silicon covering layer；
Pasc reaction layer is formed on the initial nickel silicide, and performs second of Technology for Heating Processing, to form the nisiloy of convex liter
Compound.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that in partly leading for the grid both sides
The step of source electrode and drain electrode are formed in body substrate includes：
Hex-shaped recess is formed in the Semiconductor substrate of the grid both sides；
The hex-shaped recess is being filled with silicon germanium material.
3. the preparation method of semiconductor devices according to claim 1, it is characterised in that also include：To described nickel suicide
Thing carries out the step of SiGe pre-amorphous injection.
4. the preparation method of semiconductor devices according to claim 1, it is characterised in that the silicon covering layer passes through extension
Method is formed.
5. the preparation method of semiconductor devices according to claim 4, it is characterised in that the silicon germanium material and the silicon
Coating grows formation in same epitaxy technique.
6. the preparation method of semiconductor devices according to claim 4, it is characterised in that the thickness of the silicon covering layer is
15~20nm.
7. the preparation method of semiconductor devices according to claim 1, the temperature of the first time Technology for Heating Processing is 220
~300 DEG C.
8. the preparation method of semiconductor devices according to claim 7, it is characterised in that the first time Technology for Heating Processing
Temperature changing speed be 1~3 DEG C/s.
9. the preparation method of semiconductor devices according to claim 1, it is characterised in that described containing nickel metal layer is nickel platinum
Alloy.
10. the preparation method of semiconductor devices according to claim 9, it is characterised in that the thickness containing nickel metal layer
Spend for 10~15nm.
11. the preparation method of semiconductor devices according to claim 9, it is characterised in that platinum contains in the nickel platinum alloy
Measure as 5%~15%.
12. the preparation method of semiconductor devices according to claim 9, it is characterised in that the initial nickel silicide is
Rich nickel silicide.
13. the preparation method of the semiconductor devices according to claim 1-12 any one, it is characterised in that described first
The step of pasc reaction layer is formed on beginning nickel silicide includes：
Formed and cover the grid and source electrode, the interlayer dielectric layer of drain electrode, and formed in the interlayer dielectric layer expose it is described
Grid, source electrode and the contact hole of drain electrode；
The pasc reaction layer is formed in the contact hole bottom.
14. the preparation method of semiconductor devices according to claim 13, it is characterised in that the pasc reaction layer passes through gas
Body beam injection technique deposits to be formed.
15. the preparation method of semiconductor devices according to claim 13, it is characterised in that second of the heat treatment work
The temperature of skill is 550~850 DEG C.
16. the semiconductor devices that a kind of preparation method using as described in any one in claim 1-15 makes, its feature
It is, including：Semiconductor substrate, on the semiconductor substrate formed with grid, the Semiconductor substrate in the grid both sides
In formed with source electrode and drain electrode, the source electrode and drain electrode use silicon germanium material, formed with silicon covering on the source electrode and drain electrode
Layer and the nickel silicide on the silicon covering layer.
17. a kind of electronic installation, it is characterised in that partly led including semiconductor devices as claimed in claim 16 and with described
The electronic building brick that body device is connected.
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| WO2008085686A2 (en) * | 2007-01-04 | 2008-07-17 | International Business Machines Corporation | Structure and method for mobility enhanced mosfets with unalloyed silicide |
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| JP2012204655A (en) * | 2011-03-25 | 2012-10-22 | Ulvac Japan Ltd | METHOD OF FORMING NiSi FILM, METHOD OF FORMING SILICIDE FILM, METHOD OF FORMING METAL FILM FOR SILICIDE ANNEAL, VACUUM PROCESSING APPARATUS, AND DEPOSITION APPARATUS |
| US9431536B1 (en) * | 2015-03-16 | 2016-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with raised source/drain having cap element |
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| WO2008085686A2 (en) * | 2007-01-04 | 2008-07-17 | International Business Machines Corporation | Structure and method for mobility enhanced mosfets with unalloyed silicide |
| CN102024761A (en) * | 2009-09-18 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor integrated circuit device |
| JP2012204655A (en) * | 2011-03-25 | 2012-10-22 | Ulvac Japan Ltd | METHOD OF FORMING NiSi FILM, METHOD OF FORMING SILICIDE FILM, METHOD OF FORMING METAL FILM FOR SILICIDE ANNEAL, VACUUM PROCESSING APPARATUS, AND DEPOSITION APPARATUS |
| US9431536B1 (en) * | 2015-03-16 | 2016-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with raised source/drain having cap element |
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