CN107810556A - Array base palte and its manufacture method - Google Patents
Array base palte and its manufacture method Download PDFInfo
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- CN107810556A CN107810556A CN201680034308.5A CN201680034308A CN107810556A CN 107810556 A CN107810556 A CN 107810556A CN 201680034308 A CN201680034308 A CN 201680034308A CN 107810556 A CN107810556 A CN 107810556A
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- protective layer
- layer
- drain electrode
- source
- array base
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000011241 protective layer Substances 0.000 claims abstract description 139
- 239000010410 layer Substances 0.000 claims abstract description 124
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 38
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 24
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 5
- 239000007921 spray Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 150000007524 organic acids Chemical class 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000002207 thermal evaporation Methods 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000002738 chelating agent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
Abstract
A kind of manufacture method of array base palte, including：Grid (20), gate insulator (30), metal oxide semiconductor layer (40), the first protective layer (50) and source-drain electrode layer (60) are sequentially formed on substrate (10)；Photoresist layer (70) is formed on source-drain electrode layer (60), vacancy section (71) is provided with photoresist layer (70)；The part for being exposed to vacancy section (71) of source-drain electrode layer (60) is removed, to expose the first protective layer (50)；Dry etching is carried out to the part for being exposed to vacancy section (71) of the first protective layer (50), to cause the part for being exposed to vacancy section (71) of the first protective layer (50) and the remainder of the first protective layer (50) to separate.First protective layer (50) can protect metal oxide semiconductor layer (40) to be not etched by, and avoid metal oxide semiconductor layer (40) surface destroyed, ensure that electron mobility, lift the performance of array base palte.
Description
Technical field
The application is related to display technology field, more particularly to a kind of array base palte and its manufacture method.
Background technology
Array base palte is widely used in different types of display device.With the rapid development of Display Technique, people
To the characteristic requirements such as the resolution ratio of display, response time also more and more higher.In this case, to being arranged on display array
Mobility on substrate requires more and more higher.
At present, the requirement to mobility can not have been met with non-crystalline silicon making active layer, people have turned one's attention to
There are the metal oxide materials of high mobility.The mistake using metal oxide as active layer material is manufactured in the prior art
Cheng Zhong, mainly there is following problem：When traditional handicraft carries out the patterning processes of source-drain electrode, due to not blocked above active layer, because
This can be caused to damage to active layer, so as to have influence on the performance of array base palte.
The content of the invention
The purpose of the application is to provide a kind of manufacture method of array base palte, can avoid causing in manufacturing process active
The corrosion of layer, lift the performance of array base palte.
The another object of the application is to provide a kind of array base palte of above-mentioned manufacture method manufacture.
To achieve the above object, the application provides following technical scheme：
The application provides a kind of manufacture method of array base palte, and methods described includes：
Grid, gate insulator, metal oxide semiconductor layer, the first protective layer and source-drain electrode are sequentially formed on substrate
Layer；
Photoresist layer is formed on the source-drain electrode layer, vacancy section is provided with the photoresist layer；
The part for being exposed to the vacancy section of the source-drain electrode layer is removed, to expose first protective layer；
Dry etching is carried out to the part for being exposed to the vacancy section of first protective layer, to cause described first to protect
The part for being exposed to the vacancy section of sheath and the remainder of first protective layer separate.
Wherein, the part for being exposed to the vacancy section to first protective layer carries out dry etching, to cause
The part for being exposed to the vacancy section of first protective layer is with the remainder cut-off step of first protective layer, wrapping
Include and first protective layer is bombarded using etching gas, the vacancy section is exposed to cause first protective layer
Part and first protective layer remainder between form slit, the slit separates exposing for first protective layer
In the part of the vacancy section and the remainder of first protective layer.
Wherein, the etching gas is a kind of in SF6, O2, Cl2, He, Ar or any several mixing.
Wherein, the part for being exposed to the vacancy section for removing the source-drain electrode layer, to expose first protection
In layer step, it is included in the source-drain electrode layer spray etching liquid and is etched, removed after first protective layer is completely exposed
The etching solution.
Wherein, the part for being exposed to the vacancy section for removing the source-drain electrode layer, to expose first protection
In layer step, it is included in the source-drain electrode layer spray etching liquid and is etched, to form trapezoidal raceway groove on the source-drain electrode layer,
The etching solution is removed after first protective layer is exposed to the trapezoidal raceway groove.
Wherein, the part for being exposed to the vacancy section for removing the source-drain electrode layer, to expose first protection
Layer step in, by control the etching solution concentration and the etching solution the source-drain electrode layer etching period so that institute
The first protective layer is stated to be completely exposed in the trapezoidal raceway groove, wherein, the concentration of the etching solution and the etching period are default
Value.
Wherein, the etching solution includes H2O2, metal-chelator or organic acid.
Wherein, it is described that grid, gate insulator, metal oxide semiconductor layer, the first protection are sequentially formed on substrate
In layer and source-drain electrode layer step, including sequentially form described first on the metal oxide semiconductor layer by sputtering method and protect
Sheath and the source-drain electrode layer.
Wherein, the metal oxide uses IGZO materials, and first protective layer uses GZO materials.
Wherein, the source-drain electrode layer includes the metal level and the second protective layer being stacked, and forms the source-drain electrode layer step
In rapid, including metal level and the second protective layer sequentially formed on first protective layer by sputtering method.
Wherein, second protective layer uses GZO materials.
The application provides a kind of array base palte, including is cascadingly set on the grid, gate insulator, metal oxygen of substrate
Compound semiconductor layer, the first protective layer and source-drain electrode layer, the source-drain electrode layer are provided with the raceway groove for leading to first protective layer,
The part for being exposed to the raceway groove of first protective layer and the remainder of first protective layer separate.
Wherein, the part for being exposed to the vacancy section of first protective layer and the remainder of first protective layer
Between be provided with slit, the slit separates the part for being exposed to the vacancy section and the described first protection of first protective layer
The remainder of layer.
Wherein, the raceway groove is trapezoidal raceway groove.
Wherein, the source-drain electrode layer includes the metal level and the second protective layer being stacked, and the metal level is between described
Between first protective layer and second protective layer.
Wherein, second protective layer uses GZO materials.
Wherein, the metal oxide uses IGZO materials, and first protective layer uses GZO materials.
Wherein, the source-drain electrode layer is made of copper or Cu alloy material.
The embodiment of the present application has the following advantages that or beneficial effect：
In the manufacture method of the array base palte of the application, source-drain electrode layer and the first protective layer are etched twice, first
It is secondary to be first fully etched source-drain electrode layer, then the first protective layer is etched by the method for dry etching for the second time, so that
Obtain the metal oxide semiconductor layer part and be exposed to first protective layer, the first protective layer described in dry etch process
The metal oxide semiconductor layer can be protected to be not etched by, avoid metal oxide semiconductor layer surface is destroyed from (being formed
Wedge angle and pit), electron mobility is ensure that, lifts the performance of array base palte.
Brief description of the drawings
, below will be to institute in embodiment in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the application
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is a kind of manufacture method flow chart for array base palte that the embodiment of the present application provides.
Fig. 2-Fig. 5 is the process schematic of Fig. 1 shown manufacture method.
Fig. 6 is the array base palte that the embodiment of the present application provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.It is based on
Embodiment in the application, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of the application protection.
Ordinal determinative employed in the application following examples, first, second grade is merely to clearly demonstrate this
The distinctive term of similar feature in application, putting in order or using order for corresponding feature is not represented.
The array base palte that the manufacture method of the application is produced can apply in LCDs or organic display screen.
The present embodiments relate to flexible display screen for but not limited to mobile phone, tablet personal computer, palm PC, personal digital assistant
(Personal Digital Assistant, PDA) or electronic reader etc., the embodiment of the present invention is not especially limited to this.
Referring to Fig. 1, Fig. 1 is a kind of manufacture method flow chart for array base palte that the embodiment of the present application provides.The application
The manufacture method of offer mainly comprises the following steps：
S001：Sequentially formed on substrate grid, gate insulator, metal oxide semiconductor layer, the first protective layer and
Source-drain electrode layer.
Specifically, please refer to Fig. 2.The substrate 10 is transparent glass substrate, and first is deposited on the substrate 10
Metallic film.First metallic film can select the metal or alloy such as Cr, W, Cu, Ti, Ta, Mo, be made up of multiple layer metal
Barrier metal layer can also meet needs.By patterning processes grid line (not shown), public electrode are formed using common photoresist layer
The figure of line (not shown) and grid 20.Then PECVD (plasma enhanced chemical vapor depositions are passed through on this basis
Method) method deposition gate insulator 30, gate insulator 30 can be from oxide, nitride or oxynitrides etc..
Then, the method depositing metal oxide semiconductor layer 40 of sputtering or thermal evaporation, metal are passed through on gate insulation layer
Oxide semiconductor layer 40 can be using IGZO (indium gallium zinc oxide, indium gallium zinc oxide), HIZO,
IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb, Cd-Sn-O or
Other metal oxides are made.Preferably, can be made from IGZO materials.
Then, the first protective layer 50 and source-drain electrode layer are sequentially formed using the method for sputtering or thermal evaporation on the substrate 10
60.The effect of first protective layer 50 is diffused into metal oxide semiconductor layer 40 in the metal in source-drain electrode layer 60 is prevented
In, in order to avoid reduce the performance of array base palte.
Preferably, the material that first protective layer 50 can use metal oxide semiconductor layer 50 different is made, example
Such as can be GZO materials.Preferably, the source-drain electrode layer 60 includes the protective layer 62 of metal level 61 and second being stacked.Can
So that the protective layer 62 of metal level 61 and second is sequentially formed on first protective layer 50 by the method for sputtering method or thermal evaporation.
Optionally, the material of the second protective layer 62 can be identical with the material of the first protective layer 50.Described second protects
Sheath 62 is used to prevent the metal level 61 to be oxidized.The metal level 61 can select the metal such as Cr, W, Cu, Ti, Ta, Mo or
Alloy, the barrier metal layer being made up of multiple layer metal can also meet needs.Preferably, copper or Cu alloy material can be selected to be made.
Optionally, the thickness of first protective layer 50 and second protective layer is all 300A.The metal level 61
Thickness can be 2000A.
Optionally, the thickness of the metal oxide semiconductor layer 40 is 300A.
S002：Photoresist layer is covered on the source-drain electrode layer, vacancy section is provided with the photoresist layer.
Specifically, please refer to Fig. 3.Photoresist is coated on second protective layer；A mask plate is provided to cover
Above the photoresist.So as to form photoresist layer 70 by photoetching process.Formed with vacancy section 71 on lid photoresist layer 70.The light
Resistance layer 70 is covered in the top of the second protective layer 62.Second protective layer 62 has subregion to be exposed to the photoresist layer 70
On vacancy section 71.To form raceway groove 65 followed by etching.
S003：The part for being exposed to the vacancy section of the source-drain electrode layer is removed, to expose first protective layer.
Fig. 4 is please referred to, in this step, it is necessary to form raceway groove 65, and is formd on the source-drain electrode layer 60
Source electrode 63 and drain electrode 64.Specifically, raceway groove 65 can be formed on the source-drain electrode layer by the method for wet etching, while by
Source electrode 63 and drain electrode 64 are formed by the raceway groove.
Further specifically, can on the photoresist layer 70 spray etching liquid, etching solution is via engraving on photoresist layer 70
Dead zone 71 is etched to the second protective layer 62 and metal level 61 successively, until the metal level 61 is being located at into vacancy section 71 just
The part of lower section is fully etched, and exposes the first protective layer 50.In this step, when can be by controlling etchant concentration and etching
Between control the depth of etching, wherein, the etchant concentration and the etching period can preset.But actual production
It is difficult just to etch at first protective layer 50 in journey.In view of the performance of the thickness array substrate of the first protective layer 50 does not have
Have an impact, to ensure metal level 61 being fully etched, etching solution can be caused to etch a period of time in the first protective layer 50, so as to
After metal level 61 is fully etched, etching solution is removed.Now, formd on the source-drain electrode layer 60 source electrode 63, drain electrode 64 and
Raceway groove 65 therebetween.It is understood that now the bottom of raceway groove 65 is the first protective layer 50.It is appreciated that
It is that the raceway groove 65 is trapezoidal.This is due to after etching solution enters the second protective layer 62 and the surface of metal level 61 through vacancy section 71
It can be spread to both sides.And more up the time of its contact etching solution is also longer, and the amount of etching solution toward two lateral erosions is bigger,
Therefore trapezoidal raceway groove 65 can be formed on source-drain electrode layer 60.
Preferably, the etching solution can select H2O2, metal-chelator or organic acid etc..
S004：Dry etching is carried out to the part for being exposed to the vacancy section of first protective layer, it is described to cause
The part for being exposed to the vacancy section of first protective layer and the remainder of first protective layer separate.
Specifically, please refer to Fig. 5.Etching gas can be placed in environment under low pressure, and impose voltage, by etching gas
Plasma-based is excited into, then first protective layer 50 is bombarded.To etch the first protective layer 50.In plasma-based to the first protective layer
During 50 are bombarded, after plasma-based enters raceway groove 65, reflection bounce-back can be produced in the side wall 651 in raceway groove 65.Therefore, exist
The bottom of raceway groove 65 (the first protective layer 50) can be initially formed slit 66 with the intersection of side wall 651, close on intersection relative intermediate position
Etching speed faster.Therefore the presentation of metal oxide semiconductor layer 40 below intersection is on first protective layer 50
Slit 66.In other words, the part 51 for being exposed to the vacancy section 71 of first protective layer 50 and the described first protection
Slit 66 is formed between the remainder 52 of layer 50, what the slit 66 separated first protective layer 50 is exposed to the hollow out
The part 51 in area 71 and the remainder 52 of first protective layer.The part of metal oxide semiconductor layer 40 is exposed to institute
State slit 66.As long as some is exposed to first protective layer 50 for metal oxide semiconductor layer 40, then electronics moves
The passage can of shifting is formed.That is, without the first protective layer 50 is etched completely, in dry etch process is carried out,
First protective layer 50 can play a part of protect metal oxide semiconductor layer 40, avoid metal oxide semiconductor layer 40 by
The surface quality caused by etching declines, influences electron transfer rate etc., so as to lift the basic performance of array.
Referring to Fig. 6, after slit 66 is formed, dry etching can be stopped, and remove the photoresist layer 70, and after continuation
Continuous step, completes the making of array base palte.Subsequent step is not the emphasis that the present invention protects, and here is omitted.
Preferably, the selection that the etching gas can be appropriate, such as select SF6、O2、Cl2, it is a kind of in He, Ar (argon gas)
Or any several mixing etc..
In the manufacture method of the array base palte of the application, source-drain electrode layer and the first protective layer are etched twice, first
It is secondary to be first fully etched source-drain electrode layer, then the first protective layer is etched by the method for dry etching for the second time, so that
Obtain the metal oxide semiconductor layer part and be exposed to first protective layer, the first protective layer described in dry etch process
The metal oxide semiconductor layer can be protected to be not etched by, avoid metal oxide semiconductor layer surface is destroyed from (being formed
Wedge angle and pit), the surface quality of metal oxide semiconductor layer is ensure that, ensure that electron mobility, lifts array base palte
Performance.
Referring to Fig. 6, the application also provides a kind of array base palte 100.Array base palte 100 includes being cascadingly set on base
Grid 20, gate insulator 30, metal oxide semiconductor layer 40, the first protective layer 50 and the source-drain electrode layer 60 of plate 10.It is described
Source-drain electrode layer 60 is provided with the raceway groove 65 for leading to first protective layer 50.Further, source-drain electrode layer 60 includes the He of source electrode 63
Drain electrode 64, the raceway groove 65 are arranged between the source electrode 63 and the drain electrode 64.First protective layer 50 is exposed to institute
The part 51 and the remainder 52 of first protective layer 50 for stating raceway groove separate.
In the array base palte of the application, covered with the first protection on metal oxide semiconductor layer and gate insulator
Layer, and the part that the first protective layer is located in raceway groove separates with its protective layer other parts so that and the first protective layer is located at ditch
Part in road can protect metal oxide semiconductor layer injury-free in trenches are formed, and ensure that metal oxide
The surface quality of semiconductor layer, ensure that electron mobility, lift the performance of array base palte.
Further, the part 51 for being exposed to the vacancy section of first protective layer 50 and first protective layer it
Slit 66 is provided between remainder 52, the slit separates the part 51 for being exposed to the vacancy section of first protective layer
With the remainder 52 of first protective layer.
Specifically, the raceway groove 65 is trapezoidal raceway groove.Described in wet etching during raceway groove 65, because etching solution is through vacancy section 71
It can be spread after into the second protective layer 62 and the surface of metal level 61 to both sides.And more up it contacts the time of etching solution also just
Longer, the amount of etching solution toward two lateral erosions is bigger, therefore trapezoidal raceway groove 65 can be formed on source-drain electrode layer 60.
Preferably, first protective layer 50 can be made of the material different from metal oxide semiconductor layer 50,
Such as can be GZO materials.Preferably, the source-drain electrode layer 60 includes the protective layer 62 of metal level 61 and second being stacked.
The protective layer of metal level 61 and second can be sequentially formed on first protective layer 50 by sputtering method or the method for thermal evaporation
62。
Optionally, the material of the second protective layer 62 can be identical with the material of the first protective layer 50.Described second protects
Sheath 62 is used to prevent the metal level 61 to be oxidized.The metal level 61 can select the metal such as Cr, W, Cu, Ti, Ta, Mo or
Alloy, the barrier metal layer being made up of multiple layer metal can also meet needs.Preferably, copper or Cu alloy material can be selected to be made.
The embodiment of the present application is described in detail above, specific case used herein to the principle of the application and
Embodiment is set forth, and the explanation of above example is only intended to help and understands the present processes and its core concept；
Meanwhile for those of ordinary skill in the art, according to the thought of the application, can in specific embodiments and applications
There is change part, in summary, this specification content should not be construed as the limitation to the application.
Claims (18)
1. a kind of manufacture method of array base palte, it is characterised in that methods described includes：
Grid, gate insulator, metal oxide semiconductor layer, the first protective layer and source-drain electrode layer are sequentially formed on substrate；
Photoresist layer is formed on the source-drain electrode layer, vacancy section is provided with the photoresist layer；
The part for being exposed to the vacancy section of the source-drain electrode layer is removed, to expose first protective layer；
Dry etching is carried out to the part for being exposed to the vacancy section of first protective layer, to cause first protective layer
The part for being exposed to the vacancy section and first protective layer remainder separate.
2. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the dew to first protective layer
Part for the vacancy section carries out dry etching, to cause the part for being exposed to the vacancy section of first protective layer
With in the remainder cut-off step of first protective layer, being banged including the use of etching gas first protective layer
Hit, to cause between the remainder of the part for being exposed to the vacancy section of first protective layer and first protective layer
Form slit, the slit separate first protective layer the part for being exposed to the vacancy section and first protective layer it
Remainder.
3. the manufacture method of array base palte as claimed in claim 2, it is characterised in that the etching gas is SF6、O2、Cl2、
A kind of or arbitrarily several mixing in He, Ar.
4. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the dew for removing the source-drain electrode layer
For the part of the vacancy section, to expose in the first protective layer step, it is included in the source-drain electrode layer spray etching liquid
It is etched, the etching solution is removed after first protective layer is completely exposed.
5. the manufacture method of array base palte as claimed in claim 4, it is characterised in that the dew for removing the source-drain electrode layer
For the part of the vacancy section, to expose in the first protective layer step, it is included in the source-drain electrode layer spray etching liquid
It is etched, to form trapezoidal raceway groove on the source-drain electrode layer, after first protective layer is exposed to the trapezoidal raceway groove
Remove the etching solution.
6. the manufacture method of array base palte as claimed in claim 5, it is characterised in that the dew for removing the source-drain electrode layer
For the part of the vacancy section, to expose in the first protective layer step, by the concentration and the institute that control the etching solution
State etching period of the etching solution in the source-drain electrode layer so that first protective layer is completely exposed in the trapezoidal raceway groove, its
In, the concentration of the etching solution and the etching period are preset value.
7. the manufacture method of array base palte as claimed in claim 4, it is characterised in that the etching solution includes H2O2, metal chelating
Mixture or organic acid.
8. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described that grid are sequentially formed on substrate
In pole, gate insulator, metal oxide semiconductor layer, the first protective layer and source-drain electrode layer step, including existed by sputtering method
First protective layer and the source-drain electrode layer are sequentially formed on the metal oxide semiconductor layer.
9. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the metal oxide uses IGZO materials
Material, first protective layer use GZO materials.
10. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the source-drain electrode layer is set including stacking
The metal level and the second protective layer put, are formed in the source-drain electrode layer step, including by sputtering method in first protective layer
On sequentially form metal level and the second protective layer.
11. the manufacture method of array base palte as claimed in claim 10, it is characterised in that second protective layer uses GZO
Material.
12. a kind of array base palte, it is characterised in that grid, gate insulator, metal oxygen including being cascadingly set on substrate
Compound semiconductor layer, the first protective layer and source-drain electrode layer, the source-drain electrode layer are provided with the raceway groove for leading to first protective layer,
The part for being exposed to the raceway groove of first protective layer and the remainder of first protective layer separate.
13. array base palte as claimed in claim 12, it is characterised in that first protective layer is exposed to the vacancy section
Part and first protective layer remainder between be provided with slit, the slit separates exposing for first protective layer
In the part of the vacancy section and the remainder of first protective layer.
14. array base palte as claimed in claim 12, it is characterised in that the raceway groove is trapezoidal raceway groove.
15. array base palte as claimed in claim 12, it is characterised in that the source-drain electrode layer includes the metal level being stacked
With the second protective layer, the metal level is between first protective layer and second protective layer.
16. array base palte as claimed in claim 14, it is characterised in that second protective layer uses GZO materials.
17. array base palte as claimed in claim 12, it is characterised in that the metal oxide uses IGZO materials, described
First protective layer uses GZO materials.
18. array base palte as claimed in claim 12, it is characterised in that the source-drain electrode layer uses copper or Cu alloy material system
Into.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2016/103795 WO2018076285A1 (en) | 2016-10-28 | 2016-10-28 | Array substrate and method for manufacturing same |
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| CN107810556B CN107810556B (en) | 2021-12-28 |
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Cited By (2)
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|---|---|---|---|---|
| CN111740001A (en) * | 2020-01-20 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device and method of forming the same |
| WO2023173507A1 (en) * | 2022-03-16 | 2023-09-21 | Tcl华星光电技术有限公司 | Tft substrate and manufacturing method therefor, liquid crystal display and oled display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257879B (en) * | 2021-05-25 | 2022-07-15 | 厦门天马微电子有限公司 | Array substrate and display panel |
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| CN101246909A (en) * | 2007-02-16 | 2008-08-20 | 三星电子株式会社 | Thin film transistor and method of forming the same |
| US20130320317A1 (en) * | 2012-06-05 | 2013-12-05 | Innolux Corporation | Thin film transistor substrate and display |
| US20150102317A1 (en) * | 2013-10-15 | 2015-04-16 | Samsung Display Co., Ltd. | Thin film transistor substrates, display devices and methods of manufacturing display devices |
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| US20110263079A1 (en) * | 2010-04-23 | 2011-10-27 | Applies Materials, Inc. | Interface protection layaer used in a thin film transistor structure |
| KR102050438B1 (en) * | 2012-11-29 | 2020-01-09 | 엘지디스플레이 주식회사 | Method for fabricating oxide thin film transistor |
| KR102080065B1 (en) * | 2013-04-30 | 2020-04-07 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and method for fabricating the same |
| CN104934330A (en) * | 2015-05-08 | 2015-09-23 | 京东方科技集团股份有限公司 | Film transistor and preparation method thereof, array substrate and display panel |
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| CN101246909A (en) * | 2007-02-16 | 2008-08-20 | 三星电子株式会社 | Thin film transistor and method of forming the same |
| US20130320317A1 (en) * | 2012-06-05 | 2013-12-05 | Innolux Corporation | Thin film transistor substrate and display |
| US20150102317A1 (en) * | 2013-10-15 | 2015-04-16 | Samsung Display Co., Ltd. | Thin film transistor substrates, display devices and methods of manufacturing display devices |
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| CN111740001A (en) * | 2020-01-20 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device and method of forming the same |
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| WO2018076285A1 (en) | 2018-05-03 |
| CN107810556B (en) | 2021-12-28 |
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