CN107799518A - 一种双向npn穿通型超低压tvs结构及其制备方法 - Google Patents
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Abstract
一种双向NPN穿通型超低压TVS结构及其制备方法,随着半导体IC制造工艺最小线宽的不断降低,半导体IC的工作电压也变得越来越低,工作电压从最初的5V降低到3.3V,再从3.3V降低到2.5V,这就需要作为过压保护的TVS击穿电压也要相应的降低,以便更好地保护半导体IC,当二极管TVS击穿电压低于5V后,齐纳击穿的隧道效应会导致击穿曲线软化,漏电增大至1E‑5A的水平,漏电增大会导致功耗增大,发热量增大等等一系列问题,此发明的双向NPN穿通型TVS既能做到击穿电压低于5V,同时又能保证优秀的击穿曲线,且漏电低至1E‑9A的水平。
Description
技术领域
本发明属于一种TVS结构及其制备方法,此TVS适用于保护超低工作电压的半导体IC。
背景技术
随着半导体IC的集成度不断提升,半导体制造工艺最小线宽的不断降低,半导体IC能承载的最大功率变得更低,这就需要半导体IC工作电压变得比原来要低,才能有效降低半导体IC承载的功率。近些年,半导体IC的工作电压从5V降低到了3.3V,后来又从3.3V降低到了2.5V,这就需要作为过压保护的TVS击穿电压也要相应的降低,以便更好地保护半导体IC,当二极管TVS击穿电压低于5V后,齐纳击穿的隧道效应会导致击穿曲线软化,漏电增大至1E-5A的水平,漏电增大会导致功耗增大,发热量增大等等一系列问题,此发明的双向NPN穿通型TVS既能做到击穿电压低于5V,同时又能保证优秀的击穿曲线,且漏电低至1E-9A的水平。
发明内容
1、一种双向NPN穿通型超低压TVS结构,其结构包括:NPN1区301、NP1区302、DN隔离区303、DN连通区304、NPN2区305及NP2区306。
A、NPN1区301结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,钝化层部分打开,其中,DP与衬底相连,SN与正面金属相连且通过正面金属与NP1区302的SN相连。
B、NP1区302结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN和SP,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中,DP与衬底相连,SN与正面金属相连,且SN通过正面金属与NPN1区301的SN相连,SP与正面金属相连,且SP通过正面金属与DN连通区304的SN相连,NP1区302内的SN与SP不相连。
C、DN隔离区303结构包括:衬底上面是外延层,衬底和外延层里面包含DN,DN里面包含SN,外延层上面是SiO2层,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中DN与衬底相连。
D、DN连通区304结构包括:衬底上面是外延层,衬底和外延层里面包含DN,DN里面包含SN,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中DN与衬底相连,SN与正面金属相连,且通过正面金属与NP1区302及NP2区306的SP相连。
E、NPN2区305结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,钝化层部分打开,其中,DP与衬底相连,SN与正面金属相连且通过正面金属与NP2区306的SN相连,NPN1区301的正面金属与NPN2区305的正面金属不相连。
F、NP2区306结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN和SP,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中,DP与衬底相连,SN与正面金属相连,且SN通过正面金属与NPN区2305的SN相连,SP与正面金属相连,且SP通过正面金属与DN连通区304的SN相连,NP2区306内的SN与SP不相连,NP1区302的正面金属与NP2区306的正面金属相连。
2、一种双向NPN穿通型超低压TVS的制备方法,其方法包括:
A、衬底211的准备及外延层212的制备,在N型低阻单晶硅上,生长P型高阻单晶硅层;
B、DN221制备,通过POCL3工艺掺杂,高温扩散至DN与衬底211连通;
C、SP231制备,离子注入高浓P型杂质;
D、DP241制备,离子注入P型杂质,高温退火;
E、SN251制备,通过POCL3工艺掺杂P元素,高温退火;
F、引线孔制备,SiO2层261淀积,光刻,SiO2刻蚀;
G、正面金属271制备,金属层淀积,光刻,金属层刻蚀,去胶;
H、钝化层281制备,SiO2淀积,SiN淀积,光刻,SiN刻蚀,SiO2刻蚀,去胶;
I、根据封装要求进行背面减薄。
附图说明
图1是此发明双向NPN穿通型超低压TVS的等效电路图;
图2是此发明双向NPN穿通型超低压TVS的工艺截面图;
图3是此发明双向NPN穿通型超低压TVS的区域划分图。
编号说明
101:雪崩二极管1,简称:雪崩1管;
102:串联整流二极管1,简称:串1管;
103:并联整流二极管1,简称:并1管;
104:雪崩二极管2,简称:雪崩2管;
105:串联整流二极管2,简称:串2管;
106:并联整流二极管2,简称:并2管;
107:I/O电极pin1;
108:I/O电极pin2;
211:衬底,本发明衬底为N型低阻单晶硅;
212:外延层,本发明外延为P型单晶硅;
221:DN,隔离以及连接衬底211的通道;
231:SP,作用是与正面金属271形成欧姆接触;
241:DP,TVS击穿时的穿通区,雪崩二极管P区,串联整流二极管的P区,以及并联整流二极管的P区;
251:SN,TVS雪崩二极管的N区,以及DN221和正面金属271的欧姆接触区;
261:SiO2层,作用是隔离外延层212与正面金属271层,使其之间绝缘;
271:正面金属,用做二极管之间的布线及TVS的电极,暴露在外的部分用做电极;
281:钝化层,作用是提高器件可靠性,通常使用SiO2层+SiN层;
301:TVS的NPN1区,雪崩1管101和串1管102所在区域;
302:TVS的NP1区,并1管103所在区域;
303:TVS的DN隔离区,PN节隔离区域;
304:TVS的DN连通区,实现并1管103和并2管(106)的P区与衬底连接;
305:TVS的NPN2区,雪崩2管104和串2管105所在区域;
306:TVS的NP2区,并2管106所在区域。
具体实施方式
1.衬底211的准备及外延层212的制备,在N型低阻单晶硅上,生长P型高阻单晶硅层。衬底的浓度、外延的浓度及厚度对TVS电参数有重要影响。
2.DN221制备,通过POCL3工艺掺杂,高温扩散至DN与衬底211连通,作用是隔离及连接衬底。由于DN不是关键工艺,所以做在工艺流程的前部分,可以避免DN的热过程对关键工艺照成过多的热影响,导致工艺难以控制。
3.SP231制备,离子注入大剂量P型杂质,通常注入B元素。SP和DN金属相连,只要做到欧姆接触即可。
4.DP241制备,离子注入P型杂质,高温退火。DP是雪崩二极管的P区,同时是串联整流二极管的P区,也是TVS击穿时的穿通区域,以及并联整流二极管的P区,作为关键工艺,直接影响到TVS的击穿电压,同时也影响串联整流二极管和并联整流二极管的击穿电压、电容、漏电等关键电参数。
5.SN251制备,通过POCL3工艺掺杂P元素,高温退火。除了引线功能之外,SN的结深直接关系到NPN穿通区的宽度,SN的浓度直接关系到TVS的击穿电压。
6.引线孔制备,SiO2层261淀积,光刻,SiO2刻蚀。
7.正面金属271制备,金属层淀积,光刻,金属层刻蚀,去胶,用做I/O电极及二极管之间的布线。
8.钝化层281制备,SiO2淀积,SiN淀积,光刻,SiN刻蚀,SiO2刻蚀,去胶。
9.背面减薄,根据封装对芯片厚度的要求进行背面减薄。
通过上述实施例阐述了本发明,同时也可以采用其它实施例实现本发明。本发明不局限于上述具体实施例,因此本发明有所附权利要求范围限定。
Claims (2)
1.一种双向NPN穿通型超低压TVS结构,其结构包括:NPN1区301、NP1区302、DN隔离区303、DN连通区304、NPN2区305及NP2区306,
A、NPN1区301结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,钝化层部分打开,其中,DP与衬底相连,SN与正面金属相连且通过正面金属与NP1区302的SN相连;
B、NP1区302结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN和SP,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中,DP与衬底相连,SN与正面金属相连,且SN通过正面金属与NPN1区301的SN相连,SP与正面金属相连,且SP通过正面金属与DN连通区304的SN相连,NP1区302内的SN与SP不相连;
C、DN隔离区303结构包括:衬底上面是外延层,衬底和外延层里面包含DN,DN里面包含SN,外延层上面是SiO2层,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中DN与衬底相连;
D、DN连通区304结构包括:衬底上面是外延层,衬底和外延层里面包含DN,DN里面包含SN,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中DN与衬底相连,SN与正面金属相连,且通过正面金属与NP1区302及NP2区306的SP相连;
E、NPN2区305结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,钝化层部分打开,其中,DP与衬底相连,SN与正面金属相连且通过正面金属与NP2区306的SN相连,NPN1区301的正面金属与NPN2区305的正面金属不相连;
F、NP2区306结构包括:衬底上面是外延层,衬底和外延层里面包含DP,DP里面包含SN和SP,外延层上面是SiO2层,SiO2层部分打开,SiO2层上面是正面金属,正面金属部分打开,正面金属上面是钝化层,其中,DP与衬底相连,SN与正面金属相连,且SN通过正面金属与NPN2区305的SN相连,SP与正面金属相连,且SP通过正面金属与DN连通区304的SN相连,NP2区306内的SN与SP不相连,NP1区302的正面金属与NP2区306的正面金属相连。
2.一种双向NPN穿通型超低压TVS的制备方法,其方法包括:
A、衬底211的准备及外延层212的制备,在N型低阻单晶硅上,生长P型高阻单晶硅层;
B、DN221制备,通过POCL3工艺掺杂,高温扩散至DN与衬底211连通;
C、SP231制备,离子注入高浓P型杂质;
D、DP241制备,离子注入P型杂质,高温退火;
E、SN251制备,通过POCL3工艺掺杂P元素,高温退火;
F、引线孔制备,SiO2层261淀积,光刻,SiO2刻蚀;
G、正面金属271制备,金属层淀积,光刻,金属层刻蚀,去胶;
H、钝化层281制备,SiO2淀积,SiN淀积,光刻,SiN刻蚀,SiO2刻蚀,去胶;
I、根据封装要求进行背面减薄。
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Citations (10)
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