CN107799409A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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Abstract
一种半导体结构的形成方法,包括:形成基底,包括第一区域和第二区域;形成伪栅结构;形成开口;形成第一栅介质层和第二栅介质层;形成牺牲层;形成第一材料层;形成第一掩膜;露出所述第二栅介质层;露出所述第一材料层;形成第二材料层。与仅靠所述第一材料层保护所述第二栅介质层的现有技术相比,本发明技术方案中,所述第一材料层和所述牺牲层的总厚度较大,对所述第二栅介质层的保护能力更强,能够有效的减少第二栅介质层在第一掩膜形成过程中受损,有利于提高栅介质层的性能,改善所形成半导体结构的性能。
A method for forming a semiconductor structure, comprising: forming a base, including a first region and a second region; forming a dummy gate structure; forming an opening; forming a first gate dielectric layer and a second gate dielectric layer; forming a sacrificial layer; material layer; forming a first mask; exposing the second gate dielectric layer; exposing the first material layer; forming a second material layer. Compared with the prior art that only relies on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.
Description
技术领域technical field
本发明涉及半导体制造领域,特别涉及一种半导体结构的形成方法。The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
背景技术Background technique
随着半导体制造技术的飞速发展,半导体器件朝着更高的元件密度,以及更高的集成度的方向发展。晶体管作为最基本的半导体器件目前正被广泛应用,因此随着半导体器件的元件密度和集成度的提高晶体管的特征尺寸也越来越小,为了降低晶体管栅极的寄生电容、提高器件速度,高K栅介质层与金属栅极的栅极结构被引入到晶体管中。With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the improvement of component density and integration of semiconductor devices, the feature size of transistors is getting smaller and smaller. In order to reduce the parasitic capacitance of transistor gates and improve device speed, high The gate structure of the K gate dielectric layer and the metal gate is introduced into the transistor.
然而,在高K栅介质层上形成金属栅极时仍有许多问题亟待解决,其中一个就是功函数的匹配问题,因为功函数将直接影响器件的阈值电压(Vt)和晶体管的性能。所以在高K金属栅结构中引入功函数层,从而实现对器件阈值电压的调节。However, there are still many problems to be solved when forming a metal gate on a high-K gate dielectric layer, one of which is the matching of the work function, because the work function will directly affect the threshold voltage (Vt) of the device and the performance of the transistor. Therefore, a work function layer is introduced into the high-K metal gate structure to realize the adjustment of the threshold voltage of the device.
但是即使在高K金属栅结构中引入功函数层,现有技术中半导体结构的性能仍有待提高。However, even if a work function layer is introduced into the high-K metal gate structure, the performance of the semiconductor structure in the prior art still needs to be improved.
发明内容Contents of the invention
本发明解决的问题是提供一种半导体结构的形成方法,以提高半导体结构的性能。The problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
为解决上述问题,本发明提供一种半导体结构的形成方法,包括:In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
形成基底,所述基底包括用于形成晶体管的第一区域和第二区域,且所述第一区域晶体管的阈值电压大于第二区域晶体管的阈值电压;在所述基底上形成伪栅结构;在相邻伪栅结构间的基底上形成介质层;去除所述伪栅结构在所述介质层内形成开口;在所述开口底部形成栅介质层,位于所述第一区域介质层内开口底部的栅介质层为第一栅介质层,位于所述第二区域介质层内开口底部的栅介质层为第二栅介质层;在所述第二栅介质层上形成牺牲层;在所述第一栅介质层和牺牲层上形成第一材料层;形成位于所述第一材料层上的第一掩膜,所述第一掩膜露出所述第二栅介质层上的第一材料层;以所述第一掩膜为掩膜,去除所述第二栅介质层上的第一材料层和牺牲层,露出所述第二栅介质层;去除所述第一掩膜,露出所述第一栅介质层上的所述第一材料层;在所述第一栅介质层的第一材料层和所述第二栅介质层上形成第二材料层。forming a substrate, the substrate includes a first region and a second region for forming a transistor, and the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region; forming a dummy gate structure on the substrate; Forming a dielectric layer on the substrate between adjacent dummy gate structures; removing the dummy gate structure to form an opening in the dielectric layer; forming a gate dielectric layer at the bottom of the opening, located at the bottom of the opening in the dielectric layer in the first region The gate dielectric layer is a first gate dielectric layer, and the gate dielectric layer at the bottom of the opening in the second region dielectric layer is a second gate dielectric layer; a sacrificial layer is formed on the second gate dielectric layer; forming a first material layer on the gate dielectric layer and the sacrificial layer; forming a first mask on the first material layer, the first mask exposing the first material layer on the second gate dielectric layer; The first mask is a mask, and the first material layer and the sacrificial layer on the second gate dielectric layer are removed to expose the second gate dielectric layer; the first mask is removed to expose the first The first material layer on the gate dielectric layer; forming a second material layer on the first material layer of the first gate dielectric layer and the second gate dielectric layer.
与现有技术相比,本发明的技术方案具有以下优点:Compared with the prior art, the technical solution of the present invention has the following advantages:
本发明技术方案,在形成栅介质层后,在第二栅介质层上形成牺牲层,在牺牲层上形成第一材料层;在形成第一掩膜的过程中,以所述牺牲层和所述第一材料层保护所述第二栅介质层。与仅靠所述第一材料层保护所述第二栅介质层的技术方案相比,本发明技术方案中,所述第一材料层和所述牺牲层的总厚度较大,对所述第二栅介质层的保护能力更强,能够有效的减少第二栅介质层在第一掩膜形成过程中受损,有利于提高栅介质层的性能,改善所形成半导体结构的性能。In the technical solution of the present invention, after forming the gate dielectric layer, a sacrificial layer is formed on the second gate dielectric layer, and a first material layer is formed on the sacrificial layer; in the process of forming the first mask, the sacrificial layer and the The first material layer protects the second gate dielectric layer. Compared with the technical solution of only relying on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the second The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.
附图说明Description of drawings
图1至图5是一种半导体结构形成方法各个步骤对应的剖面结构示意图。1 to 5 are schematic cross-sectional structure diagrams corresponding to each step of a method for forming a semiconductor structure.
图6至图16是本发明半导体结构形成方法一实施例各个步骤对应的剖面结构示意图。6 to 16 are schematic cross-sectional structure diagrams corresponding to each step of an embodiment of the semiconductor structure forming method of the present invention.
具体实施方式Detailed ways
由背景技术可知,现有技术中的引入功函数层的半导体结构存在性能不良的问题。现结合一种半导体结构的形成方法分析其性能不良问题的原因:It can be seen from the background art that the semiconductor structure introducing the work function layer in the prior art has the problem of poor performance. Now combine the formation method of a semiconductor structure to analyze the reasons for its poor performance:
参考图1至图5,示出了一种半导体结构形成方法各个步骤对应的剖面结构示意图。Referring to FIG. 1 to FIG. 5 , schematic cross-sectional structure diagrams corresponding to each step of a method for forming a semiconductor structure are shown.
参考图1,提供基底10,所述基底10包括用于形成N型晶体管的第一区域10a和第二区域10b,所述第一区域晶体管的阈值电压大于所述第二区域10b晶体管的阈值电压。1, a substrate 10 is provided, the substrate 10 includes a first region 10a and a second region 10b for forming an N-type transistor, the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region 10b .
继续参考图1,在所述基底10上形成栅介质层,位于第一区域10a基底10上的栅介质层为第一栅介质层11a,位于第二区域10b基底10上的栅介质层为第二栅介质层11b;在所述栅介质层上形成第一材料层12,所述第一材料层12位于所述第一栅介质层11a和所述第二栅介质层11b上。Continuing to refer to FIG. 1, a gate dielectric layer is formed on the substrate 10, the gate dielectric layer on the substrate 10 in the first region 10a is the first gate dielectric layer 11a, and the gate dielectric layer on the substrate 10 in the second region 10b is the second gate dielectric layer. The second gate dielectric layer 11b; forming a first material layer 12 on the gate dielectric layer, and the first material layer 12 is located on the first gate dielectric layer 11a and the second gate dielectric layer 11b.
参考图2,在所述第一材料层12上形成底部抗反射层13;在所述底部抗反射层13上形成图形层14,所述图形层14露出所述第二栅介质层11b上的底部抗反射层13。Referring to FIG. 2, a bottom antireflection layer 13 is formed on the first material layer 12; a graphic layer 14 is formed on the bottom antireflective layer 13, and the graphic layer 14 exposes the Bottom anti-reflection layer 13.
参考图3,去除所述第二栅介质层11b上的底部抗反射层13(如图2所示),露出所述第二栅介质层11b上的第一材料层12。Referring to FIG. 3 , the bottom anti-reflection layer 13 on the second gate dielectric layer 11 b (as shown in FIG. 2 ) is removed to expose the first material layer 12 on the second gate dielectric layer 11 b.
参考图4,去除露出的所述第一材料层12(如图3所示),露出所述第二栅介质层11b。Referring to FIG. 4 , the exposed first material layer 12 (as shown in FIG. 3 ) is removed to expose the second gate dielectric layer 11b.
参考图5,去除所述图形层14以及剩余的所述底部抗反射层13(如图4所示),露出所述第一材料层12;形成位于所述第一材料层12和所述第二栅介质层11b上的第二材料层16。With reference to Fig. 5, remove described graphic layer 14 and remaining described bottom anti-reflection layer 13 (as shown in Fig. 4), expose described first material layer 12; The second material layer 16 on the second gate dielectric layer 11b.
由于所述第一区域晶体管的阈值电压大于所述第二区域晶体管的阈值电压,因此所述第一区域10a基底10所形成N型晶体管功函数层的厚度大于所述第二区域10b基底10所形成N型晶体管功函数层的厚度。Since the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region, the thickness of the N-type transistor work function layer formed on the substrate 10 in the first region 10a is greater than that in the substrate 10 in the second region 10b. Form the thickness of the N-type transistor work function layer.
所以第一栅介质层11a上的所述第一材料层12和所述第二材料层16形成第一功函数层;所述第二栅介质层11b上的所述第二材料层16形成所述第二功函数层,从而使所述第一区域10a基底10所形成N型晶体管功函数层的厚度大于所述第二区域10b基底10所形成N型晶体管功函数层的厚度。而且所述第一材料层12的厚度与所述第一功函数层和所述第二功函数层的厚度差相等,约为 Therefore, the first material layer 12 and the second material layer 16 on the first gate dielectric layer 11a form the first work function layer; the second material layer 16 on the second gate dielectric layer 11b forms the The second work function layer, so that the thickness of the N-type transistor work function layer formed on the substrate 10 in the first region 10a is greater than the thickness of the N-type transistor work function layer formed on the substrate 10 in the second region 10b. Moreover, the thickness of the first material layer 12 is equal to the thickness difference between the first work function layer and the second work function layer, about
所以在第一材料层12上形成的底部抗反射层13需要露出所述第二栅介质层11b上的第一材料层12以便去除。现有技术常常采用干法刻蚀15(如图3所示)的方式去除所述第二栅介质层11b上的底部抗反射层13,以露出所述第二栅介质层11b上的第一材料层12。由于所述第一材料层12的厚度较小,仅为左右,因此所述第一材料层12对下方的所述第二栅介质层11b的保护能力有限。所以采用干法刻蚀15去除所述第二栅介质层11b上的底部抗反射层13的做法,常常会使所述第二栅介质层11b受损,从而造成所形成半导体结构的性能不良。Therefore, the bottom anti-reflection layer 13 formed on the first material layer 12 needs to expose the first material layer 12 on the second gate dielectric layer 11b for removal. In the prior art, dry etching 15 (as shown in FIG. 3 ) is often used to remove the bottom anti-reflection layer 13 on the second gate dielectric layer 11b, so as to expose the first material layer 12. Due to the small thickness of the first material layer 12, only Therefore, the ability of the first material layer 12 to protect the second gate dielectric layer 11b below is limited. Therefore, the method of removing the bottom anti-reflection layer 13 on the second gate dielectric layer 11b by dry etching 15 will often damage the second gate dielectric layer 11b, thus resulting in poor performance of the formed semiconductor structure.
为解决所述技术问题,本发明提供一种半导体结构的形成方法,包括:In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising:
形成基底,所述基底包括用于形成晶体管的第一区域和第二区域,且所述第一区域晶体管的阈值电压大于第二区域晶体管的阈值电压;在所述基底上形成伪栅结构;在相邻伪栅结构间的基底上形成介质层;去除所述伪栅结构在所述介质层内形成开口;在所述开口底部形成栅介质层,位于所述第一区域介质层内开口底部的栅介质层为第一栅介质层,位于所述第二区域介质层内开口底部的栅介质层为第二栅介质层;在所述第二栅介质层上形成牺牲层;在所述第一栅介质层和牺牲层上形成第一材料层;形成位于所述第一材料层上的第一掩膜,所述第一掩膜露出所述第二栅介质层上的第一材料层;以所述第一掩膜为掩膜,去除所述第二栅介质层上的第一材料层和牺牲层,露出所述第二栅介质层;去除所述第一掩膜,露出所述第一栅介质层上的所述第一材料层;在所述第一栅介质层的第一材料层和所述第二栅介质层上形成第二材料层。forming a substrate, the substrate includes a first region and a second region for forming a transistor, and the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region; forming a dummy gate structure on the substrate; Forming a dielectric layer on the substrate between adjacent dummy gate structures; removing the dummy gate structure to form an opening in the dielectric layer; forming a gate dielectric layer at the bottom of the opening, located at the bottom of the opening in the dielectric layer in the first region The gate dielectric layer is a first gate dielectric layer, and the gate dielectric layer at the bottom of the opening in the second region dielectric layer is a second gate dielectric layer; a sacrificial layer is formed on the second gate dielectric layer; forming a first material layer on the gate dielectric layer and the sacrificial layer; forming a first mask on the first material layer, the first mask exposing the first material layer on the second gate dielectric layer; The first mask is a mask, and the first material layer and the sacrificial layer on the second gate dielectric layer are removed to expose the second gate dielectric layer; the first mask is removed to expose the first The first material layer on the gate dielectric layer; forming a second material layer on the first material layer of the first gate dielectric layer and the second gate dielectric layer.
本发明技术方案,在形成栅介质层后,在第二栅介质层上形成牺牲层,在牺牲层上形成第一材料层;在形成第一掩膜的过程中,以所述牺牲层和所述第一材料层保护所述第二栅介质层。与仅靠所述第一材料层保护所述第二栅介质层的现有技术相比,本发明技术方案中,所述第一材料层和所述牺牲层的总厚度较大,对所述第二栅介质层的保护能力更强,能够有效的减少第二栅介质层在第一掩膜形成过程中受损,有利于提高栅介质层的性能,改善所形成半导体结构的性能。In the technical solution of the present invention, after forming the gate dielectric layer, a sacrificial layer is formed on the second gate dielectric layer, and a first material layer is formed on the sacrificial layer; in the process of forming the first mask, the sacrificial layer and the The first material layer protects the second gate dielectric layer. Compared with the prior art that only relies on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
图6至图16,示出了本发明半导体结构形成方法一实施例各个步骤对应的剖面结构示意图。FIGS. 6 to 16 show schematic cross-sectional structures corresponding to each step of an embodiment of the semiconductor structure forming method of the present invention.
参考图6,形成基底(图中未标示),所述基底包括用于形成晶体管的第一区域100na和第二区域100nb,且所述第一区域100na晶体管的阈值电压大于所述第二区域100nb晶体管的阈值电压。Referring to FIG. 6, a substrate (not shown in the figure) is formed, the substrate includes a first region 100na and a second region 100nb for forming transistors, and the threshold voltage of transistors in the first region 100na is greater than that of the second region 100nb threshold voltage of the transistor.
所述基底用于为后续半导体工艺提供工艺基础。The substrate is used to provide a process basis for subsequent semiconductor processes.
本实施例中,所述半导体结构为鳍式场效应晶体管,所述基底包括衬底100以及位于所述衬底100上分立的鳍部110。In this embodiment, the semiconductor structure is a fin field effect transistor, and the base includes a substrate 100 and discrete fins 110 on the substrate 100 .
所述衬底100用于为半导体工艺提供操作平台,所述鳍部110用于形成鳍式场效应晶体管。The substrate 100 is used to provide an operating platform for a semiconductor process, and the fin portion 110 is used to form a fin field effect transistor.
本实施例中,形成基底的步骤包括:提供初始衬底;刻蚀所述初始衬底,形成衬底100以及位于所述衬底100上分立的鳍部110。In this embodiment, the step of forming the base includes: providing an initial substrate; etching the initial substrate to form the substrate 100 and the discrete fins 110 on the substrate 100 .
所述初始衬底用于形成衬底100和刻蚀形成鳍部110。本实施例中,所述初始基底的材料为单晶硅。所以所述衬底100和所述鳍部110的材料也为单晶硅。The initial substrate is used to form the substrate 100 and etch to form the fins 110 . In this embodiment, the material of the initial substrate is single crystal silicon. Therefore, the material of the substrate 100 and the fin portion 110 is also single crystal silicon.
在本发明其他实施例中,所述初始衬底的材料还可以选自锗、砷化镓或硅锗化合物;所述初始衬底还可以是其他半导体材料。此外,所述初始衬底还可以选自具有外延层或外延层上硅结构。所述衬底可以选择适于工艺需求或易于集成的衬底;所述半导体层的材料可以选择适于形成鳍部的材料。In other embodiments of the present invention, the material of the initial substrate may also be selected from germanium, gallium arsenide or silicon germanium compounds; the initial substrate may also be other semiconductor materials. In addition, the initial substrate can also be selected from a structure having an epitaxial layer or a silicon-on-epitaxial layer. The substrate can be selected to be suitable for process requirements or easy to integrate; the material of the semiconductor layer can be selected to be suitable for forming fins.
刻蚀所述初始衬底的步骤包括:在所述初始衬底上形成图形化的鳍部掩膜层(图中未示出);以所述鳍部掩膜层为掩膜,刻蚀所述初始衬底,以形成所述衬底100以及位于所述衬底100上分立的鳍部110。所述鳍部掩膜层可以为图形化的光刻胶层、硬掩膜层或多重图形化掩膜工艺形成的掩膜层。The step of etching the initial substrate includes: forming a patterned fin mask layer (not shown in the figure) on the initial substrate; using the fin mask layer as a mask, etching the The initial substrate is used to form the substrate 100 and the discrete fins 110 on the substrate 100 . The fin mask layer may be a patterned photoresist layer, a hard mask layer or a mask layer formed by multiple patterned masking processes.
此外,所述基底还包括位于相邻鳍部110之间的隔离层(图中未标示),所述隔离层的顶部表面低于所述鳍部110的顶部表面,以露出所述鳍部110顶部表面和侧壁的部分表面。所以形成所述衬底100以及所述鳍部110之后,所述形成方法还包括:在相邻鳍部110之间形成所述隔离层。In addition, the base further includes an isolation layer (not shown) between adjacent fins 110 , the top surface of the isolation layer is lower than the top surface of the fins 110 to expose the fins 110 Partial surfaces of the top surface and side walls. Therefore, after forming the substrate 100 and the fins 110 , the forming method further includes: forming the isolation layer between adjacent fins 110 .
所述隔离层用于实现相邻鳍部110之间以及所述半导体结构与衬底100上其他半导体结构之间的电隔离。The isolation layer is used to realize electrical isolation between adjacent fins 110 and between the semiconductor structure and other semiconductor structures on the substrate 100 .
本实施例中,所述隔离层的材料为氧化硅。本发明其他实施例中,所述隔离层的材料还可以为氮化硅或氮氧化硅。需要说明的是,本实施例中,在形成所述隔离层之后,通过湿法刻蚀工艺去除所述鳍部掩膜层,以露出所述鳍部的顶部表面。具体的,由于所述鳍部掩膜层的材料为氮化硅,所以所述湿法刻蚀工艺过程中所采用的刻蚀溶液为磷酸溶液。In this embodiment, the material of the isolation layer is silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride. It should be noted that, in this embodiment, after the isolation layer is formed, the fin mask layer is removed through a wet etching process, so as to expose the top surface of the fin. Specifically, since the material of the fin mask layer is silicon nitride, the etching solution used in the wet etching process is a phosphoric acid solution.
本实施例中,所述第一区域100na的基底和所述第二区域100nb的基底均用于形成N型晶体管。所述第一区域100na的基底所形成N型晶体管的阈值电压高于所述第二区域100nb基底所形成的N型晶体管,也就是说,所述第一区域100na的基底用于形成高阈值电压的N型晶体管,所述第二区域100nb的基底用于形成低阈值电压的N型晶体管。In this embodiment, both the substrate of the first region 100na and the substrate of the second region 100nb are used to form N-type transistors. The threshold voltage of the N-type transistor formed on the substrate of the first region 100na is higher than that of the N-type transistor formed on the substrate of the second region 100nb, that is, the substrate of the first region 100na is used to form a high threshold voltage N-type transistors, the base of the second region 100nb is used to form N-type transistors with low threshold voltage.
此外,所述基底还还包括第三区域100p。具体的,所述第三区域100p的基底用于形成P型晶体管。In addition, the substrate further includes a third region 100p. Specifically, the base of the third region 100p is used to form a P-type transistor.
继续参考图6,在所述基底上形成伪栅结构120。Continuing to refer to FIG. 6 , a dummy gate structure 120 is formed on the substrate.
所述伪栅结构120用于为后续所形成栅极结构占据空间位置。The dummy gate structure 120 is used to occupy a space position for a subsequently formed gate structure.
所述伪栅结构120包括位于所述基底上的伪氧化层和位于所述伪氧化层上的伪栅极。本实施例中,所述伪氧化层的材料为氧化硅;所述伪栅极的材料为多晶硅。The dummy gate structure 120 includes a dummy oxide layer on the substrate and a dummy gate on the dummy oxide layer. In this embodiment, the material of the dummy oxide layer is silicon oxide; the material of the dummy gate is polysilicon.
具体的,形成所述伪栅结构120的步骤包括:在所述基底表面形成氧化层;在所述氧化层上形成栅电极材料层;在所述栅电极材料层上形成栅极掩膜;以所述栅极掩膜为掩膜,刻蚀所述栅电极材料层至露出所述氧化层表面停止,形成所述伪栅极以及被所述伪栅极覆盖的伪氧化层。Specifically, the step of forming the dummy gate structure 120 includes: forming an oxide layer on the surface of the substrate; forming a gate electrode material layer on the oxide layer; forming a gate mask on the gate electrode material layer; The gate mask is a mask, and the gate electrode material layer is etched until the surface of the oxide layer is exposed to form the dummy gate and the dummy oxide layer covered by the dummy gate.
形成所述伪栅结构120之后,所述形成方法还包括形成位于所述伪栅极和所述伪氧化层侧壁的栅极侧墙。所述栅极侧墙为氧化硅-氮化硅-氧化硅的叠层结构。本发明其他实施例中,所栅极侧墙也可以是氮化硅等材料的单层结构。After forming the dummy gate structure 120 , the forming method further includes forming gate spacers located on sidewalls of the dummy gate and the dummy oxide layer. The gate spacer is a stacked structure of silicon oxide-silicon nitride-silicon oxide. In other embodiments of the present invention, the gate spacer can also be a single-layer structure of silicon nitride or other materials.
本实施例中,所述半导体结构为鳍式场效应晶体管,所以形成所述伪栅结构120的步骤包括:形成位于所述鳍部110上的伪栅结构120,所述伪栅结构120横跨所述鳍部110且覆盖所述鳍部110顶部和侧壁的部分表面。In this embodiment, the semiconductor structure is a fin field effect transistor, so the step of forming the dummy gate structure 120 includes: forming the dummy gate structure 120 on the fin portion 110, and the dummy gate structure 120 straddles the The fin 110 covers part of the top and sidewall of the fin 110 .
继续参考图6,在相邻伪栅结构120间的基底上形成介质层130。Continuing to refer to FIG. 6 , a dielectric layer 130 is formed on the substrate between adjacent dummy gate structures 120 .
所述介质层130为层间介质层,用于实现半导体结构之间的电隔离。The dielectric layer 130 is an interlayer dielectric layer for realizing electrical isolation between semiconductor structures.
本实施例中,所述介质层130的材料为氧化硅。在本发明其他实施例中,所述介质层的材料还可以选自氮化硅、氮氧化硅、低K介质材料(介电常数大于或等于2.5、小于3.9)或超低K介质材料(介电常数小于2.5)中的一种或多种组合。In this embodiment, the material of the dielectric layer 130 is silicon oxide. In other embodiments of the present invention, the material of the dielectric layer can also be selected from silicon nitride, silicon oxynitride, low K dielectric material (dielectric constant greater than or equal to 2.5, less than 3.9) or ultra-low K dielectric material (dielectric constant One or more combinations of electrical constants less than 2.5).
形成所述介质层130的步骤包括:在相邻鳍部110之间的衬底100上形成介质材料层,所述介质材料层的顶部表面高于所述栅极掩膜层;对所述介质材料层进行平坦化处理至露出所述伪栅极停止。所以对所述介质材料层的平坦化处理还去除了所述栅极掩膜层,使所形成的介质层130与所述伪栅极的顶部表面齐平,露出所述伪栅极的顶部表面。The step of forming the dielectric layer 130 includes: forming a dielectric material layer on the substrate 100 between adjacent fins 110, the top surface of the dielectric material layer is higher than the gate mask layer; The material layer is planarized until the dummy gate is exposed. Therefore, the planarization process to the dielectric material layer also removes the gate mask layer, so that the formed dielectric layer 130 is flush with the top surface of the dummy gate, exposing the top surface of the dummy gate .
需要说明的是,形成伪栅结构120之后,形成介质层130之前,所述形成方法还包括:在所述伪栅结构120两侧的基底内形成应力层(图中未标示)。It should be noted that, after forming the dummy gate structure 120 and before forming the dielectric layer 130 , the forming method further includes: forming a stress layer (not shown in the figure) in the substrate on both sides of the dummy gate structure 120 .
所述应力层用于形成半导体结构的源区或漏区。The stress layer is used to form a source region or a drain region of the semiconductor structure.
需要说明的是,本实施例中,由于所述第一区域100na的基底和所述第二区域100nb的基底用于形成N型晶体管,所述第三区域100p的基底用于形成P型晶体管。所以所述第一区域100na基底内和所述第二区域100nb基底内所形成的应力层为碳硅材料的“方形”应力层,所述第三区域100p基底内所形成的应力层为锗硅材料的“∑形”应力层。It should be noted that, in this embodiment, since the substrate of the first region 100na and the substrate of the second region 100nb are used to form an N-type transistor, the substrate of the third region 100p is used to form a P-type transistor. Therefore, the stress layer formed in the substrate of the first region 100na and the substrate of the second region 100nb is a "square" stress layer of carbon silicon material, and the stress layer formed in the substrate of the third region 100p is silicon germanium The "Σ-shaped" stress layer of the material.
还需要说明的是,在形成应力层之后,形成介质层130之前,所述形成方法还包括:形成覆盖所述基底、所述应力层以及所述栅极侧墙侧壁的接触孔刻蚀停止层(图中未标示)。It should also be noted that after forming the stress layer and before forming the dielectric layer 130, the forming method further includes: forming a contact hole etching stop covering the substrate, the stress layer, and the sidewall of the gate spacer. layers (not shown in the figure).
所述应力层和所述接触孔刻蚀停止层的形成方法与现有技术相同,本发明在此不再赘述。The methods for forming the stress layer and the contact hole etching stop layer are the same as those in the prior art, and the present invention will not repeat them here.
参考图7,去除所述伪栅结构120(如图6所示),在所述介质层130内形成开口121。Referring to FIG. 7 , the dummy gate structure 120 (as shown in FIG. 6 ) is removed, and an opening 121 is formed in the dielectric layer 130 .
所述开口121用于为后续形成栅极结构提供工艺空间。The opening 121 is used to provide a process space for subsequent formation of a gate structure.
形成所述开口121的步骤包括:去除所述伪栅极露出所述为栅极下方的伪氧化层;去除所述伪氧化层,形成所述开口121,所述开口121的底部露出所述基底表面。具体的,所述伪栅极和所述伪氧化层可以通过干法刻蚀的方式去除。The step of forming the opening 121 includes: removing the dummy gate to expose the dummy oxide layer under the gate; removing the dummy oxide layer to form the opening 121, and the bottom of the opening 121 exposes the substrate surface. Specifically, the dummy gate and the dummy oxide layer can be removed by dry etching.
本实施例中,所述半导体结构为鳍式场效应晶体管,且所述基底包括第一区域100na、第二区域100nb以及第三区域100p。所以形成开口的步骤包括:去除所述伪栅结构120,分别在所述第一区域100na的介质层130内、在所述第二区域100nb的介质层130内以及在所述第三区域100p的介质层130内形成开口121。In this embodiment, the semiconductor structure is a FinFET, and the substrate includes a first region 100na, a second region 100nb and a third region 100p. Therefore, the step of forming the opening includes: removing the dummy gate structure 120, respectively in the dielectric layer 130 in the first region 100na, in the dielectric layer 130 in the second region 100nb and in the third region 100p. An opening 121 is formed in the dielectric layer 130 .
所述开口121底部分别露出第一区域100na鳍部110的部分顶部和部分侧壁的表面、第二区域100nb鳍部110的部分顶部和部分侧壁的表面以及第三区域100p鳍部110的部分顶部和部分侧壁表面。The bottom of the opening 121 exposes part of the top and part of the sidewall surface of the fin 110 in the first region 100na, part of the top and part of the sidewall surface of the fin 110 in the second region 100nb, and part of the fin 110 in the third region 100p. Top and some side wall surfaces.
结合参考图8和图9,其中图9中间100na区域的结构为图8中沿AA线的剖视结构示意图;图9中右侧100nb区域的结构为图8中沿BB线的剖视结构示意图;图9左侧100p区域的结构为图8中沿CC线的剖视结构示意图。Referring to Figure 8 and Figure 9, the structure of the 100na region in the middle of Figure 9 is a schematic cross-sectional structure diagram along the AA line in Figure 8; the structure of the 100nb region on the right side in Figure 9 is a schematic cross-sectional structure diagram along the BB line in Figure 8 ; The structure of the 100p region on the left side of FIG. 9 is a schematic cross-sectional structure diagram along CC line in FIG. 8 .
在所述开口121底部形成栅介质层(图中未标示),位于所述第一区域100na介质层130内开口121底部的栅介质层为第一栅介质层140na,位于所述第二区域100nb介质层130内开口121底部的栅介质层为第二栅介质层140nb。A gate dielectric layer (not shown in the figure) is formed at the bottom of the opening 121, the gate dielectric layer at the bottom of the opening 121 in the dielectric layer 130 in the first region 100na is the first gate dielectric layer 140na, and is located in the second region 100nb The gate dielectric layer at the bottom of the opening 121 in the dielectric layer 130 is the second gate dielectric layer 140nb.
本实施例中,所述基底还包括第三区域100p,所以位于第三区域100p介质层130内开口121底部的栅介质层为第三栅介质层140p。In this embodiment, the substrate further includes a third region 100p, so the gate dielectric layer at the bottom of the opening 121 in the dielectric layer 130 in the third region 100p is the third gate dielectric layer 140p.
所述栅介质层用于形成栅极结构,隔离后续所形成的栅电极与半导体结构的沟道区域。The gate dielectric layer is used to form a gate structure and isolate the subsequently formed gate electrode from the channel region of the semiconductor structure.
本实施例中,所述半导体结构具有“高K金属栅”结构,所以形成所述栅介质层的步骤包括:形成包括高K介质层的栅介质层。In this embodiment, the semiconductor structure has a "high-K metal gate" structure, so the step of forming the gate dielectric layer includes: forming a gate dielectric layer including a high-K dielectric layer.
所述高K介质层的材料为相对介电常数大于氧化硅相对介电常数的栅介质材料。本实施例中,所述高K介质层的材料为氧化铪。本发明其他实施例中,所述高K介质层的材料还可以选自氧化锆、氧化镧、氧化铝、氧化钛、钛酸锶、氧化铝镧、氧化钇、氮氧化铪、氮氧化锆、氮氧化镧、氮氧化铝、氮氧化钛、氮氧化锶钛、氮氧化镧铝、氮氧化钇中的一种或多种。The material of the high-K dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-K dielectric layer is hafnium oxide. In other embodiments of the present invention, the material of the high-K dielectric layer can also be selected from zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, strontium titanate, aluminum oxide lanthanum, yttrium oxide, hafnium oxynitride, zirconium oxynitride, One or more of lanthanum oxynitride, aluminum oxynitride, titanium oxynitride, strontium titanium oxynitride, lanthanum aluminum oxynitride, and yttrium oxynitride.
形成所述栅介质层的方法为化学气相沉积、物理气相沉积或原子层沉积等膜层沉积等膜层沉积方法。The method for forming the gate dielectric layer is a film deposition method such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.
需要说明的是,形成开口之后,形成所述栅介质层之前,所述形成方法还包括:在所述开口121底部形成界面层(Interface Layer,IL)(图中未标示),用于缓解所述基底与所述栅介质层之间的晶格失配问题。It should be noted that, after forming the opening and before forming the gate dielectric layer, the forming method further includes: forming an interface layer (Interface Layer, IL) (not shown in the figure) at the bottom of the opening 121 to alleviate the The problem of lattice mismatch between the substrate and the gate dielectric layer.
具体的,如图9所示,所述第一栅介质层140na位于所述第一区域100na鳍部110部分顶部和部分侧壁的表面上;所述第二栅介质层140nb位于所述第二区域100nb鳍部110部分顶部和部分侧壁的表面上;所述第三栅介质层140p位于所述第三区域100p鳍部110部分顶部和部分侧壁的表面上。Specifically, as shown in FIG. 9, the first gate dielectric layer 140na is located on the surface of part of the top and part of the sidewall of the fin 110 in the first region 100na; the second gate dielectric layer 140nb is located on the second The region 100nb is on part of the top and part of the sidewall surface of the fin 110; the third gate dielectric layer 140p is located on the part of the top and part of the sidewall surface of the fin 110 in the third region 100p.
参考图10至图12,在所述第二栅介质层140nb上形成牺牲层160。Referring to FIGS. 10 to 12 , a sacrificial layer 160 is formed on the second gate dielectric layer 140nb.
所述牺牲层160用于在后续工艺中保护所述第二栅介质层140nb,避免所述第二栅介质层140nb受到损伤。本实施例中,所述牺牲层160用于在后续形成所述第一掩膜过程中保护所述第二栅介质层140nb,避免所述第二栅介质层140nb受到刻蚀工艺的影响。The sacrificial layer 160 is used to protect the second gate dielectric layer 140nb in subsequent processes to prevent the second gate dielectric layer 140nb from being damaged. In this embodiment, the sacrificial layer 160 is used to protect the second gate dielectric layer 140nb during the subsequent formation of the first mask, so as to prevent the second gate dielectric layer 140nb from being affected by the etching process.
如果所述牺牲层160的厚度太小,则难以在后续工艺中起到保护所述第二栅介质层140nb的作用,难以降低所述第二栅介质层140nb受损的可能;如果所述牺牲层160的厚度太大,则容易引起材料浪费还会增加工艺难度。本实施例中,所述牺牲层160的厚度在到范围内。If the thickness of the sacrificial layer 160 is too small, it is difficult to protect the second gate dielectric layer 140nb in subsequent processes, and it is difficult to reduce the possibility of damage to the second gate dielectric layer 140nb; If the thickness of the layer 160 is too large, it will easily cause material waste and increase the difficulty of the process. In this embodiment, the thickness of the sacrificial layer 160 is arrive within range.
本实施例中,形成所述牺牲层160的步骤包括:如图10所示,在所述栅介质层上形成初始材料层160a;如图11所示,去除所述第一栅介质层140na上的初始材料层160a,露出所述第一栅介质层140na,位于所述第二栅介质层140nb上的初始材料层160a(如图10所示)作为所述牺牲层160。In this embodiment, the step of forming the sacrificial layer 160 includes: as shown in FIG. 10 , forming an initial material layer 160 a on the gate dielectric layer; as shown in FIG. 11 , removing the The initial material layer 160a is exposed to the first gate dielectric layer 140na, and the initial material layer 160a (as shown in FIG. 10 ) on the second gate dielectric layer 140nb serves as the sacrificial layer 160 .
具体的,参考图10,形成位于所述栅介质层上的初始材料层160a。Specifically, referring to FIG. 10 , an initial material layer 160 a is formed on the gate dielectric layer.
由于所述基底包括第一区域100na和第二区域100nb,所以所述初始材料层160a覆盖所述第一栅介质层140na和所述第二栅介质层140nb。Since the substrate includes a first region 100na and a second region 100nb, the initial material layer 160a covers the first gate dielectric layer 140na and the second gate dielectric layer 140nb.
需要说明的是,本实施例中,所述基底还包括第三区域100p,所以形成所述初始材料层160a的步骤中,所述初始材料层160a还位于所述第三栅介质层140p上。所述第三栅介质层140p上的初始材料层160还用于构成所述第三区域100p晶体管功函数层。这种做法的好处在于,无需增加半导体工艺以实现所述初始材料层160a的形成,有利于减少工艺步骤,降低工艺成本。It should be noted that, in this embodiment, the substrate further includes a third region 100p, so in the step of forming the initial material layer 160a, the initial material layer 160a is also located on the third gate dielectric layer 140p. The initial material layer 160 on the third gate dielectric layer 140p is also used to form a transistor work function layer in the third region 100p. The advantage of this method is that there is no need to increase the semiconductor process to realize the formation of the initial material layer 160a, which is beneficial to reduce process steps and process cost.
本实施例中,所述第三区域100p基底用于形成P型晶体管,所以所述初始材料层160a的材料为氮化钛。In this embodiment, the base of the third region 100p is used to form a P-type transistor, so the material of the initial material layer 160a is titanium nitride.
具体的,所述初始材料层160a可以通过化学气相沉积、物理气相沉积或者原子层沉积等膜层沉积方式形成于所述栅介质层上。Specifically, the initial material layer 160a may be formed on the gate dielectric layer by chemical vapor deposition, physical vapor deposition or atomic layer deposition or other film deposition methods.
需要说明的是,由于所述初始材料层160a用于形成所述牺牲层160还用于构成所述第三区域100p晶体管的功函数层,所以所述初始材料层160a的厚度不宜过大,也不宜过小。如果所述初始材料层160a的厚度太小,则所形成的所述牺牲层160的厚度太小,难以起到保护所述第二栅介质层140nb的作用,所述初始材料层160a的厚度太小也会影响后续所形成第三区域100p晶体管功函数层的厚度,难以实现对第三区域100p晶体管阈值电压的调节;如果所述初始材料层160a的厚度太大,则容易造成材料浪费,也会增加工艺难度。本实施例中,形成所述初始材料层160a的步骤中,所述初始材料层160a的厚度在到范围内。It should be noted that since the initial material layer 160a is used to form the sacrificial layer 160 and is also used to form the work function layer of the transistor in the third region 100p, the thickness of the initial material layer 160a should not be too large. Should not be too small. If the thickness of the initial material layer 160a is too small, the thickness of the formed sacrificial layer 160 is too small to protect the second gate dielectric layer 140nb, and the thickness of the initial material layer 160a is too large. A small thickness will also affect the thickness of the transistor work function layer in the third region 100p formed subsequently, making it difficult to adjust the threshold voltage of the transistor in the third region 100p; if the thickness of the initial material layer 160a is too large, it will easily cause material waste, and It will increase the difficulty of the process. In this embodiment, in the step of forming the initial material layer 160a, the thickness of the initial material layer 160a is arrive within range.
参考图10,去除所述第一栅介质层140na上的初始材料层160a,露出所述第一栅介质层140na,位于所述第二栅介质层140nb上的初始材料层160a作为所述牺牲层160。Referring to FIG. 10, the initial material layer 160a on the first gate dielectric layer 140na is removed to expose the first gate dielectric layer 140na, and the initial material layer 160a on the second gate dielectric layer 140nb serves as the sacrificial layer 160.
具体的,去除所述第一栅介质层140na上的初始材料层160a的步骤包括:在所述初始材料层160a上形成高压区掩膜160b,所述高压区掩膜160b露出所述第一栅介质层140na上的初始材料层160a;以所述高压区掩膜160b为掩膜,去除所述第一栅介质层140na上的初始材料层160a,露出所述第一栅介质层140na。Specifically, the step of removing the initial material layer 160a on the first gate dielectric layer 140na includes: forming a high voltage area mask 160b on the initial material layer 160a, and the high voltage area mask 160b exposes the first gate dielectric layer 160a. The initial material layer 160a on the dielectric layer 140na; using the high voltage area mask 160b as a mask, remove the initial material layer 160a on the first gate dielectric layer 140na to expose the first gate dielectric layer 140na.
所述高压区掩膜160b用于构成所述第二掩膜,以在半导体工艺中保护所述第二栅介质层140nb上的初始材料层160a。The high voltage region mask 160b is used to form the second mask to protect the initial material layer 160a on the second gate dielectric layer 140nb during the semiconductor process.
具体的,形成所述第二掩膜的步骤包括:Specifically, the step of forming the second mask includes:
在所述初始材料层160a上形成第二掩膜材料层;在所述第二掩膜材料层上形成第一图形层160c,所述第一图形层160c露出所述第一栅介质层140na上的第二掩膜材料层;以所述第一图形层160c为掩膜,去除所述第一栅介质层140na上的第二掩膜材料层,露出所述第一栅介质层140na上的初始材料层160a,形成所述高压区掩膜160b,以构成所述第二掩膜。A second mask material layer is formed on the initial material layer 160a; a first pattern layer 160c is formed on the second mask material layer, and the first pattern layer 160c is exposed on the first gate dielectric layer 140na The second mask material layer; using the first pattern layer 160c as a mask, remove the second mask material layer on the first gate dielectric layer 140na, exposing the initial pattern on the first gate dielectric layer 140na The material layer 160a forms the high voltage region mask 160b to constitute the second mask.
其中,所述第二掩膜材料层用于形成所述高压区掩膜160b,以构成所述第二掩膜。具体的,形成第二掩膜材料层的步骤中,所述第二掩膜材料层为底部抗反射层,可以通过涂布工艺形成。Wherein, the second mask material layer is used to form the high voltage area mask 160b to form the second mask. Specifically, in the step of forming the second mask material layer, the second mask material layer is a bottom anti-reflection layer, which can be formed through a coating process.
所述第一图形层160c用于对所述第二掩膜材料层进行图形化,从而形成第二掩膜。具体的,本实施例中,所述第一图形层160c为光刻胶层,可以通过涂布工艺和光刻工艺形成。本发明其他实施例中,所述第一图形层160c也可以是多重掩膜工艺所形成的掩膜。The first pattern layer 160c is used to pattern the second mask material layer to form a second mask. Specifically, in this embodiment, the first pattern layer 160c is a photoresist layer, which can be formed by a coating process and a photolithography process. In other embodiments of the present invention, the first pattern layer 160c may also be a mask formed by multiple masking processes.
去除所述第一栅介质层140na上的第二掩膜材料层的步骤用于露出所述第一栅介质层140na上的初始材料层160a,形成所述高压区掩膜160b,为后续工艺提供工艺表面。The step of removing the second mask material layer on the first gate dielectric layer 140na is used to expose the initial material layer 160a on the first gate dielectric layer 140na to form the high-voltage region mask 160b to provide for subsequent processes. craft surface.
具体的,去除所述第一栅介质层140na上的第二掩膜材料层的步骤包括:通过干法刻蚀的方式去除所述第一栅介质层140na上的第二掩膜材料层。由于所述第一栅介质层140na上形成有初始材料层160a,所述初始材料层160a能够有效保护所述第一栅介质层140na,避免所述第一栅介质层140na受到干法刻蚀工艺的损伤。Specifically, the step of removing the second mask material layer on the first gate dielectric layer 140na includes: removing the second mask material layer on the first gate dielectric layer 140na by dry etching. Since the initial material layer 160a is formed on the first gate dielectric layer 140na, the initial material layer 160a can effectively protect the first gate dielectric layer 140na and prevent the first gate dielectric layer 140na from being subjected to a dry etching process. damage.
需要说明的是,本实施例中,所述基底还包括第三区域100p,所述第三栅介质层140p上的初始材料层160a后续用于构成所述第三区域100p晶体管的功函数层。It should be noted that, in this embodiment, the substrate further includes a third region 100p, and the initial material layer 160a on the third gate dielectric layer 140p is subsequently used to form a work function layer of a transistor in the third region 100p.
所以形成第二掩膜的步骤中,所述第二掩膜还位于所述第三栅介质层140p上,也就是说,所述高压区掩膜160b还位于所述第三栅介质层140p上,用于保护所述第三栅介质层140p上的初始材料层160a。Therefore, in the step of forming the second mask, the second mask is also located on the third gate dielectric layer 140p, that is, the high voltage region mask 160b is also located on the third gate dielectric layer 140p , used to protect the initial material layer 160a on the third gate dielectric layer 140p.
继续参考图11,以所述第二掩膜为掩膜,去除所述第一栅介质层140na上的初始材料层160a,露出所述第一栅介质层140na。Continuing to refer to FIG. 11 , using the second mask as a mask, the initial material layer 160a on the first gate dielectric layer 140na is removed to expose the first gate dielectric layer 140na.
本实施例,以所述高压区掩膜160b为掩膜,通过湿法刻蚀的方式去除所述第一栅介质层140na上的初始材料层160a,露出所述第一栅介质层140na。In this embodiment, the initial material layer 160a on the first gate dielectric layer 140na is removed by wet etching by using the high voltage region mask 160b as a mask to expose the first gate dielectric layer 140na.
采用湿法刻蚀工艺去除所述初始材料层160a的做法,能够有效减小去除所述初始材料层160a工艺对所述第一栅介质层140na的影响,减少所述第一栅介质层140na受到损伤的可能。The method of removing the initial material layer 160a by using a wet etching process can effectively reduce the influence of the process of removing the initial material layer 160a on the first gate dielectric layer 140na, and reduce the impact on the first gate dielectric layer 140na. possibility of injury.
由于所述初始材料层160a的材料为氮化钛,所以通过湿法刻蚀的方式去除所述初始材料层160a的步骤中,刻蚀溶液为NH4OH、H2O2和水的混合溶液(SC1溶液)或者NH4、H2O2和水的混合溶液或者HCl、H2O2和水的混合溶液(SC2溶液)。Since the material of the initial material layer 160a is titanium nitride, in the step of removing the initial material layer 160a by wet etching, the etching solution is a mixed solution of NH 4 OH, H 2 O 2 and water (SC1 solution) or a mixed solution of NH 4 , H 2 O 2 and water or a mixed solution of HCl, H 2 O 2 and water (SC2 solution).
具体的,本实施例中,去除所述初始材料层160a的步骤中,刻蚀溶液为HCl、H2O2和水的混合溶液,其中,HCl、H2O2和水的质量百分比比值在1:3:200到3:3:200范围内,刻蚀温度在20℃到80℃范围内。Specifically, in this embodiment, in the step of removing the initial material layer 160a, the etching solution is a mixed solution of HCl, H 2 O 2 and water, wherein the mass percentage ratio of HCl, H 2 O 2 and water is between In the range of 1:3:200 to 3:3:200, the etching temperature is in the range of 20°C to 80°C.
本发明其他实施例中,去除所述初始材料层的步骤还可以采用NH4OH、H2O2和水的混合溶液或者NH4、H2O2和水的混合溶液。其中,NH4OH、H2O2和水的混合溶液为SC1溶液,刻蚀温度在20℃到80℃范围内;NH4、H2O2和水的混合溶液中NH4、H2O2和水的质量百分比比值在1:200:1000到5:200:1000范围内。In other embodiments of the present invention, the step of removing the initial material layer may also use a mixed solution of NH 4 OH, H 2 O 2 and water or a mixed solution of NH 4 , H 2 O 2 and water. Among them, the mixed solution of NH 4 OH, H 2 O 2 and water is SC1 solution, and the etching temperature is in the range of 20°C to 80°C; in the mixed solution of NH 4 , H 2 O 2 and water, NH 4 , H 2 O The mass percentage ratio of 2 and water is in the range of 1:200:1000 to 5:200:1000.
需要说明的是,由于所述第三栅介质层140p也具有第二掩膜,所以所述第三栅介质层140p上的初始材料层160a被保留,未受到刻蚀工艺的影响。It should be noted that since the third gate dielectric layer 140p also has a second mask, the initial material layer 160a on the third gate dielectric layer 140p is retained and is not affected by the etching process.
参考图12,去除所述第一栅介质层140na上初始材料层160a之后,去除所述第二掩膜,露出所述第二栅介质层140nb上的初始材料层160a,形成牺牲层160。Referring to FIG. 12 , after the initial material layer 160a on the first gate dielectric layer 140na is removed, the second mask is removed to expose the initial material layer 160a on the second gate dielectric layer 140nb to form a sacrificial layer 160 .
去除所述第二掩膜的步骤用于露出所述第二栅介质层140na上的初始材料层160a,以形成牺牲层160,从而为后续工艺提供操作表面。The step of removing the second mask is used to expose the initial material layer 160a on the second gate dielectric layer 140na to form a sacrificial layer 160 to provide an operating surface for subsequent processes.
本实施例中,所述第二掩膜通过底部抗反射层形成,所以去除所述第二掩膜的步骤中,通过灰化的方式去除所述第二掩膜。具体的,通过灰化的方式去除所述高压区掩膜160b,以露出所述牺牲层160。In this embodiment, the second mask is formed by the bottom anti-reflection layer, so in the step of removing the second mask, the second mask is removed by ashing. Specifically, the high voltage region mask 160b is removed by ashing to expose the sacrificial layer 160 .
采用灰化的方式去除所述第二掩膜的做法,能够避免去除工艺对露出的所述第一栅介质层140na的影响,减少第一栅介质层140na受损的可能。The method of removing the second mask by ashing can avoid the influence of the removal process on the exposed first gate dielectric layer 140na, and reduce the possibility of damage to the first gate dielectric layer 140na.
需要说明的是,所述高压区掩膜160还位于第三栅介质层140p上,所以通过灰化方式去除所述高压区掩膜160的步骤也露出了所述第三栅介质层140p上的初始材料层160a。It should be noted that the high-voltage region mask 160 is also located on the third gate dielectric layer 140p, so the step of removing the high-voltage region mask 160 by ashing also exposes the The initial material layer 160a.
继续参考图12,在所述第一栅介质层140na和所述牺牲层160上形成第一材料层161。Continuing to refer to FIG. 12 , a first material layer 161 is formed on the first gate dielectric layer 140na and the sacrificial layer 160 .
所述第一材料层161用于在后续半导体工艺中保护所述第二栅介质层140nb。本实施例中,所述第二栅介质层140nb上的第一材料层161与所述牺牲层160一起,在后续形成第一掩膜的过程中,减少刻蚀工艺对所述第二栅介质层140nb的影响,降低所述第二栅介质层140nb受损的可能。The first material layer 161 is used to protect the second gate dielectric layer 140nb in subsequent semiconductor processes. In this embodiment, the first material layer 161 on the second gate dielectric layer 140nb, together with the sacrificial layer 160, reduces the impact of the etching process on the second gate dielectric during the subsequent formation of the first mask. layer 140nb, reducing the possibility of damage to the second gate dielectric layer 140nb.
此外,所述第一栅介质层140na上的所述第一材料层161还用于构成所述第一区域100na基底所形成晶体管的功函数层。这种做法的好处在于,无需增加工艺步骤,即可实现对所述第二栅介质层140nb保护能力的提升以及所述第一区域100na基底所形成晶体管功函数层的形成,有利于简化工艺步骤,降低工艺成本。In addition, the first material layer 161 on the first gate dielectric layer 140na is also used to form the work function layer of the transistor formed on the base of the first region 100na. The advantage of this approach is that without adding process steps, the protection ability of the second gate dielectric layer 140nb can be improved and the formation of the transistor work function layer formed on the base of the first region 100na is beneficial to simplify the process steps , reduce process cost.
本实施例中,所述第一区域100na基底用于形成N型晶体管,所以所述第一材料层161的材料为氮化钛,可以通过化学气相沉积、物理气相沉积或者原子层沉积等方式形成。In this embodiment, the substrate of the first region 100na is used to form an N-type transistor, so the material of the first material layer 161 is titanium nitride, which can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. .
需要说明的是,所述第一材料层161的厚度如果太小,则无法在后续工艺中起到保护所述第二栅介质层140nb的作用,而且也会影响所形成第一区域100nb基底所形成晶体管功函数层的形成;所述第一材料层161的厚度如果太大,则容易造成材料浪费,增加工艺难度。本实施例中,所述第一材料层161的厚度在到范围内。It should be noted that if the thickness of the first material layer 161 is too small, it will not be able to protect the second gate dielectric layer 140nb in the subsequent process, and it will also affect the formed first region 100nb substrate. The formation of the transistor work function layer; if the thickness of the first material layer 161 is too large, it will easily cause material waste and increase the difficulty of the process. In this embodiment, the thickness of the first material layer 161 is arrive within range.
还需要说明的是,形成所述第一材料层161的过程中,所述第三栅介质层140p上的初始材料层160a也被露出,所以形成所述第一材料层161的步骤中,所述第一材料层161还位于所述第三栅介质层140p上。It should also be noted that during the process of forming the first material layer 161, the initial material layer 160a on the third gate dielectric layer 140p is also exposed, so in the step of forming the first material layer 161, the The first material layer 161 is also located on the third gate dielectric layer 140p.
参考图13和图14,形成位于所述第一材料层161上的第一掩膜170,所述第一掩膜170露出所述第二栅介质层140nb上的第一材料层161。Referring to FIG. 13 and FIG. 14 , a first mask 170 is formed on the first material layer 161 , and the first mask 170 exposes the first material layer 161 on the second gate dielectric layer 140nb.
所述第一掩膜170用于在半导体工艺中保护所述第一区域100na,避免所述第一栅介质层140na上的第一材料层161受影响。本实施例中,所述第一掩膜170用于在后续去除所述牺牲层160和第二栅介质层140nb上第一材料层161过程中,保护所述第一栅介质层140na上所述第一材料层161。The first mask 170 is used to protect the first region 100na during the semiconductor process, preventing the first material layer 161 on the first gate dielectric layer 140na from being affected. In this embodiment, the first mask 170 is used to protect the sacrificial layer 160 and the first material layer 161 on the second gate dielectric layer 140nb to protect the The first material layer 161 .
具体的,形成所述第一掩膜170的步骤包括:Specifically, the step of forming the first mask 170 includes:
如图13所述,在所述第一材料层161上形成第一掩膜材料层170a。As shown in FIG. 13 , a first mask material layer 170 a is formed on the first material layer 161 .
所述第一掩膜材料层170a用于形成所述第一掩膜。The first mask material layer 170a is used to form the first mask.
本实施例中,所述基底包括第一区域100na、第二区域100nb以及第三区域100p,所以所述第一掩膜材料层170p位于所述第一栅介质层140na、第二栅介质层140nb以及第三栅介质层140p上。In this embodiment, the substrate includes a first region 100na, a second region 100nb, and a third region 100p, so the first mask material layer 170p is located on the first gate dielectric layer 140na, the second gate dielectric layer 140nb and on the third gate dielectric layer 140p.
具体的,形成所述第一掩膜材料层170a的步骤中,所述第一掩膜材料层170为底部抗反射层,可以通过涂布工艺形成。Specifically, in the step of forming the first mask material layer 170a, the first mask material layer 170 is a bottom anti-reflection layer, which can be formed through a coating process.
形成所述第一掩膜材料层170a之后,在所述第一掩膜材料层170a上形成第二图形层170b,所述第二图形层170b露出所述第二栅介质层140nb上的第一掩膜材料层170a。After forming the first mask material layer 170a, a second pattern layer 170b is formed on the first mask material layer 170a, and the second pattern layer 170b exposes the first gate dielectric layer 140nb. Mask material layer 170a.
所述第二图形层170b用于对所述第一掩膜材料层170a进行图形化。所述第二图形层170b露出所述第二栅介质层140nb上的第一掩膜材料层170a,用于为后续露出所述第二栅介质层140nb上第一材料层161的工艺提供操作表面。The second pattern layer 170b is used to pattern the first mask material layer 170a. The second pattern layer 170b exposes the first mask material layer 170a on the second gate dielectric layer 140nb to provide an operating surface for the subsequent process of exposing the first material layer 161 on the second gate dielectric layer 140nb .
本实施例中,所述第二图形层170b为光刻胶层,可以通过涂布工艺和光刻工艺形成。本发明其他实施例中,所述第二图形层170b也可以是多重掩膜工艺所形成的掩膜。In this embodiment, the second pattern layer 170b is a photoresist layer, which can be formed by a coating process and a photolithography process. In other embodiments of the present invention, the second pattern layer 170b may also be a mask formed by multiple masking processes.
需要说明的是,所述第二图形层170b还位于所述第三栅介质层140p上的第一掩膜材料层170a上。It should be noted that, the second pattern layer 170b is also located on the first mask material layer 170a on the third gate dielectric layer 140p.
参考图14,以所述第二图形层170b为掩膜,去除所述第二栅介质层140nb上的第一掩膜材料层170a(如图13所示),露出所述第二栅介质层140nb上的第一材料层161,剩余的所述第一掩膜材料层170a形成所述第一掩膜170。Referring to FIG. 14, using the second pattern layer 170b as a mask, remove the first mask material layer 170a (as shown in FIG. 13 ) on the second gate dielectric layer 140nb, exposing the second gate dielectric layer The first material layer 161 on 140nb and the remaining first mask material layer 170a form the first mask 170 .
去除所述第二栅介质层140nb上的第一掩膜材料层170a的步骤用于为后续去除所述牺牲层161和所述第二栅介质层140nb上的第一材料层161提供工艺表面。The step of removing the first mask material layer 170a on the second gate dielectric layer 140nb is used to provide a process surface for subsequent removal of the sacrificial layer 161 and the first material layer 161 on the second gate dielectric layer 140nb.
本实施例中,所述第一掩膜材料层170a为底部抗反射层,所以去除所述第二栅介质层140nb上的第一掩膜材料层170a的步骤包括:以所述第二图形层170b为掩膜,通过干法刻蚀的方式去除所述第二栅介质层140nb上的第一掩膜材料层170a,露出所述第二栅介质层140nb上的第一材料层161。In this embodiment, the first mask material layer 170a is a bottom anti-reflection layer, so the step of removing the first mask material layer 170a on the second gate dielectric layer 140nb includes: using the second pattern layer 170b is a mask, and the first mask material layer 170a on the second gate dielectric layer 140nb is removed by dry etching to expose the first material layer 161 on the second gate dielectric layer 140nb.
由于所述第二栅介质层140nb上具有牺牲层160和第一材料层161,而且与仅具有第一材料层161的现有技术相比,所述牺牲层160和所述第一材料层161的厚度较大,保护能力较强,能够有效的降低所述第二栅介质层140nb受损的可能,减少所述第二栅介质层140nb受损现象的出现,有利于提高所述第二栅介质层140nb的质量,提高所形成半导体结构的性能。Since the second gate dielectric layer 140nb has the sacrificial layer 160 and the first material layer 161, and compared with the prior art with only the first material layer 161, the sacrificial layer 160 and the first material layer 161 thicker, stronger protection capability, can effectively reduce the possibility of damage to the second gate dielectric layer 140nb, reduce the occurrence of damage to the second gate dielectric layer 140nb, and help improve the second gate dielectric layer 140nb The quality of the dielectric layer 140nb improves the performance of the formed semiconductor structure.
具体的,通过干法刻蚀的方式去除所述第二栅介质层140nb上的第一掩膜材料层170a的步骤中,工艺参数包括:刻蚀气体为CH4、H2以及N2;刻蚀气体流量为CH4的流量在5sccm到50sccm范围内,H2的流量在100sccm到800sccm范围内,N2的流量在20sccm到200sccm范围内;压强为1mTorr到150mTorr;功率为100W到200W;偏压在10V到300V范围内;工艺温度在20℃到90℃范围内;时间在30s到1000s范围内。Specifically, in the step of removing the first mask material layer 170a on the second gate dielectric layer 140nb by dry etching, the process parameters include: the etching gas is CH 4 , H 2 and N 2 ; The flow rate of the etching gas is in the range of 5sccm to 50sccm for CH4 , the flow rate of H2 is in the range of 100sccm to 800sccm, the flow rate of N2 is in the range of 20sccm to 200sccm; the pressure is 1mTorr to 150mTorr; the power is 100W to 200W; The voltage is in the range of 10V to 300V; the process temperature is in the range of 20°C to 90°C; the time is in the range of 30s to 1000s.
需要说明的是,由于所述第二图形层170b还位于所述第三栅介质层140p上的第一掩膜材料层170a上,所以形成第一掩膜170的步骤中,所述第一掩膜170还位于所述第三栅介质层140p上,以保护所述第三栅介质层140p上的第一材料层161和初始材料层160a。It should be noted that, since the second pattern layer 170b is also located on the first mask material layer 170a on the third gate dielectric layer 140p, in the step of forming the first mask 170, the first mask The film 170 is also located on the third gate dielectric layer 140p to protect the first material layer 161 and the initial material layer 160a on the third gate dielectric layer 140p.
参考图15,以所述第一掩膜170为掩膜,去除所述第二栅介质层140nb上的第一材料层161(如图14所示)和牺牲层160(如图14所示),露出所述第二栅介质层140nb。Referring to FIG. 15, using the first mask 170 as a mask, remove the first material layer 161 (as shown in FIG. 14 ) and the sacrificial layer 160 (as shown in FIG. 14 ) on the second gate dielectric layer 140nb , exposing the second gate dielectric layer 140nb.
去除所述第二栅介质层140nb上的第一材料层161和所述牺牲层160的步骤用于为后续工艺提供工艺表面。The step of removing the first material layer 161 and the sacrificial layer 160 on the second gate dielectric layer 140nb is used to provide a process surface for subsequent processes.
具体的,去除所述第二栅介质层140nb上的第一材料层161和牺牲层160的步骤包括:通过湿法刻蚀的方式去除所述第二栅介质层140nb上的第一材料层161和牺牲层160。Specifically, the step of removing the first material layer 161 and the sacrificial layer 160 on the second gate dielectric layer 140nb includes: removing the first material layer 161 on the second gate dielectric layer 140nb by wet etching and a sacrificial layer 160 .
采用湿法刻蚀的方式去除所述第二栅介质层140nb上的第一材料层161和牺牲层160的做法,能够有效减小去除工艺对第二栅介质层140nb的影响,降低第二栅介质层140nb受损的可能。The method of removing the first material layer 161 and the sacrificial layer 160 on the second gate dielectric layer 140nb by wet etching can effectively reduce the influence of the removal process on the second gate dielectric layer 140nb, and reduce the second gate dielectric layer 140nb. The possibility of damage to the dielectric layer 140nb.
本实施例中,由于所述第一材料层161和所述牺牲层160的材料为氮化钛,所以通过湿法刻蚀的方式去除所述第二栅介质层140nb上的第一材料层161和牺牲层160的步骤中,刻蚀溶液为NH4OH、H2O2和水的混合溶液(SC1溶液)或者NH4、H2O2和水的混合溶液或者HCl、H2O2和水的混合溶液(SC2溶液)。In this embodiment, since the material of the first material layer 161 and the sacrificial layer 160 is titanium nitride, the first material layer 161 on the second gate dielectric layer 140nb is removed by wet etching and sacrificial layer 160, the etching solution is a mixed solution of NH 4 OH, H 2 O 2 and water (SC1 solution) or a mixed solution of NH 4 , H 2 O 2 and water or HCl, H 2 O 2 and Mixed solution of water (SC2 solution).
具体的,本实施例中,去除所述第一材料层161和所述牺牲层160的步骤中,刻蚀溶液为HCl、H2O2和水的混合溶液,其中,HCl、H2O2和水的质量百分比比值在1:3:200到3:3:200范围内,刻蚀温度在20℃到80℃范围内。Specifically, in this embodiment, in the step of removing the first material layer 161 and the sacrificial layer 160, the etching solution is a mixed solution of HCl, H 2 O 2 and water, wherein HCl, H 2 O 2 The mass percentage ratio of water and water is in the range of 1:3:200 to 3:3:200, and the etching temperature is in the range of 20°C to 80°C.
本发明其他实施例中,去除所述第一材料层和所述牺牲层160的步骤还可以采用NH4OH、H2O2和水的混合溶液或者NH4、H2O2和水的混合溶液。其中,NH4OH、H2O2和水的混合溶液为SC1溶液,刻蚀温度在20℃到80℃范围内;NH4、H2O2和水的混合溶液中NH4、H2O2和水的质量百分比比值在1:200:1000到5:200:1000范围内。In other embodiments of the present invention, the step of removing the first material layer and the sacrificial layer 160 may also use a mixed solution of NH 4 OH, H 2 O 2 and water or a mixed solution of NH 4 , H 2 O 2 and water solution. Among them, the mixed solution of NH 4 OH, H 2 O 2 and water is SC1 solution, and the etching temperature is in the range of 20°C to 80°C; in the mixed solution of NH 4 , H 2 O 2 and water, NH 4 , H 2 O The mass percentage ratio of 2 and water is in the range of 1:200:1000 to 5:200:1000.
需要说明的是,由于所述第一掩膜170还位于所述第三栅介质层140p上,所以所述第三栅介质层140p上的初始材料层160a和所述第一材料层161被保留,未收到刻蚀工艺的影响。It should be noted that since the first mask 170 is also located on the third gate dielectric layer 140p, the initial material layer 160a and the first material layer 161 on the third gate dielectric layer 140p are retained , not affected by the etching process.
参考图16,露出所述第二栅介质层140nb之后,去除所述第一掩膜170(如图15所示),露出所述第一栅介质层140na上的所述第一材料层161。Referring to FIG. 16 , after exposing the second gate dielectric layer 140nb, the first mask 170 (as shown in FIG. 15 ) is removed to expose the first material layer 161 on the first gate dielectric layer 140na.
去除所述第一掩膜170的步骤用于为后续形成第二材料层提供工艺表面。The step of removing the first mask 170 is used to provide a process surface for the subsequent formation of the second material layer.
本实施例中,所述第一掩膜170由底部抗反射层形成,所以去除所述第一掩膜170的步骤包括:通过灰化的方式去除所述第一掩膜170。采用灰化的方式去除所述第一掩膜170的做法,能够避免去除工艺对露出的所述第二栅介质层140nb的影响,减少第二栅介质层140nb受损的可能。In this embodiment, the first mask 170 is formed by a bottom anti-reflection layer, so the step of removing the first mask 170 includes: removing the first mask 170 by ashing. The method of removing the first mask 170 by ashing can avoid the influence of the removal process on the exposed second gate dielectric layer 140nb, and reduce the possibility of damage to the second gate dielectric layer 140nb.
需要说明的是,由于所述第一掩膜170还位于所述第三栅介质层140p上,所以通过灰化的方式去除所述第一掩膜170的步骤也露出了所述第三栅介质层140p上的第一材料层161。It should be noted that since the first mask 170 is still located on the third gate dielectric layer 140p, the step of removing the first mask 170 by ashing also exposes the third gate dielectric layer 140p. A first material layer 161 on layer 140p.
继续参考图16,在所述第一栅介质层140na的第一材料层161和所述第二栅介质层140nb上形成第二材料层171。Continuing to refer to FIG. 16 , a second material layer 171 is formed on the first material layer 161 of the first gate dielectric layer 140na and the second gate dielectric layer 140nb.
所述第二材料层171用于构成所述第二区域100nb所形成晶体管的功函数层,还用于构成所述第一区域100na所形成晶体管的功函数层。The second material layer 171 is used to form the work function layer of the transistor formed in the second region 100nb, and is also used to form the work function layer of the transistor formed in the first region 100na.
所以由于所述第一区域100na基底和所述第二区域基底100nb基底用于形成N型晶体管,所以所述第二材料层的材料为氮化钛,可以通过化学气相沉积、物理气相沉积或者原子层沉积等膜层沉积工艺形成。Therefore, since the substrate in the first region 100na and the substrate in the second region 100nb are used to form an N-type transistor, the material of the second material layer is titanium nitride, which can be deposited by chemical vapor deposition, physical vapor deposition or atomic Layer deposition and other film deposition processes are formed.
需要说明的是,由于去除所述第一掩膜170的步骤也露出了所述第三栅介质层140p上的第一材料层161,所以形成所述第二材料层171的步骤中,所述第二材料层171还位于所述第三栅介质层上140p上,以构成所述第三区域100p基底所形成晶体管功函数层。It should be noted that, since the step of removing the first mask 170 also exposes the first material layer 161 on the third gate dielectric layer 140p, in the step of forming the second material layer 171, the The second material layer 171 is also located on the third gate dielectric layer 140p to form a transistor work function layer formed on the base of the third region 100p.
本实施例中,根据所述第二区域100nb基底所形成晶体管的阈值电压,所述第二材料层171的厚度在到范围内。In this embodiment, according to the threshold voltage of the transistor formed on the base of the second region 100nb, the thickness of the second material layer 171 is arrive within range.
需要说明的是,所述第二区域100nb基底所形成晶体管的功函数层包括所述第二介质层140nb上的第二材料层171;所述第一区域100na基底所形成晶体管的功函数层包括第一栅介质层140na上的第一材料层161以及第二材料层171;所述第三区域100p基底所形成晶体管的功函数层包括第三栅介质层140p上的初始材料层160a、所述第一材料层161以及所述第二材料层171。It should be noted that the work function layer of the transistor formed on the base of the second region 100nb includes the second material layer 171 on the second dielectric layer 140nb; the work function layer of the transistor formed on the base of the first region 100nb includes The first material layer 161 and the second material layer 171 on the first gate dielectric layer 140na; the work function layer of the transistor formed on the base of the third region 100p includes the initial material layer 160a on the third gate dielectric layer 140p, the The first material layer 161 and the second material layer 171 .
所以所述第二材料层171的厚度根据所述第二区域100nb基底所形成晶体管的阈值电压而确定;所述第一材料层161的厚度根据所述第一区域100na基底所形成晶体管的阈值电压以及所述第二材料层171的厚度确定;所述初始材料层160a的厚度根据所述第三区域100p基底所形成晶体管的阈值电压以及所述第一材料层161的厚度、所述第二材料层171的厚度确定。Therefore, the thickness of the second material layer 171 is determined according to the threshold voltage of the transistor formed on the substrate of the second region 100nb; the thickness of the first material layer 161 is determined according to the threshold voltage of the transistor formed on the substrate of the first region 100na And the thickness of the second material layer 171 is determined; the thickness of the initial material layer 160a is based on the threshold voltage of the transistor formed on the substrate of the third region 100p, the thickness of the first material layer 161, the thickness of the second material layer The thickness of layer 171 is determined.
本实施例中,所述第一区域100na的基底和所述第二区域100nb的基底用于形成N型晶体管,在形成第二材料层171后,所述形成方法还包括:在所述第二材料层171上形成钛铝层,以形成第一区域100na基底所形成晶体管的功函数层以及所述第二区域100nb基底所形成晶体管的功函数层。In this embodiment, the substrate of the first region 100na and the substrate of the second region 100nb are used to form an N-type transistor, and after forming the second material layer 171, the forming method further includes: A titanium aluminum layer is formed on the material layer 171 to form the work function layer of the transistor formed on the base of the first region 100na and the work function layer of the transistor formed on the base of the second region 100nb.
所述钛铝层的形成方法与现有技术相同,本发明在此不再赘述。The method for forming the titanium-aluminum layer is the same as that of the prior art, and will not be repeated in the present invention.
综上,本发明技术方案,在形成栅介质层后,在第二栅介质层上形成牺牲层,在牺牲层上形成第一材料层;在形成第一掩膜的过程中,以所述牺牲层和所述第一材料层保护所述第二栅介质层。与仅靠所述第一材料层保护所述第二栅介质层的现有技术相比,本发明技术方案中,所述第一材料层和所述牺牲层的总厚度较大,对所述第二栅介质层的保护能力更强,能够有效的减少第二栅介质层在第一掩膜形成过程中受损,有利于提高栅介质层的性能,改善所形成半导体结构的性能。To sum up, in the technical solution of the present invention, after forming the gate dielectric layer, a sacrificial layer is formed on the second gate dielectric layer, and a first material layer is formed on the sacrificial layer; layer and the first material layer protect the second gate dielectric layer. Compared with the prior art that only relies on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including:Substrate is formed, the substrate includes being used for first area and the second area for forming transistor, and the first area is brilliant The threshold voltage of body pipe is more than the threshold voltage of second area transistor;Pseudo- grid structure is formed on the substrate;Dielectric layer is formed in the adjacent pseudo- interstructural substrate of grid;Remove dummy gate structure and opening is formed in the dielectric layer;Gate dielectric layer is formed in the open bottom, the gate dielectric layer positioned at the first area dielectric layer inner opening bottom is the One gate dielectric layer, the gate dielectric layer positioned at the second area dielectric layer inner opening bottom are the second gate dielectric layer;Sacrifice layer is formed on second gate dielectric layer;First material layer is formed on first gate dielectric layer and sacrifice layer;Form the first mask in the first material layer, first mask exposes the on second gate dielectric layer One material layer;Using first mask as mask, first material layer and sacrifice layer on second gate dielectric layer are removed, is exposed described Second gate dielectric layer;First mask is removed, exposes the first material layer on first gate dielectric layer;Second material layer is formed in the first material layer of first gate dielectric layer and second gate dielectric layer.
- 2. forming method as claimed in claim 1, it is characterised in that in the step of forming sacrifice layer, the thickness of the sacrifice layer Degree existsArriveIn the range of.
- 3. forming method as claimed in claim 1, it is characterised in that the step of forming the sacrifice layer includes:Original material layer is formed on the gate dielectric layer;The original material layer on first gate dielectric layer is removed, exposes first gate dielectric layer, is situated between positioned at the second gate Original material layer on matter layer is as the sacrifice layer.
- 4. forming method as claimed in claim 3, it is characterised in that remove the original material layer on first gate dielectric layer The step of include:The second mask is formed on the original material layer, second mask exposes the initial material on first gate dielectric layer The bed of material;Using second mask as mask, the original material layer on first gate dielectric layer is removed, exposes the first grid and is situated between Matter layer;Second mask is removed, exposes the original material layer on second gate dielectric layer, forms sacrifice layer.
- 5. forming method as claimed in claim 4, it is characterised in that the step of forming second mask includes:The second mask layer is formed on the original material layer;The first graph layer is formed on second mask layer, first graph layer exposes on first gate dielectric layer The second mask layer;Using first graph layer as mask, the second mask layer on first gate dielectric layer is removed, exposes described the Original material layer on one gate dielectric layer, form second mask.
- 6. forming method as claimed in claim 5, it is characterised in that in the step of forming the second mask layer, described the Two mask layers are bottom anti-reflection layer.
- 7. forming method as claimed in claim 5, it is characterised in that remove the second mask material on first gate dielectric layer The step of bed of material, includes:The second mask layer on first gate dielectric layer is removed by way of dry etching.
- 8. the forming method as described in claim 3 or 4, it is characterised in that remove the initial material on first gate dielectric layer The step of bed of material, includes:The original material layer on first gate dielectric layer is removed by way of wet etching.
- 9. forming method as claimed in claim 4, it is characterised in that in the step of removing second mask, pass through ashing Mode remove second mask.
- 10. forming method as claimed in claim 3, it is characterised in that in the step of forming substrate, the substrate also includes the Three regions;In the step of forming gate dielectric layer, the gate dielectric layer positioned at the 3rd Region Medium layer inner opening bottom is situated between for the 3rd grid Matter layer;In the step of forming original material layer, the original material layer is also located on the 3rd gate dielectric layer;In the step of forming the second mask, second mask is also located on the 3rd gate dielectric layer;In the step of forming the first material layer, the first material layer is also located on the 3rd gate dielectric layer;In the step of forming the first mask, first mask is also located on the 3rd gate dielectric layer;In the step of forming the second material layer, the second material layer is also located on the 3rd gate dielectric layer.
- 11. forming method as claimed in claim 10, it is characterised in that in the step of forming substrate, the 3rd region base Bottom is used to form P-type transistor;In the step of forming the original material layer, the original material layer is titanium nitride.
- 12. forming method as claimed in claim 1, it is characterised in that the step of forming first mask includes:The first mask layer is formed in the first material layer;Second graph layer is formed on first mask layer, the second graph layer exposes on second gate dielectric layer The first mask layer;Using the second graph layer as mask, the first mask layer on second gate dielectric layer is removed, exposes described the First material layer on two gate dielectric layers, form first mask.
- 13. forming method as claimed in claim 12, it is characterised in that in the step of forming first mask layer, First mask layer is bottom anti-reflection layer.
- 14. forming method as claimed in claim 12, it is characterised in that remove the first mask on second gate dielectric layer The step of material layer, includes:The first mask layer on second gate dielectric layer is removed by way of dry etching.
- 15. forming method as claimed in claim 1, it is characterised in that remove the first material on second gate dielectric layer The step of layer and sacrifice layer, includes:First material layer on second gate dielectric layer and sacrificial is removed by way of wet etching Domestic animal layer.
- 16. forming method as claimed in claim 1, it is characterised in that the step of removing first mask includes:Pass through ash The mode of change removes first mask.
- 17. forming method as claimed in claim 1, it is characterised in that in the step of forming substrate, the first area and institute Second area is stated to be used to form N-type transistor;The material of the first material layer and the second material layer is titanium nitride.
- 18. forming method as claimed in claim 1, it is characterised in that in the step of forming the first material layer, described The thickness of one material layer existsArriveIn the range of.
- 19. forming method as claimed in claim 1, it is characterised in that the step of forming gate dielectric layer includes:Formation includes height The gate dielectric layer of K dielectric layer.
- 20. forming method as claimed in claim 1, it is characterised in that the semiconductor structure is fin formula field effect transistor;The step of forming substrate includes:Initial substrate is provided;The initial substrate is etched, forms substrate and discrete fin on the substrate;The step of forming dummy gate structure includes:Form the pseudo- grid structure on the fin, dummy gate structure across Part surface at the top of the fin and the covering fin with side wall.
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