CN107799409A - The forming method of semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: forming a base, including a first region and a second region; forming a dummy gate structure; forming an opening; forming a first gate dielectric layer and a second gate dielectric layer; forming a sacrificial layer; material layer; forming a first mask; exposing the second gate dielectric layer; exposing the first material layer; forming a second material layer. Compared with the prior art that only relies on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.

Description

Formation method of semiconductor structure

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the improvement of component density and integration of semiconductor devices, the feature size of transistors is getting smaller and smaller. In order to reduce the parasitic capacitance of transistor gates and improve device speed, high The gate structure of the K gate dielectric layer and the metal gate is introduced into the transistor.

However, there are still many problems to be solved when forming a metal gate on a high-K gate dielectric layer, one of which is the matching of the work function, because the work function will directly affect the threshold voltage (Vt) of the device and the performance of the transistor. Therefore, a work function layer is introduced into the high-K metal gate structure to realize the adjustment of the threshold voltage of the device.

However, even if a work function layer is introduced into the high-K metal gate structure, the performance of the semiconductor structure in the prior art still needs to be improved.

Contents of the invention

The problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

forming a substrate, the substrate includes a first region and a second region for forming a transistor, and the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region; forming a dummy gate structure on the substrate; Forming a dielectric layer on the substrate between adjacent dummy gate structures; removing the dummy gate structure to form an opening in the dielectric layer; forming a gate dielectric layer at the bottom of the opening, located at the bottom of the opening in the dielectric layer in the first region The gate dielectric layer is a first gate dielectric layer, and the gate dielectric layer at the bottom of the opening in the second region dielectric layer is a second gate dielectric layer; a sacrificial layer is formed on the second gate dielectric layer; forming a first material layer on the gate dielectric layer and the sacrificial layer; forming a first mask on the first material layer, the first mask exposing the first material layer on the second gate dielectric layer; The first mask is a mask, and the first material layer and the sacrificial layer on the second gate dielectric layer are removed to expose the second gate dielectric layer; the first mask is removed to expose the first The first material layer on the gate dielectric layer; forming a second material layer on the first material layer of the first gate dielectric layer and the second gate dielectric layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, after forming the gate dielectric layer, a sacrificial layer is formed on the second gate dielectric layer, and a first material layer is formed on the sacrificial layer; in the process of forming the first mask, the sacrificial layer and the The first material layer protects the second gate dielectric layer. Compared with the technical solution of only relying on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the second The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.

Description of drawings

1 to 5 are schematic cross-sectional structure diagrams corresponding to each step of a method for forming a semiconductor structure.

6 to 16 are schematic cross-sectional structure diagrams corresponding to each step of an embodiment of the semiconductor structure forming method of the present invention.

Detailed ways

It can be seen from the background art that the semiconductor structure introducing the work function layer in the prior art has the problem of poor performance. Now combine the formation method of a semiconductor structure to analyze the reasons for its poor performance:

Referring to FIG. 1 to FIG. 5 , schematic cross-sectional structure diagrams corresponding to each step of a method for forming a semiconductor structure are shown.

1, a substrate 10 is provided, the substrate 10 includes a first region 10a and a second region 10b for forming an N-type transistor, the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region 10b .

Continuing to refer to FIG. 1, a gate dielectric layer is formed on the substrate 10, the gate dielectric layer on the substrate 10 in the first region 10a is the first gate dielectric layer 11a, and the gate dielectric layer on the substrate 10 in the second region 10b is the second gate dielectric layer. The second gate dielectric layer 11b; forming a first material layer 12 on the gate dielectric layer, and the first material layer 12 is located on the first gate dielectric layer 11a and the second gate dielectric layer 11b.

Referring to FIG. 2, a bottom antireflection layer 13 is formed on the first material layer 12; a graphic layer 14 is formed on the bottom antireflective layer 13, and the graphic layer 14 exposes the Bottom anti-reflection layer 13.

Referring to FIG. 3 , the bottom anti-reflection layer 13 on the second gate dielectric layer 11 b (as shown in FIG. 2 ) is removed to expose the first material layer 12 on the second gate dielectric layer 11 b.

Referring to FIG. 4 , the exposed first material layer 12 (as shown in FIG. 3 ) is removed to expose the second gate dielectric layer 11b.

With reference to Fig. 5, remove described graphic layer 14 and remaining described bottom anti-reflection layer 13 (as shown in Fig. 4), expose described first material layer 12; The second material layer 16 on the second gate dielectric layer 11b.

Since the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region, the thickness of the N-type transistor work function layer formed on the substrate 10 in the first region 10a is greater than that in the substrate 10 in the second region 10b. Form the thickness of the N-type transistor work function layer.

Therefore, the first material layer 12 and the second material layer 16 on the first gate dielectric layer 11a form the first work function layer; the second material layer 16 on the second gate dielectric layer 11b forms the The second work function layer, so that the thickness of the N-type transistor work function layer formed on the substrate 10 in the first region 10a is greater than the thickness of the N-type transistor work function layer formed on the substrate 10 in the second region 10b. Moreover, the thickness of the first material layer 12 is equal to the thickness difference between the first work function layer and the second work function layer, about

Therefore, the bottom anti-reflection layer 13 formed on the first material layer 12 needs to expose the first material layer 12 on the second gate dielectric layer 11b for removal. In the prior art, dry etching 15 (as shown in FIG. 3 ) is often used to remove the bottom anti-reflection layer 13 on the second gate dielectric layer 11b, so as to expose the first material layer 12. Due to the small thickness of the first material layer 12, only Therefore, the ability of the first material layer 12 to protect the second gate dielectric layer 11b below is limited. Therefore, the method of removing the bottom anti-reflection layer 13 on the second gate dielectric layer 11b by dry etching 15 will often damage the second gate dielectric layer 11b, thus resulting in poor performance of the formed semiconductor structure.

In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising:

forming a substrate, the substrate includes a first region and a second region for forming a transistor, and the threshold voltage of the transistor in the first region is greater than the threshold voltage of the transistor in the second region; forming a dummy gate structure on the substrate; Forming a dielectric layer on the substrate between adjacent dummy gate structures; removing the dummy gate structure to form an opening in the dielectric layer; forming a gate dielectric layer at the bottom of the opening, located at the bottom of the opening in the dielectric layer in the first region The gate dielectric layer is a first gate dielectric layer, and the gate dielectric layer at the bottom of the opening in the second region dielectric layer is a second gate dielectric layer; a sacrificial layer is formed on the second gate dielectric layer; forming a first material layer on the gate dielectric layer and the sacrificial layer; forming a first mask on the first material layer, the first mask exposing the first material layer on the second gate dielectric layer; The first mask is a mask, and the first material layer and the sacrificial layer on the second gate dielectric layer are removed to expose the second gate dielectric layer; the first mask is removed to expose the first The first material layer on the gate dielectric layer; forming a second material layer on the first material layer of the first gate dielectric layer and the second gate dielectric layer.

In the technical solution of the present invention, after forming the gate dielectric layer, a sacrificial layer is formed on the second gate dielectric layer, and a first material layer is formed on the sacrificial layer; in the process of forming the first mask, the sacrificial layer and the The first material layer protects the second gate dielectric layer. Compared with the prior art that only relies on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIGS. 6 to 16 show schematic cross-sectional structures corresponding to each step of an embodiment of the semiconductor structure forming method of the present invention.

Referring to FIG. 6, a substrate (not shown in the figure) is formed, the substrate includes a first region 100na and a second region 100nb for forming transistors, and the threshold voltage of transistors in the first region 100na is greater than that of the second region 100nb threshold voltage of the transistor.

The substrate is used to provide a process basis for subsequent semiconductor processes.

In this embodiment, the semiconductor structure is a fin field effect transistor, and the base includes a substrate 100 and discrete fins 110 on the substrate 100 .

The substrate 100 is used to provide an operating platform for a semiconductor process, and the fin portion 110 is used to form a fin field effect transistor.

In this embodiment, the step of forming the base includes: providing an initial substrate; etching the initial substrate to form the substrate 100 and the discrete fins 110 on the substrate 100 .

The initial substrate is used to form the substrate 100 and etch to form the fins 110 . In this embodiment, the material of the initial substrate is single crystal silicon. Therefore, the material of the substrate 100 and the fin portion 110 is also single crystal silicon.

In other embodiments of the present invention, the material of the initial substrate may also be selected from germanium, gallium arsenide or silicon germanium compounds; the initial substrate may also be other semiconductor materials. In addition, the initial substrate can also be selected from a structure having an epitaxial layer or a silicon-on-epitaxial layer. The substrate can be selected to be suitable for process requirements or easy to integrate; the material of the semiconductor layer can be selected to be suitable for forming fins.

The step of etching the initial substrate includes: forming a patterned fin mask layer (not shown in the figure) on the initial substrate; using the fin mask layer as a mask, etching the The initial substrate is used to form the substrate 100 and the discrete fins 110 on the substrate 100 . The fin mask layer may be a patterned photoresist layer, a hard mask layer or a mask layer formed by multiple patterned masking processes.

In addition, the base further includes an isolation layer (not shown) between adjacent fins 110 , the top surface of the isolation layer is lower than the top surface of the fins 110 to expose the fins 110 Partial surfaces of the top surface and side walls. Therefore, after forming the substrate 100 and the fins 110 , the forming method further includes: forming the isolation layer between adjacent fins 110 .

The isolation layer is used to realize electrical isolation between adjacent fins 110 and between the semiconductor structure and other semiconductor structures on the substrate 100 .

In this embodiment, the material of the isolation layer is silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride. It should be noted that, in this embodiment, after the isolation layer is formed, the fin mask layer is removed through a wet etching process, so as to expose the top surface of the fin. Specifically, since the material of the fin mask layer is silicon nitride, the etching solution used in the wet etching process is a phosphoric acid solution.

In this embodiment, both the substrate of the first region 100na and the substrate of the second region 100nb are used to form N-type transistors. The threshold voltage of the N-type transistor formed on the substrate of the first region 100na is higher than that of the N-type transistor formed on the substrate of the second region 100nb, that is, the substrate of the first region 100na is used to form a high threshold voltage N-type transistors, the base of the second region 100nb is used to form N-type transistors with low threshold voltage.

In addition, the substrate further includes a third region 100p. Specifically, the base of the third region 100p is used to form a P-type transistor.

Continuing to refer to FIG. 6 , a dummy gate structure 120 is formed on the substrate.

The dummy gate structure 120 is used to occupy a space position for a subsequently formed gate structure.

The dummy gate structure 120 includes a dummy oxide layer on the substrate and a dummy gate on the dummy oxide layer. In this embodiment, the material of the dummy oxide layer is silicon oxide; the material of the dummy gate is polysilicon.

Specifically, the step of forming the dummy gate structure 120 includes: forming an oxide layer on the surface of the substrate; forming a gate electrode material layer on the oxide layer; forming a gate mask on the gate electrode material layer; The gate mask is a mask, and the gate electrode material layer is etched until the surface of the oxide layer is exposed to form the dummy gate and the dummy oxide layer covered by the dummy gate.

After forming the dummy gate structure 120 , the forming method further includes forming gate spacers located on sidewalls of the dummy gate and the dummy oxide layer. The gate spacer is a stacked structure of silicon oxide-silicon nitride-silicon oxide. In other embodiments of the present invention, the gate spacer can also be a single-layer structure of silicon nitride or other materials.

In this embodiment, the semiconductor structure is a fin field effect transistor, so the step of forming the dummy gate structure 120 includes: forming the dummy gate structure 120 on the fin portion 110, and the dummy gate structure 120 straddles the The fin 110 covers part of the top and sidewall of the fin 110 .

Continuing to refer to FIG. 6 , a dielectric layer 130 is formed on the substrate between adjacent dummy gate structures 120 .

The dielectric layer 130 is an interlayer dielectric layer for realizing electrical isolation between semiconductor structures.

In this embodiment, the material of the dielectric layer 130 is silicon oxide. In other embodiments of the present invention, the material of the dielectric layer can also be selected from silicon nitride, silicon oxynitride, low K dielectric material (dielectric constant greater than or equal to 2.5, less than 3.9) or ultra-low K dielectric material (dielectric constant One or more combinations of electrical constants less than 2.5).

The step of forming the dielectric layer 130 includes: forming a dielectric material layer on the substrate 100 between adjacent fins 110, the top surface of the dielectric material layer is higher than the gate mask layer; The material layer is planarized until the dummy gate is exposed. Therefore, the planarization process to the dielectric material layer also removes the gate mask layer, so that the formed dielectric layer 130 is flush with the top surface of the dummy gate, exposing the top surface of the dummy gate .

It should be noted that, after forming the dummy gate structure 120 and before forming the dielectric layer 130 , the forming method further includes: forming a stress layer (not shown in the figure) in the substrate on both sides of the dummy gate structure 120 .

The stress layer is used to form a source region or a drain region of the semiconductor structure.

It should be noted that, in this embodiment, since the substrate of the first region 100na and the substrate of the second region 100nb are used to form an N-type transistor, the substrate of the third region 100p is used to form a P-type transistor. Therefore, the stress layer formed in the substrate of the first region 100na and the substrate of the second region 100nb is a "square" stress layer of carbon silicon material, and the stress layer formed in the substrate of the third region 100p is silicon germanium The "Σ-shaped" stress layer of the material.

It should also be noted that after forming the stress layer and before forming the dielectric layer 130, the forming method further includes: forming a contact hole etching stop covering the substrate, the stress layer, and the sidewall of the gate spacer. layers (not shown in the figure).

The methods for forming the stress layer and the contact hole etching stop layer are the same as those in the prior art, and the present invention will not repeat them here.

Referring to FIG. 7 , the dummy gate structure 120 (as shown in FIG. 6 ) is removed, and an opening 121 is formed in the dielectric layer 130 .

The opening 121 is used to provide a process space for subsequent formation of a gate structure.

The step of forming the opening 121 includes: removing the dummy gate to expose the dummy oxide layer under the gate; removing the dummy oxide layer to form the opening 121, and the bottom of the opening 121 exposes the substrate surface. Specifically, the dummy gate and the dummy oxide layer can be removed by dry etching.

In this embodiment, the semiconductor structure is a FinFET, and the substrate includes a first region 100na, a second region 100nb and a third region 100p. Therefore, the step of forming the opening includes: removing the dummy gate structure 120, respectively in the dielectric layer 130 in the first region 100na, in the dielectric layer 130 in the second region 100nb and in the third region 100p. An opening 121 is formed in the dielectric layer 130 .

The bottom of the opening 121 exposes part of the top and part of the sidewall surface of the fin 110 in the first region 100na, part of the top and part of the sidewall surface of the fin 110 in the second region 100nb, and part of the fin 110 in the third region 100p. Top and some side wall surfaces.

Referring to Figure 8 and Figure 9, the structure of the 100na region in the middle of Figure 9 is a schematic cross-sectional structure diagram along the AA line in Figure 8; the structure of the 100nb region on the right side in Figure 9 is a schematic cross-sectional structure diagram along the BB line in Figure 8 ; The structure of the 100p region on the left side of FIG. 9 is a schematic cross-sectional structure diagram along CC line in FIG. 8 .

A gate dielectric layer (not shown in the figure) is formed at the bottom of the opening 121, the gate dielectric layer at the bottom of the opening 121 in the dielectric layer 130 in the first region 100na is the first gate dielectric layer 140na, and is located in the second region 100nb The gate dielectric layer at the bottom of the opening 121 in the dielectric layer 130 is the second gate dielectric layer 140nb.

In this embodiment, the substrate further includes a third region 100p, so the gate dielectric layer at the bottom of the opening 121 in the dielectric layer 130 in the third region 100p is the third gate dielectric layer 140p.

The gate dielectric layer is used to form a gate structure and isolate the subsequently formed gate electrode from the channel region of the semiconductor structure.

In this embodiment, the semiconductor structure has a "high-K metal gate" structure, so the step of forming the gate dielectric layer includes: forming a gate dielectric layer including a high-K dielectric layer.

The material of the high-K dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-K dielectric layer is hafnium oxide. In other embodiments of the present invention, the material of the high-K dielectric layer can also be selected from zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, strontium titanate, aluminum oxide lanthanum, yttrium oxide, hafnium oxynitride, zirconium oxynitride, One or more of lanthanum oxynitride, aluminum oxynitride, titanium oxynitride, strontium titanium oxynitride, lanthanum aluminum oxynitride, and yttrium oxynitride.

The method for forming the gate dielectric layer is a film deposition method such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

It should be noted that, after forming the opening and before forming the gate dielectric layer, the forming method further includes: forming an interface layer (Interface Layer, IL) (not shown in the figure) at the bottom of the opening 121 to alleviate the The problem of lattice mismatch between the substrate and the gate dielectric layer.

Specifically, as shown in FIG. 9, the first gate dielectric layer 140na is located on the surface of part of the top and part of the sidewall of the fin 110 in the first region 100na; the second gate dielectric layer 140nb is located on the second The region 100nb is on part of the top and part of the sidewall surface of the fin 110; the third gate dielectric layer 140p is located on the part of the top and part of the sidewall surface of the fin 110 in the third region 100p.

Referring to FIGS. 10 to 12 , a sacrificial layer 160 is formed on the second gate dielectric layer 140nb.

The sacrificial layer 160 is used to protect the second gate dielectric layer 140nb in subsequent processes to prevent the second gate dielectric layer 140nb from being damaged. In this embodiment, the sacrificial layer 160 is used to protect the second gate dielectric layer 140nb during the subsequent formation of the first mask, so as to prevent the second gate dielectric layer 140nb from being affected by the etching process.

If the thickness of the sacrificial layer 160 is too small, it is difficult to protect the second gate dielectric layer 140nb in subsequent processes, and it is difficult to reduce the possibility of damage to the second gate dielectric layer 140nb; If the thickness of the layer 160 is too large, it will easily cause material waste and increase the difficulty of the process. In this embodiment, the thickness of the sacrificial layer 160 is arrive within range.

In this embodiment, the step of forming the sacrificial layer 160 includes: as shown in FIG. 10 , forming an initial material layer 160 a on the gate dielectric layer; as shown in FIG. 11 , removing the The initial material layer 160a is exposed to the first gate dielectric layer 140na, and the initial material layer 160a (as shown in FIG. 10 ) on the second gate dielectric layer 140nb serves as the sacrificial layer 160 .

Specifically, referring to FIG. 10 , an initial material layer 160 a is formed on the gate dielectric layer.

Since the substrate includes a first region 100na and a second region 100nb, the initial material layer 160a covers the first gate dielectric layer 140na and the second gate dielectric layer 140nb.

It should be noted that, in this embodiment, the substrate further includes a third region 100p, so in the step of forming the initial material layer 160a, the initial material layer 160a is also located on the third gate dielectric layer 140p. The initial material layer 160 on the third gate dielectric layer 140p is also used to form a transistor work function layer in the third region 100p. The advantage of this method is that there is no need to increase the semiconductor process to realize the formation of the initial material layer 160a, which is beneficial to reduce process steps and process cost.

In this embodiment, the base of the third region 100p is used to form a P-type transistor, so the material of the initial material layer 160a is titanium nitride.

Specifically, the initial material layer 160a may be formed on the gate dielectric layer by chemical vapor deposition, physical vapor deposition or atomic layer deposition or other film deposition methods.

It should be noted that since the initial material layer 160a is used to form the sacrificial layer 160 and is also used to form the work function layer of the transistor in the third region 100p, the thickness of the initial material layer 160a should not be too large. Should not be too small. If the thickness of the initial material layer 160a is too small, the thickness of the formed sacrificial layer 160 is too small to protect the second gate dielectric layer 140nb, and the thickness of the initial material layer 160a is too large. A small thickness will also affect the thickness of the transistor work function layer in the third region 100p formed subsequently, making it difficult to adjust the threshold voltage of the transistor in the third region 100p; if the thickness of the initial material layer 160a is too large, it will easily cause material waste, and It will increase the difficulty of the process. In this embodiment, in the step of forming the initial material layer 160a, the thickness of the initial material layer 160a is arrive within range.

Referring to FIG. 10, the initial material layer 160a on the first gate dielectric layer 140na is removed to expose the first gate dielectric layer 140na, and the initial material layer 160a on the second gate dielectric layer 140nb serves as the sacrificial layer 160.

Specifically, the step of removing the initial material layer 160a on the first gate dielectric layer 140na includes: forming a high voltage area mask 160b on the initial material layer 160a, and the high voltage area mask 160b exposes the first gate dielectric layer 160a. The initial material layer 160a on the dielectric layer 140na; using the high voltage area mask 160b as a mask, remove the initial material layer 160a on the first gate dielectric layer 140na to expose the first gate dielectric layer 140na.

The high voltage region mask 160b is used to form the second mask to protect the initial material layer 160a on the second gate dielectric layer 140nb during the semiconductor process.

Specifically, the step of forming the second mask includes:

A second mask material layer is formed on the initial material layer 160a; a first pattern layer 160c is formed on the second mask material layer, and the first pattern layer 160c is exposed on the first gate dielectric layer 140na The second mask material layer; using the first pattern layer 160c as a mask, remove the second mask material layer on the first gate dielectric layer 140na, exposing the initial pattern on the first gate dielectric layer 140na The material layer 160a forms the high voltage region mask 160b to constitute the second mask.

Wherein, the second mask material layer is used to form the high voltage area mask 160b to form the second mask. Specifically, in the step of forming the second mask material layer, the second mask material layer is a bottom anti-reflection layer, which can be formed through a coating process.

The first pattern layer 160c is used to pattern the second mask material layer to form a second mask. Specifically, in this embodiment, the first pattern layer 160c is a photoresist layer, which can be formed by a coating process and a photolithography process. In other embodiments of the present invention, the first pattern layer 160c may also be a mask formed by multiple masking processes.

The step of removing the second mask material layer on the first gate dielectric layer 140na is used to expose the initial material layer 160a on the first gate dielectric layer 140na to form the high-voltage region mask 160b to provide for subsequent processes. craft surface.

Specifically, the step of removing the second mask material layer on the first gate dielectric layer 140na includes: removing the second mask material layer on the first gate dielectric layer 140na by dry etching. Since the initial material layer 160a is formed on the first gate dielectric layer 140na, the initial material layer 160a can effectively protect the first gate dielectric layer 140na and prevent the first gate dielectric layer 140na from being subjected to a dry etching process. damage.

It should be noted that, in this embodiment, the substrate further includes a third region 100p, and the initial material layer 160a on the third gate dielectric layer 140p is subsequently used to form a work function layer of a transistor in the third region 100p.

Therefore, in the step of forming the second mask, the second mask is also located on the third gate dielectric layer 140p, that is, the high voltage region mask 160b is also located on the third gate dielectric layer 140p , used to protect the initial material layer 160a on the third gate dielectric layer 140p.

Continuing to refer to FIG. 11 , using the second mask as a mask, the initial material layer 160a on the first gate dielectric layer 140na is removed to expose the first gate dielectric layer 140na.

In this embodiment, the initial material layer 160a on the first gate dielectric layer 140na is removed by wet etching by using the high voltage region mask 160b as a mask to expose the first gate dielectric layer 140na.

The method of removing the initial material layer 160a by using a wet etching process can effectively reduce the influence of the process of removing the initial material layer 160a on the first gate dielectric layer 140na, and reduce the impact on the first gate dielectric layer 140na. possibility of injury.

Since the material of the initial material layer 160a is titanium nitride, in the step of removing the initial material layer 160a by wet etching, the etching solution is a mixed solution of NH ₄ OH, H ₂ O ₂ and water (SC1 solution) or a mixed solution of NH ₄ , H ₂ O ₂ and water or a mixed solution of HCl, H ₂ O ₂ and water (SC2 solution).

Specifically, in this embodiment, in the step of removing the initial material layer 160a, the etching solution is a mixed solution of HCl, H ₂ O ₂ and water, wherein the mass percentage ratio of HCl, H ₂ O ₂ and water is between In the range of 1:3:200 to 3:3:200, the etching temperature is in the range of 20°C to 80°C.

In other embodiments of the present invention, the step of removing the initial material layer may also use a mixed solution of NH ₄ OH, H ₂ O ₂ and water or a mixed solution of NH ₄ , H ₂ O ₂ and water. Among them, the mixed solution of NH ₄ OH, H ₂ O ₂ and water is SC1 solution, and the etching temperature is in the range of 20°C to 80°C; in the mixed solution of NH ₄ , H ₂ O ₂ and water, NH ₄ , H ₂ O The mass percentage ratio of ₂ and water is in the range of 1:200:1000 to 5:200:1000.

It should be noted that since the third gate dielectric layer 140p also has a second mask, the initial material layer 160a on the third gate dielectric layer 140p is retained and is not affected by the etching process.

Referring to FIG. 12 , after the initial material layer 160a on the first gate dielectric layer 140na is removed, the second mask is removed to expose the initial material layer 160a on the second gate dielectric layer 140nb to form a sacrificial layer 160 .

The step of removing the second mask is used to expose the initial material layer 160a on the second gate dielectric layer 140na to form a sacrificial layer 160 to provide an operating surface for subsequent processes.

In this embodiment, the second mask is formed by the bottom anti-reflection layer, so in the step of removing the second mask, the second mask is removed by ashing. Specifically, the high voltage region mask 160b is removed by ashing to expose the sacrificial layer 160 .

The method of removing the second mask by ashing can avoid the influence of the removal process on the exposed first gate dielectric layer 140na, and reduce the possibility of damage to the first gate dielectric layer 140na.

It should be noted that the high-voltage region mask 160 is also located on the third gate dielectric layer 140p, so the step of removing the high-voltage region mask 160 by ashing also exposes the The initial material layer 160a.

Continuing to refer to FIG. 12 , a first material layer 161 is formed on the first gate dielectric layer 140na and the sacrificial layer 160 .

The first material layer 161 is used to protect the second gate dielectric layer 140nb in subsequent semiconductor processes. In this embodiment, the first material layer 161 on the second gate dielectric layer 140nb, together with the sacrificial layer 160, reduces the impact of the etching process on the second gate dielectric during the subsequent formation of the first mask. layer 140nb, reducing the possibility of damage to the second gate dielectric layer 140nb.

In addition, the first material layer 161 on the first gate dielectric layer 140na is also used to form the work function layer of the transistor formed on the base of the first region 100na. The advantage of this approach is that without adding process steps, the protection ability of the second gate dielectric layer 140nb can be improved and the formation of the transistor work function layer formed on the base of the first region 100na is beneficial to simplify the process steps , reduce process cost.

In this embodiment, the substrate of the first region 100na is used to form an N-type transistor, so the material of the first material layer 161 is titanium nitride, which can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. .

It should be noted that if the thickness of the first material layer 161 is too small, it will not be able to protect the second gate dielectric layer 140nb in the subsequent process, and it will also affect the formed first region 100nb substrate. The formation of the transistor work function layer; if the thickness of the first material layer 161 is too large, it will easily cause material waste and increase the difficulty of the process. In this embodiment, the thickness of the first material layer 161 is arrive within range.

It should also be noted that during the process of forming the first material layer 161, the initial material layer 160a on the third gate dielectric layer 140p is also exposed, so in the step of forming the first material layer 161, the The first material layer 161 is also located on the third gate dielectric layer 140p.

Referring to FIG. 13 and FIG. 14 , a first mask 170 is formed on the first material layer 161 , and the first mask 170 exposes the first material layer 161 on the second gate dielectric layer 140nb.

The first mask 170 is used to protect the first region 100na during the semiconductor process, preventing the first material layer 161 on the first gate dielectric layer 140na from being affected. In this embodiment, the first mask 170 is used to protect the sacrificial layer 160 and the first material layer 161 on the second gate dielectric layer 140nb to protect the The first material layer 161 .

Specifically, the step of forming the first mask 170 includes:

As shown in FIG. 13 , a first mask material layer 170 a is formed on the first material layer 161 .

The first mask material layer 170a is used to form the first mask.

In this embodiment, the substrate includes a first region 100na, a second region 100nb, and a third region 100p, so the first mask material layer 170p is located on the first gate dielectric layer 140na, the second gate dielectric layer 140nb and on the third gate dielectric layer 140p.

Specifically, in the step of forming the first mask material layer 170a, the first mask material layer 170 is a bottom anti-reflection layer, which can be formed through a coating process.

After forming the first mask material layer 170a, a second pattern layer 170b is formed on the first mask material layer 170a, and the second pattern layer 170b exposes the first gate dielectric layer 140nb. Mask material layer 170a.

The second pattern layer 170b is used to pattern the first mask material layer 170a. The second pattern layer 170b exposes the first mask material layer 170a on the second gate dielectric layer 140nb to provide an operating surface for the subsequent process of exposing the first material layer 161 on the second gate dielectric layer 140nb .

In this embodiment, the second pattern layer 170b is a photoresist layer, which can be formed by a coating process and a photolithography process. In other embodiments of the present invention, the second pattern layer 170b may also be a mask formed by multiple masking processes.

It should be noted that, the second pattern layer 170b is also located on the first mask material layer 170a on the third gate dielectric layer 140p.

Referring to FIG. 14, using the second pattern layer 170b as a mask, remove the first mask material layer 170a (as shown in FIG. 13 ) on the second gate dielectric layer 140nb, exposing the second gate dielectric layer The first material layer 161 on 140nb and the remaining first mask material layer 170a form the first mask 170 .

The step of removing the first mask material layer 170a on the second gate dielectric layer 140nb is used to provide a process surface for subsequent removal of the sacrificial layer 161 and the first material layer 161 on the second gate dielectric layer 140nb.

In this embodiment, the first mask material layer 170a is a bottom anti-reflection layer, so the step of removing the first mask material layer 170a on the second gate dielectric layer 140nb includes: using the second pattern layer 170b is a mask, and the first mask material layer 170a on the second gate dielectric layer 140nb is removed by dry etching to expose the first material layer 161 on the second gate dielectric layer 140nb.

Since the second gate dielectric layer 140nb has the sacrificial layer 160 and the first material layer 161, and compared with the prior art with only the first material layer 161, the sacrificial layer 160 and the first material layer 161 thicker, stronger protection capability, can effectively reduce the possibility of damage to the second gate dielectric layer 140nb, reduce the occurrence of damage to the second gate dielectric layer 140nb, and help improve the second gate dielectric layer 140nb The quality of the dielectric layer 140nb improves the performance of the formed semiconductor structure.

Specifically, in the step of removing the first mask material layer 170a on the second gate dielectric layer 140nb by dry etching, the process parameters include: the etching gas is CH ₄ , H ₂ and N ₂ ; The flow rate of the etching gas is in the range of 5sccm to 50sccm for _CH4 , the flow rate of _H2 is in the range of 100sccm to 800sccm, the flow rate of _N2 is in the range of 20sccm to 200sccm; the pressure is 1mTorr to 150mTorr; the power is 100W to 200W; The voltage is in the range of 10V to 300V; the process temperature is in the range of 20°C to 90°C; the time is in the range of 30s to 1000s.

It should be noted that, since the second pattern layer 170b is also located on the first mask material layer 170a on the third gate dielectric layer 140p, in the step of forming the first mask 170, the first mask The film 170 is also located on the third gate dielectric layer 140p to protect the first material layer 161 and the initial material layer 160a on the third gate dielectric layer 140p.

Referring to FIG. 15, using the first mask 170 as a mask, remove the first material layer 161 (as shown in FIG. 14 ) and the sacrificial layer 160 (as shown in FIG. 14 ) on the second gate dielectric layer 140nb , exposing the second gate dielectric layer 140nb.

The step of removing the first material layer 161 and the sacrificial layer 160 on the second gate dielectric layer 140nb is used to provide a process surface for subsequent processes.

Specifically, the step of removing the first material layer 161 and the sacrificial layer 160 on the second gate dielectric layer 140nb includes: removing the first material layer 161 on the second gate dielectric layer 140nb by wet etching and a sacrificial layer 160 .

The method of removing the first material layer 161 and the sacrificial layer 160 on the second gate dielectric layer 140nb by wet etching can effectively reduce the influence of the removal process on the second gate dielectric layer 140nb, and reduce the second gate dielectric layer 140nb. The possibility of damage to the dielectric layer 140nb.

In this embodiment, since the material of the first material layer 161 and the sacrificial layer 160 is titanium nitride, the first material layer 161 on the second gate dielectric layer 140nb is removed by wet etching and sacrificial layer 160, the etching solution is a mixed solution of NH ₄ OH, H ₂ O ₂ and water (SC1 solution) or a mixed solution of NH ₄ , H ₂ O ₂ and water or HCl, H ₂ O ₂ and Mixed solution of water (SC2 solution).

Specifically, in this embodiment, in the step of removing the first material layer 161 and the sacrificial layer 160, the etching solution is a mixed solution of HCl, H ₂ O ₂ and water, wherein HCl, H ₂ O ₂ The mass percentage ratio of water and water is in the range of 1:3:200 to 3:3:200, and the etching temperature is in the range of 20°C to 80°C.

In other embodiments of the present invention, the step of removing the first material layer and the sacrificial layer 160 may also use a mixed solution of NH ₄ OH, H ₂ O ₂ and water or a mixed solution of NH ₄ , H ₂ O ₂ and water solution. Among them, the mixed solution of NH ₄ OH, H ₂ O ₂ and water is SC1 solution, and the etching temperature is in the range of 20°C to 80°C; in the mixed solution of NH ₄ , H ₂ O ₂ and water, NH ₄ , H ₂ O The mass percentage ratio of ₂ and water is in the range of 1:200:1000 to 5:200:1000.

It should be noted that since the first mask 170 is also located on the third gate dielectric layer 140p, the initial material layer 160a and the first material layer 161 on the third gate dielectric layer 140p are retained , not affected by the etching process.

Referring to FIG. 16 , after exposing the second gate dielectric layer 140nb, the first mask 170 (as shown in FIG. 15 ) is removed to expose the first material layer 161 on the first gate dielectric layer 140na.

The step of removing the first mask 170 is used to provide a process surface for the subsequent formation of the second material layer.

In this embodiment, the first mask 170 is formed by a bottom anti-reflection layer, so the step of removing the first mask 170 includes: removing the first mask 170 by ashing. The method of removing the first mask 170 by ashing can avoid the influence of the removal process on the exposed second gate dielectric layer 140nb, and reduce the possibility of damage to the second gate dielectric layer 140nb.

It should be noted that since the first mask 170 is still located on the third gate dielectric layer 140p, the step of removing the first mask 170 by ashing also exposes the third gate dielectric layer 140p. A first material layer 161 on layer 140p.

Continuing to refer to FIG. 16 , a second material layer 171 is formed on the first material layer 161 of the first gate dielectric layer 140na and the second gate dielectric layer 140nb.

The second material layer 171 is used to form the work function layer of the transistor formed in the second region 100nb, and is also used to form the work function layer of the transistor formed in the first region 100na.

Therefore, since the substrate in the first region 100na and the substrate in the second region 100nb are used to form an N-type transistor, the material of the second material layer is titanium nitride, which can be deposited by chemical vapor deposition, physical vapor deposition or atomic Layer deposition and other film deposition processes are formed.

It should be noted that, since the step of removing the first mask 170 also exposes the first material layer 161 on the third gate dielectric layer 140p, in the step of forming the second material layer 171, the The second material layer 171 is also located on the third gate dielectric layer 140p to form a transistor work function layer formed on the base of the third region 100p.

In this embodiment, according to the threshold voltage of the transistor formed on the base of the second region 100nb, the thickness of the second material layer 171 is arrive within range.

It should be noted that the work function layer of the transistor formed on the base of the second region 100nb includes the second material layer 171 on the second dielectric layer 140nb; the work function layer of the transistor formed on the base of the first region 100nb includes The first material layer 161 and the second material layer 171 on the first gate dielectric layer 140na; the work function layer of the transistor formed on the base of the third region 100p includes the initial material layer 160a on the third gate dielectric layer 140p, the The first material layer 161 and the second material layer 171 .

Therefore, the thickness of the second material layer 171 is determined according to the threshold voltage of the transistor formed on the substrate of the second region 100nb; the thickness of the first material layer 161 is determined according to the threshold voltage of the transistor formed on the substrate of the first region 100na And the thickness of the second material layer 171 is determined; the thickness of the initial material layer 160a is based on the threshold voltage of the transistor formed on the substrate of the third region 100p, the thickness of the first material layer 161, the thickness of the second material layer The thickness of layer 171 is determined.

In this embodiment, the substrate of the first region 100na and the substrate of the second region 100nb are used to form an N-type transistor, and after forming the second material layer 171, the forming method further includes: A titanium aluminum layer is formed on the material layer 171 to form the work function layer of the transistor formed on the base of the first region 100na and the work function layer of the transistor formed on the base of the second region 100nb.

The method for forming the titanium-aluminum layer is the same as that of the prior art, and will not be repeated in the present invention.

To sum up, in the technical solution of the present invention, after forming the gate dielectric layer, a sacrificial layer is formed on the second gate dielectric layer, and a first material layer is formed on the sacrificial layer; layer and the first material layer protect the second gate dielectric layer. Compared with the prior art that only relies on the first material layer to protect the second gate dielectric layer, in the technical solution of the present invention, the total thickness of the first material layer and the sacrificial layer is larger, and the The protection ability of the second gate dielectric layer is stronger, which can effectively reduce the damage of the second gate dielectric layer during the formation of the first mask, which is beneficial to improve the performance of the gate dielectric layer and the performance of the formed semiconductor structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A kind of 1. forming method of semiconductor structure, it is characterised in that including：

   Substrate is formed, the substrate includes being used for first area and the second area for forming transistor, and the first area is brilliant The threshold voltage of body pipe is more than the threshold voltage of second area transistor；

   Pseudo- grid structure is formed on the substrate；

   Dielectric layer is formed in the adjacent pseudo- interstructural substrate of grid；

   Remove dummy gate structure and opening is formed in the dielectric layer；

   Gate dielectric layer is formed in the open bottom, the gate dielectric layer positioned at the first area dielectric layer inner opening bottom is the One gate dielectric layer, the gate dielectric layer positioned at the second area dielectric layer inner opening bottom are the second gate dielectric layer；

   Sacrifice layer is formed on second gate dielectric layer；

   First material layer is formed on first gate dielectric layer and sacrifice layer；

   Form the first mask in the first material layer, first mask exposes the on second gate dielectric layer One material layer；

   Using first mask as mask, first material layer and sacrifice layer on second gate dielectric layer are removed, is exposed described Second gate dielectric layer；

   First mask is removed, exposes the first material layer on first gate dielectric layer；

   Second material layer is formed in the first material layer of first gate dielectric layer and second gate dielectric layer.
2. 2. forming method as claimed in claim 1, it is characterised in that in the step of forming sacrifice layer, the thickness of the sacrifice layer Degree existsArriveIn the range of.
3. 3. forming method as claimed in claim 1, it is characterised in that the step of forming the sacrifice layer includes：

   Original material layer is formed on the gate dielectric layer；

   The original material layer on first gate dielectric layer is removed, exposes first gate dielectric layer, is situated between positioned at the second gate Original material layer on matter layer is as the sacrifice layer.
4. 4. forming method as claimed in claim 3, it is characterised in that remove the original material layer on first gate dielectric layer The step of include：

   The second mask is formed on the original material layer, second mask exposes the initial material on first gate dielectric layer The bed of material；

   Using second mask as mask, the original material layer on first gate dielectric layer is removed, exposes the first grid and is situated between Matter layer；

   Second mask is removed, exposes the original material layer on second gate dielectric layer, forms sacrifice layer.
5. 5. forming method as claimed in claim 4, it is characterised in that the step of forming second mask includes：

   The second mask layer is formed on the original material layer；

   The first graph layer is formed on second mask layer, first graph layer exposes on first gate dielectric layer The second mask layer；

   Using first graph layer as mask, the second mask layer on first gate dielectric layer is removed, exposes described the Original material layer on one gate dielectric layer, form second mask.
6. 6. forming method as claimed in claim 5, it is characterised in that in the step of forming the second mask layer, described the Two mask layers are bottom anti-reflection layer.
7. 7. forming method as claimed in claim 5, it is characterised in that remove the second mask material on first gate dielectric layer The step of bed of material, includes：The second mask layer on first gate dielectric layer is removed by way of dry etching.
8. 8. the forming method as described in claim 3 or 4, it is characterised in that remove the initial material on first gate dielectric layer The step of bed of material, includes：The original material layer on first gate dielectric layer is removed by way of wet etching.
9. 9. forming method as claimed in claim 4, it is characterised in that in the step of removing second mask, pass through ashing Mode remove second mask.
10. 10. forming method as claimed in claim 3, it is characterised in that in the step of forming substrate, the substrate also includes the Three regions；

    In the step of forming gate dielectric layer, the gate dielectric layer positioned at the 3rd Region Medium layer inner opening bottom is situated between for the 3rd grid Matter layer；

    In the step of forming original material layer, the original material layer is also located on the 3rd gate dielectric layer；

    In the step of forming the second mask, second mask is also located on the 3rd gate dielectric layer；

    In the step of forming the first material layer, the first material layer is also located on the 3rd gate dielectric layer；

    In the step of forming the first mask, first mask is also located on the 3rd gate dielectric layer；

    In the step of forming the second material layer, the second material layer is also located on the 3rd gate dielectric layer.
11. 11. forming method as claimed in claim 10, it is characterised in that in the step of forming substrate, the 3rd region base Bottom is used to form P-type transistor；

    In the step of forming the original material layer, the original material layer is titanium nitride.
12. 12. forming method as claimed in claim 1, it is characterised in that the step of forming first mask includes：

    The first mask layer is formed in the first material layer；

    Second graph layer is formed on first mask layer, the second graph layer exposes on second gate dielectric layer The first mask layer；

    Using the second graph layer as mask, the first mask layer on second gate dielectric layer is removed, exposes described the First material layer on two gate dielectric layers, form first mask.
13. 13. forming method as claimed in claim 12, it is characterised in that in the step of forming first mask layer, First mask layer is bottom anti-reflection layer.
14. 14. forming method as claimed in claim 12, it is characterised in that remove the first mask on second gate dielectric layer The step of material layer, includes：The first mask layer on second gate dielectric layer is removed by way of dry etching.
15. 15. forming method as claimed in claim 1, it is characterised in that remove the first material on second gate dielectric layer The step of layer and sacrifice layer, includes：First material layer on second gate dielectric layer and sacrificial is removed by way of wet etching Domestic animal layer.
16. 16. forming method as claimed in claim 1, it is characterised in that the step of removing first mask includes：Pass through ash The mode of change removes first mask.
17. 17. forming method as claimed in claim 1, it is characterised in that in the step of forming substrate, the first area and institute Second area is stated to be used to form N-type transistor；The material of the first material layer and the second material layer is titanium nitride.
18. 18. forming method as claimed in claim 1, it is characterised in that in the step of forming the first material layer, described The thickness of one material layer existsArriveIn the range of.
19. 19. forming method as claimed in claim 1, it is characterised in that the step of forming gate dielectric layer includes：Formation includes height The gate dielectric layer of K dielectric layer.
20. 20. forming method as claimed in claim 1, it is characterised in that the semiconductor structure is fin formula field effect transistor；

    The step of forming substrate includes：

    Initial substrate is provided；

    The initial substrate is etched, forms substrate and discrete fin on the substrate；

    The step of forming dummy gate structure includes：Form the pseudo- grid structure on the fin, dummy gate structure across Part surface at the top of the fin and the covering fin with side wall.