CN107799409A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN107799409A CN107799409A CN201610787056.5A CN201610787056A CN107799409A CN 107799409 A CN107799409 A CN 107799409A CN 201610787056 A CN201610787056 A CN 201610787056A CN 107799409 A CN107799409 A CN 107799409A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of forming method of semiconductor structure, including：Form substrate, including first area and second area；Form pseudo- grid structure；Form opening；Form the first gate dielectric layer and the second gate dielectric layer；Form sacrifice layer；Form first material layer；Form the first mask；Expose second gate dielectric layer；Expose the first material layer；Form second material layer.Compared with only leaning on the prior art that the first material layer protects second gate dielectric layer; in technical solution of the present invention; the first material layer and the gross thickness of the sacrifice layer are larger; it is stronger to the protective capability of second gate dielectric layer; it can effectively reduce by the second gate dielectric layer to be damaged in the first mask forming process; be advantageous to improve the performance of gate dielectric layer, improve the performance for forming semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of semiconductor structure.
Background technology
With the rapid development of semiconductor fabrication, semiconductor devices is and higher towards higher component density
The direction of integrated level is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor
The component density of device and the characteristic size of the raising transistor of integrated level are also less and less, in order to reduce posting for transistor gate
The grid structure of raw electric capacity, raising device speed, high-K gate dielectric layer and metal gates is introduced in transistor.
However, still having many problems demands to solve when forming metal gates on high-K gate dielectric layer, one of them is exactly work(
The matching problem of function, because work function will directly affect the threshold voltage (Vt) of device and the performance of transistor.So in high K
Work-function layer is introduced in metal-gate structures, so as to realize the regulation to device threshold voltage.
But work-function layer is introduced in high-K metal gate structure, the performance of semiconductor structure still has in the prior art
Wait to improve.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor structure, to improve the property of semiconductor structure
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is formed, the substrate includes being used for first area and the second area for forming transistor, and firstth area
The threshold voltage of domain transistor is more than the threshold voltage of second area transistor；Pseudo- grid structure is formed on the substrate；In phase
Dielectric layer is formed in the adjacent pseudo- interstructural substrate of grid；Remove dummy gate structure and opening is formed in the dielectric layer；Described
Open bottom forms gate dielectric layer, and the gate dielectric layer positioned at the first area dielectric layer inner opening bottom is the first gate medium
Layer, the gate dielectric layer positioned at the second area dielectric layer inner opening bottom is the second gate dielectric layer；In second gate medium
Sacrifice layer is formed on layer；First material layer is formed on first gate dielectric layer and sacrifice layer；Formation is located at first material
The first mask on the bed of material, first mask expose the first material layer on second gate dielectric layer；Covered with described first
Film is mask, removes first material layer and sacrifice layer on second gate dielectric layer, exposes second gate dielectric layer；Remove
First mask, expose the first material layer on first gate dielectric layer；The first of first gate dielectric layer
Second material layer is formed on material layer and second gate dielectric layer.
Compared with prior art, technical scheme has advantages below：
Technical solution of the present invention, after gate dielectric layer is formed, sacrifice layer is formed on the second gate dielectric layer, on sacrifice layer
Form first material layer；During the first mask is formed, with the sacrifice layer and first material layer protection described the
Two gate dielectric layers.Compared with only leaning on the technical scheme that the first material layer protects second gate dielectric layer, the technology of the present invention
In scheme, the gross thickness of the first material layer and the sacrifice layer is larger, to the protective capability of second gate dielectric layer more
By force, it can effectively reduce by the second gate dielectric layer to be damaged in the first mask forming process, be advantageous to improve the property of gate dielectric layer
Can, improve the performance for forming semiconductor structure.
Brief description of the drawings
Fig. 1 to Fig. 5 is cross-sectional view corresponding to a kind of each step of method for forming semiconductor structure.
Fig. 6 to Figure 16 is that cross-section structure corresponding to each step of the embodiment of method for forming semiconductor structure one of the present invention is illustrated
Figure.
Embodiment
From background technology, the semiconductor structure of the prior art for introducing work-function layer has that performance is bad to ask
Topic.The reason for its performance bad problem being analyzed in conjunction with a kind of forming method of semiconductor structure：
Referring to figs. 1 to Fig. 5, show that cross-section structure corresponding to a kind of each step of method for forming semiconductor structure is illustrated
Figure.
With reference to figure 1, there is provided substrate 10, the substrate 10 include being used for the first area 10a and second for forming N-type transistor
Region 10b, the threshold voltage of the first area transistor are more than the threshold voltage of the second area 10b transistors.
With continued reference to Fig. 1, gate dielectric layer is formed in the substrate 10, the grid in first area 10a substrates 10 are situated between
Matter layer is the first gate dielectric layer 11a, and the gate dielectric layer in second area 10b substrates 10 is the second gate dielectric layer 11b；Institute
State on gate dielectric layer formation first material layer 12, the first material layer 12 is located at the first gate dielectric layer 11a and described the
On two gate dielectric layer 11b.
With reference to figure 2, bottom anti-reflection layer 13 is formed in the first material layer 12；In the bottom anti-reflection layer 13
Graph layer 14 is formed, the graph layer 14 exposes the bottom anti-reflection layer 13 on the second gate dielectric layer 11b.
With reference to figure 3, the bottom anti-reflection layer 13 (as shown in Figure 2) on the second gate dielectric layer 11b is removed, is exposed described
First material layer 12 on second gate dielectric layer 11b.
With reference to figure 4, the first material layer 12 (as shown in Figure 3) exposed is removed, exposes second gate dielectric layer
11b。
With reference to figure 5, the graph layer 14 and the remaining bottom anti-reflection layer 13 (as shown in Figure 4) are removed, is exposed
The first material layer 12；The second material layer formed in the first material layer 12 and the second gate dielectric layer 11b
16。
Because the threshold voltage of the first area transistor is more than the threshold voltage of the second area transistor, therefore
The thickness that the first area 10a substrates 10 form N-type transistor work-function layer is more than the institute of second area 10b substrates 10
Form the thickness of N-type transistor work-function layer.
So the first material layer 12 and the second material layer 16 on the first gate dielectric layer 11a form the first work content
Several layers；The second material layer 16 on the second gate dielectric layer 11b forms second work-function layer, so that described
The thickness that one region 10a substrates 10 form N-type transistor work-function layer forms N more than the second area 10b substrates 10
The thickness of transistor npn npn work-function layer.And the thickness of the first material layer 12 and first work-function layer and described second
The thickness difference of work-function layer is equal, about
So the bottom anti-reflection layer 13 formed in first material layer 12 needs to expose on the second gate dielectric layer 11b
First material layer 12 to remove.Prior art usually removes described by the way of dry etching 15 (as shown in Figure 3)
Bottom anti-reflection layer 13 on two gate dielectric layer 11b, to expose the first material layer 12 on the second gate dielectric layer 11b.By
It is smaller in the thickness of the first material layer 12, be onlyLeft and right, therefore the first material layer 12 is to described the of lower section
Two gate dielectric layer 11b protective capability is limited.So the bottom on the second gate dielectric layer 11b is removed using dry etching 15
The way of anti-reflecting layer 13, the second gate dielectric layer 11b can usually be damaged, so as to cause the property of formed semiconductor structure
Can be bad.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is formed, the substrate includes being used for first area and the second area for forming transistor, and firstth area
The threshold voltage of domain transistor is more than the threshold voltage of second area transistor；Pseudo- grid structure is formed on the substrate；In phase
Dielectric layer is formed in the adjacent pseudo- interstructural substrate of grid；Remove dummy gate structure and opening is formed in the dielectric layer；Described
Open bottom forms gate dielectric layer, and the gate dielectric layer positioned at the first area dielectric layer inner opening bottom is the first gate medium
Layer, the gate dielectric layer positioned at the second area dielectric layer inner opening bottom is the second gate dielectric layer；In second gate medium
Sacrifice layer is formed on layer；First material layer is formed on first gate dielectric layer and sacrifice layer；Formation is located at first material
The first mask on the bed of material, first mask expose the first material layer on second gate dielectric layer；Covered with described first
Film is mask, removes first material layer and sacrifice layer on second gate dielectric layer, exposes second gate dielectric layer；Remove
First mask, expose the first material layer on first gate dielectric layer；The first of first gate dielectric layer
Second material layer is formed on material layer and second gate dielectric layer.
Technical solution of the present invention, after gate dielectric layer is formed, sacrifice layer is formed on the second gate dielectric layer, on sacrifice layer
Form first material layer；During the first mask is formed, with the sacrifice layer and first material layer protection described the
Two gate dielectric layers.Compared with only leaning on the prior art that the first material layer protects second gate dielectric layer, the technology of the present invention
In scheme, the gross thickness of the first material layer and the sacrifice layer is larger, to the protective capability of second gate dielectric layer more
By force, it can effectively reduce by the second gate dielectric layer to be damaged in the first mask forming process, be advantageous to improve the property of gate dielectric layer
Can, improve the performance for forming semiconductor structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 6 to Figure 16, show section knot corresponding to each step of the embodiment of method for forming semiconductor structure one of the present invention
Structure schematic diagram.
With reference to figure 6, substrate (not indicated in figure) is formed, the substrate includes being used for the first area for forming transistor
100na and second area 100nb, and the threshold voltage of the first area 100na transistors is more than the second area 100nb
The threshold voltage of transistor.
The substrate is used to provide Process ba- sis for Subsequent semiconductor technique.
In the present embodiment, the semiconductor structure is fin formula field effect transistor, and the substrate includes substrate 100 and position
In fin 110 discrete on the substrate 100.
The substrate 100 is used to provide operating platform for semiconductor technology, and the fin 110 is used to form fin field effect
Transistor.
In the present embodiment, formed substrate the step of include：Initial substrate is provided；The initial substrate is etched, forms substrate
100 and discrete fin 110 on the substrate 100.
The initial substrate is used to form substrate 100 and etching forms fin 110.In the present embodiment, the initial substrate
Material be monocrystalline silicon.So the material of the substrate 100 and the fin 110 is also monocrystalline silicon.
In other embodiments of the present invention, the material of the initial substrate is also selected from germanium, GaAs or SiGe chemical combination
Thing；The initial substrate can also be other semi-conducting materials.In addition, the initial substrate be also selected from epitaxial layer or
Epitaxial layer silicon-on.The substrate can select the substrate for being suitable to process requirements or being easily integrated；The material of the semiconductor layer
Material can select to suitably form the material of fin.
The step of etching the initial substrate includes：Patterned fin mask layer (figure is formed in the initial substrate
Not shown in)；Using the fin mask layer as mask, the initial substrate is etched, to form the substrate 100 and positioned at institute
State fin 110 discrete on substrate 100.The fin mask layer can be patterned photoresist layer, hard mask layer or multiple
The mask layer that pattern mask technique is formed.
In addition, the substrate also includes the separation layer (not indicated in figure) between adjacent fin 110, the separation layer
Top surface be less than the fin 110 top surface, to expose the part table of the top surface of fin 110 and side wall
Face.So being formed after the substrate 100 and the fin 110, the forming method also includes：Adjacent fin 110 it
Between form the separation layer.
The separation layer be used to realize between adjacent fin 110 and the semiconductor structure with substrate 100 other half
Electric isolution between conductor structure.
In the present embodiment, the material of the separation layer is silica.In other embodiments of the invention, the material of the separation layer
Material can also be silicon nitride or silicon oxynitride.It should be noted that in the present embodiment, after the separation layer is formed, pass through
Wet-etching technology removes the fin mask layer, to expose the top surface of the fin.Specifically, because the fin is covered
The material of film layer is silicon nitride, so used etching solution is phosphoric acid solution during the wet-etching technology.
In the present embodiment, the substrate of the first area 100na and the second area 100nb substrate are used to be formed
N-type transistor.The threshold voltage that the substrate of the first area 100na forms N-type transistor is higher than the second area
The N-type transistor that 100nb substrates are formed, that is to say, that the substrate of the first area 100na is used to form high threshold voltage
N-type transistor, the substrate of the second area 100nb is used for the N-type transistor for forming low threshold voltage.
In addition, the substrate also includes the 3rd region 100p.Specifically, the substrate of the 3rd region 100p is used for shape
Into P-type transistor.
With continued reference to Fig. 6, pseudo- grid structure 120 is formed on the substrate.
Dummy gate structure 120 is used to take up space position subsequently to be formed grid structure.
Dummy gate structure 120 includes the pseudo- oxide layer in the substrate and the pseudo- grid in the pseudo- oxide layer
Pole.In the present embodiment, the material of the pseudo- oxide layer is silica；The material of the dummy grid is polysilicon.
Specifically, the step of forming dummy gate structure 120 includes：Oxide layer is formed in the substrate surface；Described
Layer of gate electrode material is formed in oxide layer；Gate mask is formed in the layer of gate electrode material；Using the gate mask to cover
Film, etch the layer of gate electrode material and stop to the oxidation layer surface is exposed, form the dummy grid and by the pseudo- grid
The pseudo- oxide layer of pole covering.
Formed after dummy gate structure 120, the forming method also includes being formed being located at the dummy grid and the puppet
The grid curb wall of oxide layer side wall.The grid curb wall is the laminated construction of oxide-nitride-oxide.The present invention other
In embodiment, institute's grid curb wall can also be the single layer structure of the materials such as silicon nitride.
In the present embodiment, the semiconductor structure is fin formula field effect transistor, so forming dummy gate structure 120
Step includes：Form the pseudo- grid structure 120 on the fin 110, dummy gate structure 120 across the fin 110 and
Cover the part surface of the top of fin 110 and side wall.
With continued reference to Fig. 6, dielectric layer 130 is formed in the substrate between adjacent pseudo- grid structure 120.
The dielectric layer 130 is interlayer dielectric layer, for realizing the electric isolution between semiconductor structure.
In the present embodiment, the material of the dielectric layer 130 is silica.In other embodiments of the present invention, the medium
The material of layer is also selected from silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant is more than or equal to 2.5, less than 3.9)
Or one or more combinations in ultralow K dielectric materials (dielectric constant is less than 2.5).
The step of forming dielectric layer 130 includes：Dielectric material is formed on substrate 100 between adjacent fin 110
Layer, the top surface of the layer of dielectric material are higher than the gate mask layer；Planarization process is carried out to the layer of dielectric material
Stop to the dummy grid is exposed.So the gate mask layer is also removed to the planarization process of the layer of dielectric material,
Formed dielectric layer 130 is flushed with the top surface of the dummy grid, expose the top surface of the dummy grid.
It should be noted that being formed after pseudo- grid structure 120, formed before dielectric layer 130, the forming method is also wrapped
Include：Stressor layers (not indicated in figure) are formed in the substrate of the both sides of dummy gate structure 120.
The stressor layers are used for source region or the drain region for forming semiconductor structure.
It should be noted that in the present embodiment, substrate and the second area due to the first area 100na
100nb substrate is used to form N-type transistor, and the substrate of the 3rd region 100p is used to form P-type transistor.It is so described
The stressor layers formed in the 100na substrates of first area and in the second area 100nb substrates are " square " of carbon silicon materials
Stressor layers, the stressor layers formed in the 100p substrates of the 3rd region are " ∑ shape " stressor layers of germanium silicon material.
It should also be noted that, after stressor layers are formed, formed before dielectric layer 130, the forming method also includes：
The contact hole etching stop-layer for forming the covering substrate, the stressor layers and the grid curb wall side wall (is not marked in figure
Show).
The stressor layers and the forming method of the contact hole etching stop-layer are same as the prior art, and the present invention is herein not
Repeat again.
With reference to figure 7, dummy gate structure 120 (as shown in Figure 6) is removed, opening 121 is formed in the dielectric layer 130.
The opening 121 is used to provide state space to be subsequently formed grid structure.
The step of forming the opening 121 includes：Remove the dummy grid and expose the pseudo- oxide layer for below grid；
The pseudo- oxide layer is removed, forms the opening 121, the substrate surface is exposed in the bottom of the opening 121.Specifically, institute
Stating dummy grid and the pseudo- oxide layer can be removed by way of dry etching.
In the present embodiment, the semiconductor structure is fin formula field effect transistor, and the substrate includes first area
100na, second area 100nb and the 3rd region 100p.So the step of forming opening includes：Remove dummy gate structure
120, respectively the first area 100na dielectric layer 130 in, the second area 100nb dielectric layer 130 in and
Opening 121 is formed in the dielectric layer 130 of the 3rd region 100p.
Expose the table of the atop part and partial sidewall of first area 100na fins 110 respectively in 121 bottoms of the opening
The portion in face, the surface of the atop part of second area 100nb fins 110 and partial sidewall and the 3rd region 100p fins 110
At the top of point and partial sidewall surface.
With reference to reference to figure 8 and Fig. 9, the structure in wherein Fig. 9 centres 100na regions is to show in Fig. 8 along the sectional structure of AA lines
It is intended to；The structure in right side 100nb regions is along the cross section structure diagram of BB lines in Fig. 8 in Fig. 9；100p regions on the left of Fig. 9
Structure is along the cross section structure diagram of CC lines in Fig. 8.
Gate dielectric layer (not indicated in figure) is formed in 121 bottoms of the opening, positioned at the first area 100na dielectric layers
The gate dielectric layer of the bottom of 130 inner opening 121 is the first gate dielectric layer 140na, positioned at the second area 100nb dielectric layers 130
The gate dielectric layer of the bottom of inner opening 121 is the second gate dielectric layer 140nb.
In the present embodiment, the substrate also includes the 3rd region 100p, so in the 3rd region 100p dielectric layers 130
The gate dielectric layer of 121 bottoms of being open is the 3rd gate dielectric layer 140p.
The gate dielectric layer is used to form grid structure, isolates the raceway groove of the gate electrode subsequently formed and semiconductor structure
Region.
In the present embodiment, the semiconductor structure has " high-K metal gate " structure, so forming the step of the gate dielectric layer
Suddenly include：Being formed includes the gate dielectric layer of high-K dielectric layer.
The material of the high-K dielectric layer is the gate dielectric material that relative dielectric constant is more than silica relative dielectric constant.
In the present embodiment, the material of the high-K dielectric layer is hafnium oxide.In other embodiments of the invention, the material of the high-K dielectric layer
It is also selected from zirconium oxide, lanthana, aluminum oxide, titanium oxide, strontium titanates, aluminum oxide lanthanum, yittrium oxide, nitrogen oxidation hafnium, nitrogen oxidation
One or more in zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen oxidation strontium titanium, nitrogen oxidation lanthanum aluminium, yttrium oxynitride.
The method for forming the gate dielectric layer is sunk for film layers such as chemical vapor deposition, physical vapour deposition (PVD) or alds
The film deposition methods such as product.
It should be noted that being formed after opening, formed before the gate dielectric layer, the forming method also includes：
It is described opening 121 bottoms formed boundary layer (Interface Layer, IL) (not indicated in figure), for alleviate the substrate with
Lattice mismatch issue between the gate dielectric layer.
Specifically, as shown in figure 9, the first gate dielectric layer 140na is located at the first area 100na fins 110
At the top of point and on the surface of partial sidewall；The second gate dielectric layer 140nb is located at the second area 100nb fins 110
At the top of point and on the surface of partial sidewall；The 3rd gate dielectric layer 140p is located at the part of the 3rd region 100p fins 110
On top and the surface of partial sidewall.
With reference to figures 10 to Figure 12, sacrifice layer 160 is formed on the second gate dielectric layer 140nb.
The sacrifice layer 160 is used to protect the second gate dielectric layer 140nb in subsequent technique, avoids the second gate
Dielectric layer 140nb sustains damage.In the present embodiment, the sacrifice layer 160 is used in first mask process is subsequently formed
The second gate dielectric layer 140nb is protected, avoids the second gate dielectric layer 140nb from being influenceed by etching technics.
If the thickness of the sacrifice layer 160 is too small, it is difficult to play protection second gate medium in subsequent technique
Layer 140nb effect, it is difficult to reduce the impaired possibility of the second gate dielectric layer 140nb；If the thickness of the sacrifice layer 160
It is too big, then easily cause waste of material also to increase technology difficulty.In the present embodiment, the thickness of the sacrifice layer 160 exists
ArriveIn the range of.
In the present embodiment, the step of forming sacrifice layer 160, includes：As shown in Figure 10, the shape on the gate dielectric layer
Into original material layer 160a；As shown in figure 11, the original material layer 160a on the first gate dielectric layer 140na is removed, is exposed
The first gate dielectric layer 140na, the original material layer 160a (as shown in Figure 10) on the second gate dielectric layer 140nb
As the sacrifice layer 160.
Specifically, with reference to figure 10, the original material layer 160a formed on the gate dielectric layer.
Because the substrate includes first area 100na and second area 100nb, so the original material layer 160a covers
Cover the first gate dielectric layer 140na and the second gate dielectric layer 140nb.
It should be noted that in the present embodiment, the substrate also includes the 3rd region 100p, so forming the initial material
In the step of bed of material 160a, the original material layer 160a is also located on the 3rd gate dielectric layer 140p.3rd grid are situated between
Original material layer 160 on matter layer 140p is additionally operable to form the 3rd region 100p transistor work function layers.This way
It is advantageous in that, without increasing semiconductor technology to realize the formation of the original material layer 160a, advantageously reduces processing step,
Reduce process costs.
In the present embodiment, the 3rd region 100p substrates are used to form P-type transistor, so the original material layer
160a material is titanium nitride.
Specifically, the original material layer 160a can pass through chemical vapor deposition, physical vapour deposition (PVD) or atomic layer
The film deposition modes such as deposition are formed on the gate dielectric layer.
It should be noted that by the original material layer 160a be used for formed the sacrifice layer 160 be additionally operable to form institute
The work-function layer of the 3rd region 100p transistors is stated, so the thickness of the original material layer 160a is unsuitable excessive, also should not mistake
It is small.If the thickness of the original material layer 160a is too small, the thickness of the sacrifice layer 160 formed is too small, it is difficult to rises
To the effect for protecting the second gate dielectric layer 140nb, the thickness of the original material layer 160a is too small also to influence follow-up institute
Form the thickness of the 3rd region 100p transistor work function layers, it is difficult to realize the tune to the 3rd region 100p transistor threshold voltages
Section；If the thickness of the original material layer 160a is too big, waste of material is easily caused, can also increase technology difficulty.This reality
Apply in example, in the step of forming the original material layer 160a, the thickness of the original material layer 160a existsArriveModel
In enclosing.
With reference to figure 10, the original material layer 160a on the first gate dielectric layer 140na is removed, exposes the first grid and is situated between
Matter layer 140na, the original material layer 160a on the second gate dielectric layer 140nb is as the sacrifice layer 160.
Specifically, the step of removing the original material layer 160a on the first gate dielectric layer 140na includes：Described first
Higher-pressure region mask 160b is formed on beginning material layer 160a, the higher-pressure region mask 160b exposes the first gate dielectric layer 140na
On original material layer 160a；Using the higher-pressure region mask 160b as mask, remove first on the first gate dielectric layer 140na
Beginning material layer 160a, expose the first gate dielectric layer 140na.
The higher-pressure region mask 160b is used to form second mask, to protect the second gate in semiconductor processing
Original material layer 160a on dielectric layer 140nb.
Specifically, the step of forming second mask includes：
The second mask layer is formed on the original material layer 160a；Is formed on second mask layer
One graph layer 160c, the first graph layer 160c exposes the second mask layer on the first gate dielectric layer 140na；With
The first graph layer 160c is mask, removes the second mask layer on the first gate dielectric layer 140na, is exposed described
Original material layer 160a on first gate dielectric layer 140na, forms the higher-pressure region mask 160b, is covered with forming described second
Film.
Wherein, second mask layer is used to form the higher-pressure region mask 160b, to form second mask.
Specifically, in the step of forming the second mask layer, second mask layer is bottom anti-reflection layer, can pass through painting
Cloth technique is formed.
The first graph layer 160c is used to be patterned second mask layer, is covered so as to form second
Film.Specifically, in the present embodiment, the first graph layer 160c is photoresist layer, can pass through coating process and photoetching process
Formed.In other embodiments of the invention, the first graph layer 160c can also be the mask that multiple masking process is formed.
The step of removing the second mask layer on the first gate dielectric layer 140na is used to expose first grid Jie
Original material layer 160a on matter layer 140na, forms the higher-pressure region mask 160b, artistic face is provided for subsequent technique.
Specifically, the step of removing the second mask layer on the first gate dielectric layer 140na includes：Pass through dry method
The mode of etching removes the second mask layer on the first gate dielectric layer 140na.Due to first gate dielectric layer
140na is upper can effectively to protect first gate dielectric layer formed with original material layer 160a, the original material layer 160a
140na, the first gate dielectric layer 140na is avoided to be damaged by dry etch process.
It should be noted that in the present embodiment, the substrate also includes the 3rd region 100p, the 3rd gate dielectric layer
Original material layer 160a on 140p is subsequently used for forming the work-function layer of the 3rd region 100p transistors.
So in the step of forming the second mask, second mask is also located on the 3rd gate dielectric layer 140p,
That is the higher-pressure region mask 160b is also located on the 3rd gate dielectric layer 140p, for protecting the 3rd gate medium
Original material layer 160a on layer 140p.
With continued reference to Figure 11, using second mask as mask, the initial material on the first gate dielectric layer 140na is removed
Bed of material 160a, expose the first gate dielectric layer 140na.
The present embodiment, using the higher-pressure region mask 160b as mask, the first grid is removed by way of wet etching
Original material layer 160a on dielectric layer 140na, expose the first gate dielectric layer 140na.
The way of the original material layer 160a is removed using wet-etching technology, it is described initial that removal can be effectively reduced
Influence of the material layer 160a techniques to the first gate dielectric layer 140na, reduce the first gate dielectric layer 140na and sustain damage
Possibility.
Because the material of the original material layer 160a is titanium nitride, so being removed by way of wet etching described first
In the step of beginning material layer 160a, etching solution NH4OH、H2O2With the mixed solution (SC1 solution) or NH of water4、H2O2With
The mixed solution or HCl, H of water2O2With the mixed solution (SC2 solution) of water.
Specifically, in the present embodiment, in the step of removing the original material layer 160a, etching solution HCl, H2O2With
The mixed solution of water, wherein, HCl, H2O2Mass percent ratio with water is 1:3:200 to 3:3:In the range of 200, etching temperature
Degree is in the range of 20 DEG C to 80 DEG C.
In other embodiments of the invention, the step of removing the original material layer, can also use NH4OH、H2O2With water
Mixed solution or NH4、H2O2With the mixed solution of water.Wherein, NH4OH、H2O2Mixed solution with water is SC1 solution, etching
Temperature is in the range of 20 DEG C to 80 DEG C；NH4、H2O2With NH in the mixed solution of water4、H2O2Mass percent ratio with water is 1:
200:1000 to 5:200:In the range of 1000.
It should be noted that because the 3rd gate dielectric layer 140p also has the second mask, so the 3rd grid are situated between
Original material layer 160a on matter layer 140p is retained, and is not affected by the influence of etching technics.
With reference to figure 12, remove on the first gate dielectric layer 140na after original material layer 160a, remove described second and cover
Film, expose the original material layer 160a on the second gate dielectric layer 140nb, form sacrifice layer 160.
The step of removing second mask is for exposing the original material layer on the second gate dielectric layer 140na
160a, to form sacrifice layer 160, so as to provide operation surface for subsequent technique.
In the present embodiment, second mask is formed by bottom anti-reflection layer, so removing the step of second mask
In rapid, second mask is removed by way of ashing.Specifically, the higher-pressure region mask is removed by way of ashing
160b, to expose the sacrifice layer 160.
The way of second mask is removed by the way of ashing, can avoid remove technique to expose described first
Gate dielectric layer 140na influence, reduce the impaired possibility of the first gate dielectric layer 140na.
It should be noted that the higher-pressure region mask 160 is also located on the 3rd gate dielectric layer 140p, so passing through ashing side
The step of formula removal higher-pressure region mask 160, also exposes the original material layer 160a on the 3rd gate dielectric layer 140p.
With continued reference to Figure 12, first material layer is formed on the first gate dielectric layer 140na and the sacrifice layer 160
161。
The first material layer 161 is used to protect the second gate dielectric layer 140nb in Subsequent semiconductor technique.This reality
Apply in example, the first material layer 161 on the second gate dielectric layer 140nb is being subsequently formed together with the sacrifice layer 160
During one mask, influence of the etching technics to the second gate dielectric layer 140nb is reduced, reduces by second gate dielectric layer
Possibility impaired 140nb.
In addition, the first material layer 161 on the first gate dielectric layer 140na is additionally operable to form the first area
100na substrates form the work-function layer of transistor.This way is advantageous in that, without increasing processing step, you can realizes
Lifting and the first area 100na substrates to the second gate dielectric layer 140nb protective capabilities form transistor work(
The formation of function layer, be advantageous to simplify processing step, reduce process costs.
In the present embodiment, the first area 100na substrates are used to form N-type transistor, so the first material layer
161 material is titanium nitride, can be formed by modes such as chemical vapor deposition, physical vapour deposition (PVD) or alds.
It should be noted that if the thickness of the first material layer 161 is too small, guarantor can not be played in subsequent technique
The effect of the second gate dielectric layer 140nb is protected, and formed first area 100nb substrates can be influenceed and form transistor
The formation of work-function layer；If the thickness of the first material layer 161 is too big, waste of material is easily caused, increase technique is difficult
Degree.In the present embodiment, the thickness of the first material layer 161 existsArriveIn the range of.
It should also be noted that, during forming the first material layer 161, on the 3rd gate dielectric layer 140p
Original material layer 160a is also exposed, so in the step of forming first material layer 161, the first material layer 161 is also
On the 3rd gate dielectric layer 140p.
With reference to figure 13 and Figure 14, the first mask 170 formed in the first material layer 161, first mask
170 expose the first material layer 161 on the second gate dielectric layer 140nb.
First mask 170 is used to protect the first area 100na in semiconductor processing, avoids the first grid
First material layer 161 on dielectric layer 140na is impacted.In the present embodiment, first mask 170 is used to subsequently remove institute
State on the gate dielectric layer 140nb of sacrifice layer 160 and second during first material layer 161, protect the first gate dielectric layer 140na
The upper first material layer 161.
Specifically, the step of forming the first mask 170 includes：
As described in Figure 13, the first mask layer 170a is formed in the first material layer 161.
The first mask layer 170a is used to form first mask.
In the present embodiment, the substrate includes first area 100na, second area 100nb and the 3rd region 100p, institute
The first gate dielectric layer 140na, the second gate dielectric layer 140nb and the 3rd grid are located at the first mask layer 170p
On dielectric layer 140p.
Specifically, in the step of forming the first mask layer 170a, first mask layer 170 is bottom
Anti-reflecting layer, it can be formed by coating process.
Formed after the first mask layer 170a, second graph is formed on the first mask layer 170a
Layer 170b, the second graph layer 170b expose the first mask layer 170a on the second gate dielectric layer 140nb.
The second graph layer 170b is used to be patterned the first mask layer 170a.The second graph
Layer 170b exposes the first mask layer 170a on the second gate dielectric layer 140nb, for subsequently to expose described second
The technique of first material layer 161 provides operation surface on gate dielectric layer 140nb.
In the present embodiment, the second graph layer 170b is photoresist layer, can pass through coating process and photoetching process shape
Into.In other embodiments of the invention, the second graph layer 170b can also be the mask that multiple masking process is formed.
It should be noted that the second graph layer 170b is also located at the first mask on the 3rd gate dielectric layer 140p
On material layer 170a.
With reference to figure 14, using the second graph layer 170b as mask, first on the second gate dielectric layer 140nb is removed
Mask layer 170a (as shown in figure 13), expose the first material layer 161 on the second gate dielectric layer 140nb, it is remaining
The first mask layer 170a forms first mask 170.
The step of removing the first mask layer 170a on the second gate dielectric layer 140nb is used to remove institute to be follow-up
The first material layer 161 stated on sacrifice layer 161 and the second gate dielectric layer 140nb provides artistic face.
In the present embodiment, the first mask layer 170a is bottom anti-reflection layer, is situated between so removing the second gate
The step of the first mask layer 170a on matter layer 140nb, includes：Using the second graph layer 170b as mask, pass through dry method
The mode of etching removes the first mask layer 170a on the second gate dielectric layer 140nb, exposes second gate medium
First material layer 161 on layer 140nb.
Due to having sacrifice layer 160 and first material layer 161 on the second gate dielectric layer 140nb, and with only having
The prior art of first material layer 161 is compared, and the thickness of the sacrifice layer 160 and the first material layer 161 is larger, protects energy
Power is stronger, can effectively reduce the impaired possibility of the second gate dielectric layer 140nb, reduce second gate dielectric layer
The appearance of 140nb damaged phenomenons, is advantageous to improve the quality of the second gate dielectric layer 140nb, and raising forms semiconductor junction
The performance of structure.
Specifically, the first mask layer on the second gate dielectric layer 140nb is removed by way of dry etching
In the step of 170a, technological parameter includes：Etching gas are CH4、H2And N2；Etching gas flow is CH4Flow exist
In the range of 5sccm to 50sccm, H2Flow in the range of 100sccm to 800sccm, N2Flow in 20sccm to 200sccm
In the range of；Pressure is 1mTorr to 150mTorr；Power is 100W to 200W；It is biased in the range of 10V to 300V；Technological temperature
In the range of 20 DEG C to 90 DEG C；Time is in the range of 30s to 1000s.
It should be noted that first on the 3rd gate dielectric layer 140p is also located at due to the second graph layer 170b
On mask layer 170a, so in the step of forming the first mask 170, first mask 170 is also located at the 3rd grid
On dielectric layer 140p, to protect the first material layer 161 and original material layer 160a on the 3rd gate dielectric layer 140p.
It is mask with first mask 170 with reference to figure 15, removes the first material on the second gate dielectric layer 140nb
The bed of material 161 (as shown in figure 14) and sacrifice layer 160 (as shown in figure 14), expose the second gate dielectric layer 140nb.
The step of removing the first material layer 161 and the sacrifice layer 160 on the second gate dielectric layer 140nb is used for
Subsequent technique provides artistic face.
Specifically, the step of removing first material layer 161 and sacrifice layer 160 on the second gate dielectric layer 140nb is wrapped
Include：The first material layer 161 and sacrifice layer 160 on the second gate dielectric layer 140nb are removed by way of wet etching.
The first material layer 161 and sacrifice layer on the second gate dielectric layer 140nb are removed by the way of wet etching
160 way, the influence for removing technique to the second gate dielectric layer 140nb can be effectively reduced, reduces the second gate dielectric layer 140nb
Impaired possibility.
In the present embodiment, because the material of the first material layer 161 and the sacrifice layer 160 is titanium nitride, so logical
Cross the step of mode of wet etching removes first material layer 161 and sacrifice layer 160 on the second gate dielectric layer 140nb
In, etching solution NH4OH、H2O2With the mixed solution (SC1 solution) or NH of water4、H2O2With the mixed solution of water or
HCl、H2O2With the mixed solution (SC2 solution) of water.
Specifically, in the present embodiment, in the step of removing the first material layer 161 and the sacrifice layer 160, etching is molten
Liquid is HCl, H2O2With the mixed solution of water, wherein, HCl, H2O2Mass percent ratio with water is 1:3:200 to 3:3:200
In the range of, etching temperature is in the range of 20 DEG C to 80 DEG C.
In other embodiments of the invention, the step of removing the first material layer and the sacrifice layer 160, can also use
NH4OH、H2O2With the mixed solution or NH of water4、H2O2With the mixed solution of water.Wherein, NH4OH、H2O2With the mixed solution of water
For SC1 solution, etching temperature is in the range of 20 DEG C to 80 DEG C；NH4、H2O2With NH in the mixed solution of water4、H2O2With the quality of water
Percent ratio is 1:200:1000 to 5:200:In the range of 1000.
It should be noted that because first mask 170 is also located on the 3rd gate dielectric layer 140p, so described
Original material layer 160a and the first material layer 161 on 3rd gate dielectric layer 140p are retained, and do not receive etching technics
Influence.
With reference to figure 16, after exposing the second gate dielectric layer 140nb, first mask 170 is removed (such as Figure 15 institutes
Show), expose the first material layer 161 on the first gate dielectric layer 140na.
The step of removing the first mask 170 is used to provide artistic face to be subsequently formed second material layer.
In the present embodiment, first mask 170 is formed by bottom anti-reflection layer, so removing first mask 170
The step of include：First mask 170 is removed by way of ashing.First mask is removed by the way of ashing
170 way, it can avoid removing technique to the second gate dielectric layer 140nb exposed influence, reduce by the second gate medium
Possibility impaired layer 140nb.
It should be noted that because first mask 170 is also located on the 3rd gate dielectric layer 140p, so passing through
The mode of ashing removes the step of the first mask 170 and also exposes first material layer on the 3rd gate dielectric layer 140p
161。
With continued reference to Figure 16, first material layer 161 and second gate dielectric layer in the first gate dielectric layer 140na
Second material layer 171 is formed on 140nb.
The second material layer 171 is used to form the work-function layer that the second area 100nb forms transistor, also uses
The work-function layer of transistor is formed in the composition first area 100na.
So while the first area 100na substrates and the second area substrate 100nb substrates are used to form N-type crystalline substance
Body pipe, so the material of the second material layer is titanium nitride, chemical vapor deposition, physical vapour deposition (PVD) or original can be passed through
The film deposition techniques such as sublayer deposition are formed.
It should be noted that because the step of removing the first mask 170, also exposes the 3rd gate dielectric layer
First material layer 161 on 140p, so in the step of forming second material layer 171, the second material layer 171 also position
In on 140p, transistor work function layer is formed to form the 3rd region 100p substrates on the 3rd gate dielectric layer.
In the present embodiment, the threshold voltage of transistor, second material are formed according to the second area 100nb substrates
The thickness of the bed of material 171 existsArriveIn the range of.
It should be noted that the work-function layer that the second area 100nb substrates form transistor includes described second
Second material layer 171 on dielectric layer 140nb；The work-function layer that the first area 100na substrates form transistor includes
First material layer 161 and second material layer 171 on first gate dielectric layer 140na；3rd region 100p substrates institute shape
Into transistor work-function layer include the 3rd gate dielectric layer 140p on original material layer 160a, the first material layer 161 with
And the second material layer 171.
So the thickness of the second material layer 171 forms the threshold of transistor according to the second area 100nb substrates
Threshold voltage and determine；The thickness of the first material layer 161 forms the threshold of transistor according to the first area 100na substrates
Threshold voltage and the thickness of the second material layer 171 determine；The thickness of the original material floor 160a is according to the 3rd area
Domain 100p substrates form the threshold voltage of transistor and the thickness of the first material layer 161, the second material layer 171
Thickness determine.
In the present embodiment, the substrate of the first area 100na and the second area 100nb substrate are used to form N
Transistor npn npn, after second material layer 171 is formed, the forming method also includes：Titanium is formed in the second material layer 171
Aluminium lamination, the work-function layer of transistor and the second area 100nb substrates institute are formed to form first area 100na substrates
Form the work-function layer of transistor.
The forming method of the titanium aluminium lamination is same as the prior art, and the present invention will not be repeated here.
To sum up, technical solution of the present invention, after gate dielectric layer is formed, sacrifice layer is formed on the second gate dielectric layer, sacrificial
First material layer is formed on domestic animal layer；During the first mask is formed, protected with the sacrifice layer and the first material layer
Second gate dielectric layer.Compared with only leaning on the prior art that the first material layer protects second gate dielectric layer, this hair
In bright technical scheme, the gross thickness of the first material layer and the sacrifice layer is larger, the protection to second gate dielectric layer
Ability is stronger, can effectively reduce by the second gate dielectric layer and is damaged in the first mask forming process, is advantageous to improve gate medium
The performance of layer, improve the performance for forming semiconductor structure.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is formed, the substrate includes being used for first area and the second area for forming transistor, and the first area is brilliant The threshold voltage of body pipe is more than the threshold voltage of second area transistor；Pseudo- grid structure is formed on the substrate；Dielectric layer is formed in the adjacent pseudo- interstructural substrate of grid；Remove dummy gate structure and opening is formed in the dielectric layer；Gate dielectric layer is formed in the open bottom, the gate dielectric layer positioned at the first area dielectric layer inner opening bottom is the One gate dielectric layer, the gate dielectric layer positioned at the second area dielectric layer inner opening bottom are the second gate dielectric layer；Sacrifice layer is formed on second gate dielectric layer；First material layer is formed on first gate dielectric layer and sacrifice layer；Form the first mask in the first material layer, first mask exposes the on second gate dielectric layer One material layer；Using first mask as mask, first material layer and sacrifice layer on second gate dielectric layer are removed, is exposed described Second gate dielectric layer；First mask is removed, exposes the first material layer on first gate dielectric layer；Second material layer is formed in the first material layer of first gate dielectric layer and second gate dielectric layer.
- 2. forming method as claimed in claim 1, it is characterised in that in the step of forming sacrifice layer, the thickness of the sacrifice layer Degree existsArriveIn the range of.
- 3. forming method as claimed in claim 1, it is characterised in that the step of forming the sacrifice layer includes：Original material layer is formed on the gate dielectric layer；The original material layer on first gate dielectric layer is removed, exposes first gate dielectric layer, is situated between positioned at the second gate Original material layer on matter layer is as the sacrifice layer.
- 4. forming method as claimed in claim 3, it is characterised in that remove the original material layer on first gate dielectric layer The step of include：The second mask is formed on the original material layer, second mask exposes the initial material on first gate dielectric layer The bed of material；Using second mask as mask, the original material layer on first gate dielectric layer is removed, exposes the first grid and is situated between Matter layer；Second mask is removed, exposes the original material layer on second gate dielectric layer, forms sacrifice layer.
- 5. forming method as claimed in claim 4, it is characterised in that the step of forming second mask includes：The second mask layer is formed on the original material layer；The first graph layer is formed on second mask layer, first graph layer exposes on first gate dielectric layer The second mask layer；Using first graph layer as mask, the second mask layer on first gate dielectric layer is removed, exposes described the Original material layer on one gate dielectric layer, form second mask.
- 6. forming method as claimed in claim 5, it is characterised in that in the step of forming the second mask layer, described the Two mask layers are bottom anti-reflection layer.
- 7. forming method as claimed in claim 5, it is characterised in that remove the second mask material on first gate dielectric layer The step of bed of material, includes：The second mask layer on first gate dielectric layer is removed by way of dry etching.
- 8. the forming method as described in claim 3 or 4, it is characterised in that remove the initial material on first gate dielectric layer The step of bed of material, includes：The original material layer on first gate dielectric layer is removed by way of wet etching.
- 9. forming method as claimed in claim 4, it is characterised in that in the step of removing second mask, pass through ashing Mode remove second mask.
- 10. forming method as claimed in claim 3, it is characterised in that in the step of forming substrate, the substrate also includes the Three regions；In the step of forming gate dielectric layer, the gate dielectric layer positioned at the 3rd Region Medium layer inner opening bottom is situated between for the 3rd grid Matter layer；In the step of forming original material layer, the original material layer is also located on the 3rd gate dielectric layer；In the step of forming the second mask, second mask is also located on the 3rd gate dielectric layer；In the step of forming the first material layer, the first material layer is also located on the 3rd gate dielectric layer；In the step of forming the first mask, first mask is also located on the 3rd gate dielectric layer；In the step of forming the second material layer, the second material layer is also located on the 3rd gate dielectric layer.
- 11. forming method as claimed in claim 10, it is characterised in that in the step of forming substrate, the 3rd region base Bottom is used to form P-type transistor；In the step of forming the original material layer, the original material layer is titanium nitride.
- 12. forming method as claimed in claim 1, it is characterised in that the step of forming first mask includes：The first mask layer is formed in the first material layer；Second graph layer is formed on first mask layer, the second graph layer exposes on second gate dielectric layer The first mask layer；Using the second graph layer as mask, the first mask layer on second gate dielectric layer is removed, exposes described the First material layer on two gate dielectric layers, form first mask.
- 13. forming method as claimed in claim 12, it is characterised in that in the step of forming first mask layer, First mask layer is bottom anti-reflection layer.
- 14. forming method as claimed in claim 12, it is characterised in that remove the first mask on second gate dielectric layer The step of material layer, includes：The first mask layer on second gate dielectric layer is removed by way of dry etching.
- 15. forming method as claimed in claim 1, it is characterised in that remove the first material on second gate dielectric layer The step of layer and sacrifice layer, includes：First material layer on second gate dielectric layer and sacrificial is removed by way of wet etching Domestic animal layer.
- 16. forming method as claimed in claim 1, it is characterised in that the step of removing first mask includes：Pass through ash The mode of change removes first mask.
- 17. forming method as claimed in claim 1, it is characterised in that in the step of forming substrate, the first area and institute Second area is stated to be used to form N-type transistor；The material of the first material layer and the second material layer is titanium nitride.
- 18. forming method as claimed in claim 1, it is characterised in that in the step of forming the first material layer, described The thickness of one material layer existsArriveIn the range of.
- 19. forming method as claimed in claim 1, it is characterised in that the step of forming gate dielectric layer includes：Formation includes height The gate dielectric layer of K dielectric layer.
- 20. forming method as claimed in claim 1, it is characterised in that the semiconductor structure is fin formula field effect transistor；The step of forming substrate includes：Initial substrate is provided；The initial substrate is etched, forms substrate and discrete fin on the substrate；The step of forming dummy gate structure includes：Form the pseudo- grid structure on the fin, dummy gate structure across Part surface at the top of the fin and the covering fin with side wall.
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| US6563178B2 (en) * | 2000-03-29 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the device |
| CN103390583A (en) * | 2012-05-08 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated device and manufacturing method thereof |
| CN103681324A (en) * | 2012-08-30 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for MOS (Metal Oxide Semiconductor) transistor |
| CN103715258A (en) * | 2012-09-28 | 2014-04-09 | 台湾积体电路制造股份有限公司 | Source/drain stack stressor for semiconductor device |
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| US6723609B2 (en) * | 2002-02-04 | 2004-04-20 | United Microelectronics Corp. | Method of preventing leakage current of a metal-oxide semiconductor transistor |
| US6939768B2 (en) * | 2003-04-01 | 2005-09-06 | Macronix International Co., Ltd. | Method of forming self-aligned contacts |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563178B2 (en) * | 2000-03-29 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the device |
| CN103390583A (en) * | 2012-05-08 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated device and manufacturing method thereof |
| CN103681324A (en) * | 2012-08-30 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for MOS (Metal Oxide Semiconductor) transistor |
| CN103715258A (en) * | 2012-09-28 | 2014-04-09 | 台湾积体电路制造股份有限公司 | Source/drain stack stressor for semiconductor device |
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