CN107799136A - SONOS reads sequence circuit - Google Patents
SONOS reads sequence circuit Download PDFInfo
- Publication number
- CN107799136A CN107799136A CN201711163472.9A CN201711163472A CN107799136A CN 107799136 A CN107799136 A CN 107799136A CN 201711163472 A CN201711163472 A CN 201711163472A CN 107799136 A CN107799136 A CN 107799136A
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- CN
- China
- Prior art keywords
- pmos
- nmos
- sonos
- sequence circuit
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Landscapes
- Dram (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a kind of SONOS to read sequence circuit, comprising：First and second PMOS, first and second NMOS tube, and an electric capacity；Wherein the first PMOS connects with the first NMOS, and the 2nd PMOS connects with the 2nd NMOS；First PMOS and the 2nd PMOS source electrode connects power supply；First PMOS and the first NMOS gate connected in parallel is followed by inputting, and the first PMOS and the first NMOS series connection node connect the 2nd PMOS and the 2nd NMOS grid；2nd PMOS and the 2nd NMOS series connection node is output port, the 2nd NMOS source ground；Electric capacity one end ground connection, another termination the 2nd PMOS and the 2nd NMOS grid；The source electrode of first NMOS is grounded by a bypass current source.The present invention is using the by-pass current source with Positive and Negative Coefficient Temperature, the time sequential that precharge time and generation sense amplifier to the unit of selected reading compare data " 0 " or " 1 " is redistributed, and ensures that read sequence circuit also stably can effectively read data at low temperature.
Description
Technical field
The present invention relates to semiconductor applications, the SONOS for particularly relating to a kind of nonvolatile storage reads sequence circuit.
Background technology
NVM（Non-volatile Memory）, nonvolatile storage, have it is non-volatile, by byte access, storage density
The characteristics of high and low energy consumption, readwrite performance are close to DRAM.Electronic equipment can rapidly access the content of the memory storage space
（In most cases this kind equipment is all with byte mode to access these contents, and can also preserve them after power down）.It
Without regularly refreshing memory content.This includes the read-only storage of form of ownership（ROM）, seem programmable read only memory
（PROM）, EPROM（EPROM）, electricallyerasable ROM (EEROM)（EEPROM）And flash memory.It also includes
Battery powered random access memory（RAM）.
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-oxide-nitride-silica-silicon,
Also known as silicon oxide nitride oxide silicon) device, the memory cell of existing SONOS devices is generally by a SONOS memory transistor
(referred to as storage tube) and a high pressure selection transistor（Referred to as selecting pipe）Composition.Wherein storage tube is used for data storage,
Selecting pipe is used for completing the selection of data address.
It is NVM SONOS units cell reading timing diagram as shown in Figure 1, wherein：
Tcl:The selected address settling time read（setup time）；
Tpc:The selected cell precharge times read；
Tsa:Sense amplifier compares the time of data " 0 " or " 1 "；
Tdy:Sense amplifier latches time of the output correctly required for " 0 "/" 1 "；
Taa:One complete read cycle.
Wherein the Tpc times are longer, and reading " 0 " can be deteriorated；The Tsa times are elongated, read " 0 " or read " 1 " can be beneficial；
SONOS cell can read " 0 " and be deteriorated as temperature reduces in itself.
Generally speaking, in existing circuit sequence, above-mentioned 4 sections of sequential can be simultaneously bigger than normal with temperature reduction, due to low
Lower reading " 0 " cell of temperature itself is on the weak side, and the elongated of Tpc times is more detrimental to read " 0 ".
The content of the invention
The technical problems to be solved by the invention are that providing a kind of SONOS reads sequence circuit, has temperature compensation function,
Make reading circuit work more stable.
To solve the above problems, SONOS of the present invention reads sequence circuit, comprising：
First and second PMOS, first and second NMOS tube, and an electric capacity；
Wherein the first PMOS connects with the first NMOS, and the 2nd PMOS connects with the 2nd NMOS；
First PMOS and the 2nd PMOS source electrode connects power supply；
First PMOS and the first NMOS gate connected in parallel is followed by inputting, and the first PMOS and the first NMOS series connection node connect second
PMOS and the 2nd NMOS grid；
2nd PMOS and the 2nd NMOS series connection node is output port, the 2nd NMOS source ground；
Electric capacity one end ground connection, another termination the 2nd PMOS and the 2nd NMOS grid；
The source electrode of first NMOS is grounded by a bypass current source；
Above-mentioned reading sequential electric current produces four kinds of sequential at work：The settling time Tcl of the selected address read, it is selected what is read
Precharge time Tpc, the sense amplifier of unit compare data " 0 " or the time Tsa of " 1 " and a complete read cycle
Taa。
Further, the by-pass current source can produce the by-pass current of negative temperature coefficient or the bypass of positive temperature coefficient
Electric current.
Further, when producing the precharge time Tpc of the selected unit read, using the side with negative temperature coefficient
Road current source；When producing sense amplifier and comparing the time Tsa of data " 0 " or " 1 " using the by-pass current of positive temperature coefficient
Source.
Further, data are compared with sense amplifier is produced in the precharge time Tpc for producing the selected unit read
The circuit of the time Tsa sequential of " 0 " or " 1 ", by by-pass current source to capacitor charge and discharge, to realize that input signal rising edge arrives
The delay of output signal rising edge.
Further, compensated by the by-pass current source of Positive and Negative Coefficient Temperature to reading sequential, to the selected list read
The precharge time Tpc of member compares data " 0 " with generation sense amplifier or the time Tsa sequential of " 1 " is redistributed, will
The precharge time Tpc of the selected unit read is designed as declining and reducing with temperature, while sense amplifier compares data " 0 "
Or the time Tsa of " 1 " increases with temperature and becomes big.
Further, the electric capacity is conventional capacitance, or is replaced with metal-oxide-semiconductor.
SONOS of the present invention reads sequence circuit, when producing the precharge time Tpc of the selected unit read, adopts
With the by-pass current source with negative temperature coefficient；Used when producing sense amplifier and comparing the time Tsa of data " 0 " or " 1 "
The by-pass current source of positive temperature coefficient, precharge time Tpc and generation sense amplifier to the selected unit read relatively are counted
Redistributed according to the time Tsa sequential of " 0 " or " 1 ", ensure that read sequence circuit also stably can effectively read number at low temperature
According to.
Brief description of the drawings
Fig. 1 is the reading timing diagram that existing SONOS reads sequence circuit.
Fig. 2 is the structural representation that SONOS of the present invention reads sequence circuit.
Fig. 3 is the reading timing diagram after SONOS of the present invention reads sequence circuit compensation.
Embodiment
Read at low temperature because existing SONOS reads sequence circuit " Unit 0 " itself is on the weak side, and the elongated of Tpc times is even more
It is unfavorable for reading " 0 ", therefore the present invention is proposed under Taa time fixing situations, is redistributed using temperature compensation under low temperature
Tpc and Tsa, Tpc is designed as declining with temperature and reduced, while Tsa increases with temperature and becomes big.
Based on above-mentioned technical thought, SONOS of the present invention reads sequence circuit, comprising：
First and second PMOS, first and second NMOS tube, and an electric capacity；
Wherein the first PMOS connects with the first NMOS, and the 2nd PMOS connects with the 2nd NMOS；
First PMOS and the 2nd PMOS source electrode connects power supply；
First PMOS and the first NMOS gate connected in parallel is followed by inputting, and the first PMOS and the first NMOS series connection node connect second
PMOS and the 2nd NMOS grid；
2nd PMOS and the 2nd NMOS series connection node is output port, the 2nd NMOS source ground；
Electric capacity one end ground connection, another termination the 2nd PMOS and the 2nd NMOS grid；
The source electrode of first NMOS is grounded by a bypass current source.
The by-pass current source can produce the by-pass current of negative temperature coefficient or the by-pass current of positive temperature coefficient.Producing
During the precharge time Tpc of the raw selected unit read, using the by-pass current source with negative temperature coefficient；Producing sensitive put
Using the by-pass current source of positive temperature coefficient when big device compares the time Tsa of data " 0 " or " 1 ".
Compare data " 0 " or " 1 " producing the precharge time Tpc of the selected unit read and producing sense amplifier
The circuit of time Tsa sequential, by by-pass current source to capacitor charge and discharge, to realize input signal rising edge to output signal
Rise the delay on edge.
Compensated by the by-pass current source of Positive and Negative Coefficient Temperature to reading sequential, the precharge to the selected unit read
Time Tpc compares data " 0 " with generation sense amplifier or the time Tsa sequential of " 1 " is redistributed, by selected reading
The precharge time Tpc of unit is designed as declining and reducing with temperature, at the same sense amplifier compare data " 0 " or " 1 " when
Between Tsa increase with temperature and become big.Ensure that read sequence circuit also stably can effectively read data at low temperature.
The preferred embodiments of the present invention are these are only, are not intended to limit the present invention.Come for those skilled in the art
Say, the present invention there can be various modifications and variations.Within the spirit and principles of the invention, it is any modification for being made, equivalent
Replace, improve etc., it should be included in the scope of the protection.
Claims (6)
1. a kind of SONOS reads sequence circuit, it is characterised in that includes：
First and second PMOS, first and second NMOS tube, and an electric capacity；
Wherein the first PMOS connects with the first NMOS, and the 2nd PMOS connects with the 2nd NMOS；
First PMOS and the 2nd PMOS source electrode connects power supply；
First PMOS and the first NMOS gate connected in parallel is followed by inputting, and the first PMOS and the first NMOS series connection node connect second
PMOS and the 2nd NMOS grid；
2nd PMOS and the 2nd NMOS series connection node is output port, the 2nd NMOS source ground；
Electric capacity one end ground connection, another termination the 2nd PMOS and the 2nd NMOS grid；
The source electrode of first NMOS is grounded by a bypass current source；
Above-mentioned reading sequential electric current produces four kinds of sequential at work：The settling time Tcl of the selected address read, it is selected what is read
Precharge time Tpc, the sense amplifier of unit compare data " 0 " or the time Tsa of " 1 " and a complete read cycle
Taa。
2. SONOS as claimed in claim 1 reads sequence circuit, it is characterised in that：The by-pass current source can produce negative temperature
The by-pass current of coefficient or the by-pass current of positive temperature coefficient.
3. SONOS as claimed in claim 1 or 2 reads sequence circuit, it is characterised in that：Producing the pre- of the selected unit read
During charging interval Tpc, using the by-pass current source with negative temperature coefficient；Compare data " 0 " or " 1 " producing sense amplifier
Time Tsa when using positive temperature coefficient by-pass current source.
4. SONOS as claimed in claim 1 reads sequence circuit, it is characterised in that：Producing the preliminary filling of the selected unit read
Electric time Tpc and generation sense amplifier compare the circuit of data " 0 " or the time Tsa sequential of " 1 ", pass through by-pass current source pair
Capacitor charge and discharge, to realize delay of the input signal rising edge to output signal rising edge.
5. SONOS as claimed in claim 3 reads sequence circuit, it is characterised in that：Pass through the by-pass current of Positive and Negative Coefficient Temperature
Source compensates to reading sequential, compares data " 0 " to the precharge time Tpc and generation sense amplifier of the selected unit read
Or the time Tsa sequential of " 1 " is redistributed, and the precharge time Tpc of the unit of selected reading is designed as at a temperature of
Drop and reduce, while sense amplifier compares data " 0 " or the time Tsa of " 1 " and increases with temperature and become big.
6. SONOS as claimed in claim 1 reads sequence circuit, it is characterised in that：The electric capacity is conventional capacitance, or is used
Metal-oxide-semiconductor replaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711163472.9A CN107799136B (en) | 2017-11-21 | 2017-11-21 | SONOS read sequence circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711163472.9A CN107799136B (en) | 2017-11-21 | 2017-11-21 | SONOS read sequence circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107799136A true CN107799136A (en) | 2018-03-13 |
| CN107799136B CN107799136B (en) | 2021-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711163472.9A Active CN107799136B (en) | 2017-11-21 | 2017-11-21 | SONOS read sequence circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030193360A1 (en) * | 2002-04-12 | 2003-10-16 | Doo-Seop Lee | Integrated circuit devices that provide constant time delays irrespective of temperature variation |
| CN101630532A (en) * | 2008-07-17 | 2010-01-20 | 上海华虹Nec电子有限公司 | Sensitive amplifier used for electrically erasable read only memory and realization method thereof |
| CN102426851A (en) * | 2011-11-25 | 2012-04-25 | 中国科学院微电子研究所 | Read Timing Generation Circuit |
| CN103078607A (en) * | 2011-10-25 | 2013-05-01 | 旺宏电子股份有限公司 | Clock integrated circuit |
| CN104348457A (en) * | 2013-08-05 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Flash read control circuit |
-
2017
- 2017-11-21 CN CN201711163472.9A patent/CN107799136B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030193360A1 (en) * | 2002-04-12 | 2003-10-16 | Doo-Seop Lee | Integrated circuit devices that provide constant time delays irrespective of temperature variation |
| CN101630532A (en) * | 2008-07-17 | 2010-01-20 | 上海华虹Nec电子有限公司 | Sensitive amplifier used for electrically erasable read only memory and realization method thereof |
| CN103078607A (en) * | 2011-10-25 | 2013-05-01 | 旺宏电子股份有限公司 | Clock integrated circuit |
| CN102426851A (en) * | 2011-11-25 | 2012-04-25 | 中国科学院微电子研究所 | Read Timing Generation Circuit |
| CN104348457A (en) * | 2013-08-05 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Flash read control circuit |
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| Publication number | Publication date |
|---|---|
| CN107799136B (en) | 2021-01-22 |
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