CN103078607A - Clock integrated circuit - Google Patents
Clock integrated circuit Download PDFInfo
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- CN103078607A CN103078607A CN2011103272447A CN201110327244A CN103078607A CN 103078607 A CN103078607 A CN 103078607A CN 2011103272447 A CN2011103272447 A CN 2011103272447A CN 201110327244 A CN201110327244 A CN 201110327244A CN 103078607 A CN103078607 A CN 103078607A
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Abstract
The invention discloses a clock integrated circuit. For example, a delay circuit of a lock circuit of the integrated circuit can bear the operation under the condition of temperature change. The clock integrated circuit is provided with a current generator correlated to the temperature and has an adjustable temperature coefficient within an adjustable temperature coefficient range at a specific current value. In addition, the clock circuit of the clock integrated circuit is operated under multiple versions of current for controlling the charging and/or discharging speed to be switched between two reference signals in a time sequence circuit.
Description
Technical field
The invention relates to the integrated circuit with clock circuit, its variations such as temperature and power supply of tolerable.
Background technology
The running meeting of the clock circuit of integrated circuit has variation with factors such as temperature and power supplys.Because these variations can affect the final sequential of output clock signal, the existing multinomial research phase of carrying out can for this problem, in the situation that above-mentioned variation exists, produce more uniform output clock signal.
For example, the clock circuit of integrated circuit is responsible is higher than the voltage of supplying a voltage reference signal that produces with voltage regulator combination of heap of stone by generation.So circuit can consume a large amount of chip area and electric current.
Therefore cause the demand, hope can solve these variation problems, but adopts more uncomplicated structure and less cost.
Summary of the invention
The present invention provides a kind of integrated circuit with delay circuit of generation one signal.This integrated circuit has delay circuit and comprises that sequence circuit, electric current produce block, a plurality of current mirror block and level switching circuit.
This sequential circuit has an output of switching between reference signal.
This electric current generation block has an output control electric current and controls at least (i) discharge rate between those reference signals, and a compensating circuit in the charge rate that (ii) switches between those reference signals provides power supply by a supply voltage.
It produces a plurality of versions that a plurality of these electric currents produce this output control electric current of block, this discharge rate of these a plurality of these sequence circuit different pieces of electric current Version Control and at least one in this charge rate these a plurality of current mirror blocks.
This output of this level switching circuit and this sequence circuit couples, this level switching circuit has an output of this clock signal of the integrated circuit that determines that this has delay circuit, and wherein this output switching output level of this level switching circuit arrives a trigger point of this level switching circuit with this output that responds this sequence circuit.
In one embodiment, this output of the decision of this sequence circuit and this level switching circuit and this clock signal.
In different embodiment, this output current of this electric current generation block comprises at least one in a power supply compensating component and the temperature-compensating composition.
In the embodiment that so has the temperature-compensating composition, it has an adjustable temperature coefficient this temperature-compensating composition.Have among the embodiment of capable of regulating temperature coefficient at some, this capable of regulating temperature coefficient comprise with temperature be directly proportional, inverse ratio or irrelevant at least one.
Have among the embodiment of temperature-compensating composition at some, this temperature-compensating composition has an adjustable temperature coefficient, and this adjustable temperature coefficient comprises and one of temperature correlation voltage composition that it can surpass one times relevance adjustment.
Have among the embodiment of temperature-compensating composition at some, this temperature-compensating composition has an adjustable temperature coefficient, and this adjustable temperature coefficient comprises and a voltage composition of temperature correlation that it can be less than one times relevance adjustment.
Have among the embodiment of power supply compensating component at some, it has an adjustable power supply coefficient this power supply compensating component.Have among the embodiment of capable of regulating power supply coefficient at some, have the scope of a capable of regulating power supply coefficient at this power supply compensating component of a specific current value.Have among the embodiment of capable of regulating power supply coefficient at some, this capable of regulating power supply coefficient comprise with temperature be directly proportional, inverse ratio or irrelevant at least one.
Have among the embodiment of power supply compensating component at some, this power supply compensating component has an adjustable power supply coefficient, and this adjustable power supply coefficient comprises a voltage composition relevant with power supply, and it can surpass one times relevance adjustment.
Have among the embodiment of power supply compensating component at some, this power supply compensating component has an adjustable power supply coefficient, and this adjustable power supply coefficient comprises a voltage composition relevant with power supply, and it can be less than one times relevance adjustment.
In one embodiment, the version of these a plurality of output currents is respectively a ratio of this output current.
In one embodiment, more comprise a latch circuit.This latch circuit receives this output of this level switching circuit and produces this clock signal of this integrated circuit with delay circuit, this latch circuit comprises the logic gate that couples alternately, so that the input of another logic gate that couples alternately in the output of this logic gate that couples alternately and this latch circuit couples in this latch circuit, the different piece that this latch circuit has a plurality of inputs and this sequence circuit couples.
Another object of the present invention provides a kind of method that produces a clock signal from an integrated circuit with delay circuit.The method comprises the following step:
To switch between a plurality of reference signals of being output in of a sequential circuit;
Produce an electric current, it controls (i) discharge rate between those reference signals at least, in the charge rate that (ii) switches between those reference signals one;
Produce a plurality of electric current versions of this electric current, with this discharge rate of controlling at least this sequence circuit different piece and at least one in this charge rate, this discharge rate of these a plurality of these sequence circuit different pieces of electric current Version Control and at least one in this charge rate; And
This output of switching the output level of a level switching circuit and responding this sequence circuit arrives a trigger point of this level switching circuit, and an output of this level switching circuit determines that this has this clock signal of the integrated circuit of delay circuit.
In one embodiment, this output of the decision of this sequence circuit and this level switching circuit and this clock signal.
In different embodiment, this output of this electric current generation block comprises at least one in a reference voltage composition and the temperature-compensating composition.Have among the embodiment of temperature-compensating composition at some, this temperature-compensating composition has an adjustable temperature coefficient.Have among the embodiment of capable of regulating temperature coefficient at some, this temperature-compensating composition has an adjustable temperature coefficient scope when a specific current value.Have among the embodiment of capable of regulating temperature coefficient at some, this capable of regulating temperature coefficient comprise a voltage composition of the temperature correlation that is directly proportional with temperature and a voltage composition of the temperature correlation that is inversely proportional to temperature at least one.
Have among the embodiment of temperature-compensating composition at some, this temperature-compensating composition has an adjustable temperature coefficient, and this adjustable temperature coefficient comprises and a voltage composition of temperature correlation that it can surpass one times relevance adjustment.
Have among the embodiment of temperature-compensating composition at some, this temperature-compensating composition has an adjustable temperature coefficient, and this adjustable temperature coefficient comprises and a voltage composition of temperature correlation that it can be less than one times relevance adjustment.
In one embodiment, the version of these a plurality of output currents is respectively a ratio of this output current.
In one embodiment, comprise that more producing this that have that a bolt-lock receives this level switching circuit has this clock signal of the integrated circuit of delay circuit, this bolt-lock comprises the logic gate that couples alternately, so that the input of another logic gate that couples alternately in the output of this logic gate that couples alternately and this bolt-lock couples in this bolt-lock, the different piece that this bolt-lock has a plurality of inputs and this sequence circuit couples.
A further object of the present invention provides a kind of device that produces a plurality of inhibit signals from an integrated circuit.This integrated circuit comprises an electric current and produces block and a plurality of delay circuit.
This electric current produces block to have an output current and controls at least (i) discharge rate between those reference signals, in the charge rate that (ii) switches between those reference signals one.
These a plurality of delay circuits produce these a plurality of inhibit signals.Each delay circuit in these a plurality of delay circuits comprises delay circuit, a current mirror block and a level switching circuit.This current mirror block produces the version that this electric current produces this output current of block, this discharge rate of this sequence circuit different piece of the Current Control of this version and at least one in this charge rate.This output of this level switching circuit and this sequence circuit couples.This level switching circuit has an output of this inhibit signal that determines this integrated circuit, wherein this output switching output level of this level switching circuit and respond a trigger point of this this level switching circuit of output arrival of this sequence circuit.
One embodiment comprises a single delay circuit.
In one embodiment, this current mirror block produces the version of ratio that this electric current produces this output current of block, and wherein the specific currents size of the version of this ratio of this output current causes the corresponding time of delay in these a plurality of inhibit signals.
In one embodiment, this integrated circuit more comprises the storage stack buffer, produces a size of this output current of block to control this electric current.
In one embodiment, this group memory buffer control is by the time of delay of these a plurality of inhibit signals of these a plurality of delay circuits generations.
In one embodiment, this integrated circuit has a test pattern, and its output is according to a sum total number of the frequency signal counting of this group memory buffer change.
In one embodiment, this integrated circuit has a test pattern, and it changes this group memory buffer to compensate the different technology conditions in technique.
The present invention has disclosed many different embodiment.
The present invention is and Application No. 12/631661,12/631693,12/631705 and 12/834369 relevant.All draw at this and to be reference data.
Description of drawings
The present invention is defined by the claim scope.These and other objects, feature, and embodiment, graphic being described of can in the chapters and sections of following execution mode, arranging in pairs or groups, wherein:
Fig. 1 shows that one has and produces the discharge of control sequence circuit between two reference signals and/or the block schematic diagram of the integrated circuit clock circuit of the multiple version of the electric current of speed.
Fig. 2 shows the circuit diagram of an integrated circuit clock circuit, charging and/or discharge rate that its multiple version that can produce an electric current switches between two reference signals between sequence circuit with control.
Fig. 3 is the schematic diagram of a current generator, and it produces discharge and/or the charge rate that switches between the control sequence circuit reference signal.
Fig. 4 is the schematic diagram of a current mirror block, the discharge of switching between the control sequence circuit reference signal that its generation copies and/or the electric current of charge rate.
To be displaying time discharge and/or the OX of charge rate or the graph of a relation of OY node with electric current according to controlled discharge and/or charge rate Fig. 5.
The graph of a relation of Fig. 6 clock voltage that to be displaying time export with the integrated circuit with delay circuit.
Fig. 7 is presented at different temperatures lower frequency cycle and the graph of a relation of supplying voltage.
Fig. 8 is presented at the graph of a relation of different supply voltage lower frequency cycles and temperature.
Fig. 9 shows the circuit diagram of a temperature-compensated current generator, and it does not have an adjustable temperature coefficient under specified temp in this temperature-compensated current generator.
Figure 10 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) according to first embodiment of the invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 11 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) according to second embodiment of the invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 12 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) according to third embodiment of the invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 13 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) of more detailed the first embodiment according to the present invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 14 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) of more detailed the second embodiment according to the present invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 15 shows the temperature-compensated current of the different circuit settings according to the present invention and the graph of a relation of temperature.
Figure 16 can use the block schematic diagram that the present invention has a memory circuit of improvement integrated circuit clock circuit.
Figure 17 is the calcspar with delay circuit of the time of delay that the reference current by current generator determines.
Figure 18 has the calcspar of sharing the multiple delay circuit of the time of delay that current generator decides by one.
Figure 19 has a calcspar of sharing the multiple delay circuit of the time of delay that current generator decides by one for another kind of.
Figure 20 to Figure 23 shows that collocation is decided the calcspar of the delay circuit of time of delay by a reference current of a current generator.
The input that the different delay circuits from Figure 20 to Figure 23 of Figure 24 to Figure 27 demonstration are corresponding and the sequential chart of output voltage track.
Figure 28 displays temperature compensates the graph of a relation from the circuit power compensating delay time that is produced by different delay blocks.
Figure 29 shows the test flow chart of a test machine, and it can be adjusted automatically has in the integrated circuit single group of time of delay of pruning multiple delay block in the buffer.
Figure 30 shows that a meeting has the single group of calcspar of pruning the test macro of the time of delay of multiple delay block in the buffer in adjustment one integrated circuit automatically.
Figure 31 is presented under the different technology conditions and postpones graph of a relation time of delay that block produces by difference.
Figure 32 shows the circuit diagram of this current generating circuit, the electric current of charging and/or discharge rate between the reference signal of its generation control in having the sequence circuit of pruning circuit.
[main element symbol description]
102 sequence circuits
104 level switching circuits
106 latch circuits
108 feedback signals
110 clock signals
114 have a plurality of charging that control switches in the sequence circuit and/or electric currents of discharge of copying between reference signal
The circuit of the charging of between reference signal, switching in the 116 generation control sequence circuits and/or the electric current of discharge
118 current replication blocks
202A, 202B sequence circuit
204A, 204B negative circuit
206 latch circuits
1600 integrated circuits
1612 memory cell arrays
1614 word line/blocks are chosen decoder and driver
1616 word lines
1618 bit line decoders
1620 bit lines
1622,1626 buses
1624 induction amplifiers and data input structure
1628 Data In-Lines
1632 DOL Data Output Line
1636 bias voltage adjustment supply electric current and voltage source
1634 state machines and clock circuit
Embodiment
Fig. 1 shows that one has and produces the discharge of control sequence circuit between two those reference signals and/or the block schematic diagram of the integrated circuit clock circuit of the multiple version of the electric current of speed.
This integrated circuit with delay circuit is a loop structure normally, has sequence circuit 102, level switching circuit 104 and latch circuit 106.This latch circuit 106 produce one from latch circuit 106 feedback signal to sequence circuit 102, an and clock output signal 110.This sequential circuit 102 switches between two reference signals according to a time constant, for example supply voltage reference signal and a ground connection reference signal.The output meeting of this sequential circuit is increased to the high level reference value from the low level reference value, and/or drops to the low level reference value from the high level reference value.The rising of this sequential circuit output and/or fall off rate are to be determined by the electric current that block 116 produces.The electric current that is produced by block 116 be replicated by current mirror block 118 or equal proportion deliver to a plurality of positions in the sequence circuit 102.
Fig. 2 shows the circuit diagram of an integrated circuit clock circuit, charging and/or discharge rate that its multiple version that can produce an electric current switches between two reference signals between sequence circuit 102 with control.
In illustrative embodiment, wherein capacitor C X or CY couple with a common ground connection.Although do not express all possible variation in graphic, technology of the present invention comprises the sequence circuit that has capacitor C X or CY among all embodiment, wherein sequence circuit can be revised as capacitor C X or CY are coupled with a common ground connection.
In one embodiment, capacitor C X or CY are actually common ground end that a PMOS transistor has opposite end points and inverter and remove and to couple.
In another embodiment, wherein capacitor C X or CY are and a common supply coupling.Although do not express all possible variation in graphic, technology of the present invention comprises the sequence circuit that has capacitor C X or CY among all embodiment, wherein sequence circuit can be revised as and with capacitor C X or CY be and a common supply coupling.
This negative circuit 204A and 204B are by a CTAT power supply or one and the power supply that is inversely proportional to of temperature, and it can reduce along with the increase of temperature, drives.In another embodiment, this negative circuit 204A and 204B are by a PTAT power supply or a power supply that is directly proportional with temperature, and it can increase along with the increase of temperature, drives.In another embodiment, this negative circuit 204A and 204B are driven by a temperature independent power supply of deciding.
This negative circuit 204A and 204B are driven by a CTAP power supply (being that power supply and circuit power are inversely proportional to).In another embodiment, this negative circuit 204A and 204B are driven by a PTAP power supply (being that power supply is directly proportional with circuit power).In another embodiment, this negative circuit 204A and 204B drive with the irrelevant power supply of deciding of circuit power by one.
This inverter power supply is controlled, and compares with the stroke that changes inverter and the output (such as the rise/fall of RC circuit) of therefore detecting this sequential circuit.
This inverter has following advantage compared to the operational amplifier version: the operating voltage VDD that (1) is lower; (2) less circuit size (two metal oxide semiconductor transistors are only arranged inverter and operational amplifier has five or above metal oxide semiconductor transistor); (3) better simply design; (4) lower active electric current (inverter has a current path, and does not need required in an operational amplifier extracurrent mirror); And (5) higher operating rate (inverter has the delay in a stage).
This latch circuit 206 couples alternately, and the output of a logic gate like this and the input of another logic gate couple.One input of one logic gate is directly to couple with the output of another logic gate, another input of this logic gate be directly and the output of another logic gate pass through sequence circuit and level circuit for detecting and couple.
Fig. 3 is the schematic diagram of a current generator, and it produces discharge and/or the charge rate that switches between the control sequence circuit reference signal.
This current generating circuit, or claim the i generator, have two electric currents and produce composition: Voltage Reference composition and the temperature-compensating composition according to supply temperature change (such as direct ratio or inverse ratio) according to supply variation in voltage (such as direct ratio).
Therefore, Fig. 3 shows that (i) i-Vdd current source (according to the supply variation in voltage) reaches (ii) i-temp current source (according to temperature change).The output meeting of this current generating circuit is summed up electric current to current mirror with this two electric current compositions addition and output, or i-copy, block.As shown in FIG., output has the transistor of a plurality of series connection between this current mirror and ground connection reference voltage.The transistor of these a plurality of series connection has output nclamp and sdbias separately.This sdbias signal is the output signal of current mirror, the nclamp signal then be one repeatedly the connection circuit design be repeatedly to connect signal.Can not use for example is the transistor of nclamp, and its cost then is to obtain relatively poor result.
This negative circuit 204A and 204B are driven by a CTAP power supply (being that power supply and circuit power are inversely proportional to).In another embodiment, this negative circuit 204A and 204B are driven by a PTAP power supply (being that power supply is directly proportional with circuit power).In another embodiment, this negative circuit 204A and 204B drive with the irrelevant power supply of deciding of circuit power by one.
Fig. 4 is the schematic diagram of a current mirror block, the discharge of switching between its generation one control sequence circuit reference signal and/or the electric current version of charge rate.
Transistorized bias voltage is to produce block by electric current, or claims i to produce block, produces according to output current.Therefore, be similar to a current mirror, identical transistor biasing can be at current mirror, or i-copy, and the output of block again replica current produces block, or claims I to produce block, output current.Alternatively, can pass through to adjust transistorized width, so that current mirror, or i-copy, the output of block becomes a ratio with the output current that electric current produces block.
As shown in the figure, the transistor of these a plurality of series connection be with a ground connection reference voltage be connected such as the electric current outlet terminal among Fig. 1, it further is connected with OX or OY node.The transistor of these a plurality of series connection has input nclamp, sdbias and input (ENX or ENY) separately.This sdbias signal is the output signal of current mirror, the nclamp signal then be one repeatedly the connection circuit design repeatedly connect signal.Can not use for example is the transistor of nclamp, and its cost then is to obtain relatively poor result.
To be displaying time discharge and/or the OX of charge rate or the graph of a relation of OY node with electric current according to controlled discharge and/or charge rate Fig. 5.
As shown in FIG., discharge rate is and produces block by electric current, or claims I to produce block, and by current mirror, or i-copy, block copy or equal proportion the output current of (and optionally equal proportion) be linear scale.
Although show linearly discharge among the shown embodiment, an alternate embodiment also can be to charge linearly.
The graph of a relation of Fig. 6 clock voltage that to be displaying time export with the integrated circuit with delay circuit.
Fig. 7 and Fig. 8 show the data icon of clock circuit performance described herein.
Fig. 7 is presented at different temperatures lower frequency cycle and the graph of a relation of supplying voltage.
Fig. 8 is presented at the graph of a relation of different supply voltage lower frequency cycles and temperature.
Simulation result as shown in Figures 7 and 8, temperature range [10 ℃～80 ℃] and the supply voltage range [2.7V～4V] interval medium frequency frequency only changed for 1.5 nanoseconds from 70 nanoseconds.So only be equivalent to ± 1.1% change.
Fig. 9 shows the circuit diagram of a temperature-compensated current generator, and it does not have an adjustable temperature coefficient under specified temp in this temperature-compensated current generator.
Below, except reference voltage Vref, different V1 and V2 are called Vptat and Vctat.
I1＝(V1-Vref)/R
I2＝(V2-Vref)/R
ΔI＝I2-I1＝(V2-V1)/R＝ΔV/R
TC＝ΔI/ΔV＝1/R，Iout＝(Vptat-Vref)/R
Therefore, when adjusting temperature coefficient (TC), no matter present output current makes no has been ideal value, all must adjusting resistance value R and output current.
Figure 10 is the circuit diagram according to the temperature-compensated current generator of first embodiment of the invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Below, except reference voltage Vref, different V1 and V2 are called Vptat and Vctat.
I1＝(K1*V1-Vref)/R
I2＝(K1*V2-Vref)/R
ΔI＝I2-I1＝K1*(V2-V1)/R＝K1*ΔV/R
TC＝ΔI/ΔV＝K1/R，Iout＝(K1*Vptat-Vref)/R
Suppose Iout=1, (K1*V-Vref)=R TC=K1/ (K1*V-Vref) then
So different K1 can have different TC
When adjusting temperature coefficient TC, can be by adjusting K1 and R so that output current remains in the desired scope.
Figure 11 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) according to second embodiment of the invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Below, except reference voltage Vref, different V1 and V2 are called Vptat and Vctat.
I1＝(V1-(K2*Vref))/R
I2＝(V2-(K2*Vref))/R
ΔI＝I2-I1＝(V2-V1)/R＝ΔV/R
TC＝ΔI/ΔV＝1/R，Iout＝(V-(K2*Vref))/R
So different K1 can have different TC
When adjusting temperature coefficient TC, can be by adjusting K2 and R so that output current remains in the desired scope.
Figure 12 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) according to third embodiment of the invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Below, except reference voltage Vref, different V1 and V2 are called Vptat and Vctat.
I1＝((K1*V1)-(K2*Vref))/R
I2＝((K1*V2)-(K2*Vref))/R
ΔI＝I2-I1＝K1*(V2-V1)/R＝K1*ΔVptat/R
TC＝ΔI/ΔV＝K1/R，Iout＝((K1*V)-(K2*Vref))/R
When adjusting temperature coefficient TC, can be by adjusting K1, K2 and R so that output current remains in the desired scope.
Figure 13 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) of more detailed the first embodiment according to the present invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 14 is the circuit diagram of the temperature-compensated current generator (producing the some of block for electric current) of more detailed the second embodiment according to the present invention, and it has according to a specific current value of temperature-compensated current generator can adjust temperature coefficient.
Figure 15 shows the temperature-compensated current of the different circuit settings according to the present invention and the graph of a relation of temperature.
Figure 16 can use the block schematic diagram that the present invention has a memory circuit of improvement integrated circuit clock circuit.
Figure 16 is the concise and to the point block schematic diagram that comprises the integrated circuit 1600 of a memory array 1612.One word line (or row)/block chooses decoder and driver 1614 is coupled to, and with it electrical communication is arranged, and many word lines 1616 and character string are selected line, are to arrange along the column direction of memory cell array 1612 therebetween.One bit line (OK) decoder and driver 1618 are coupled to many bit lines 1620 of arranging along the row of memory array 1612, and electrical communication is arranged with it, with from memory cell array 1612 reading out datas, or data writing is to the memory cell of memory cell array 1612.The address is to see through bus 1622 to provide to word line and block selection decoder 1614 and bit line decoder 1618.Induction amplifier in the square 1624 and data input structure, comprise as read, the current source of programming and erasing mode, be to see through bus 1626 to be coupled to bit line decoder 1618.Data are to see through the data input structure that Data In-Line 1628 is sent to square 1624 by the input/output end port on the integrated circuit 1600.In this illustrative embodiment, other circuit 1630 is also included within this integrated circuit 1600, for example general purpose processor or special purpose circuit, or the composite module supported of storage array is to provide the system-on-a-chip function thus.Data are by the induction amplifier in the square 1624, see through DOL Data Output Line 1632, are sent to input/output end port or other integrated circuit 1600 interior or outer data destinations on the integrated circuit 1600.State machine and improvement clock circuit (as discussed here) are in circuit 1634, with control bias voltage adjustment supply electric current and voltage source 1636.In different embodiment, this circuit 1634 has the current generator with temperature correlation, and it has for example is the adjustable temperature coefficient that has an adjustable temperature coefficient scope when a specific current value.In different embodiment, this circuit 1634 has charging that control switches between two reference signals in sequence circuit and/or the multiple of electric current of discharge rate copied or the version of equal proportion.
Figure 17 is the calcspar with delay circuit of the time of delay that the reference current by current generator determines.
This delay circuit is the distortion version that has the clock circuit of one group of similar components among Fig. 2.This delay circuit is usually with the output voltage of capacitor C X charge or discharge with change CX place.The rising of this delay circuit output and/or fall off rate are to produce the reference current decision that block produces by electric current.Electric current produces block thus, or claims I to produce block, electric current be by current mirror, or i-copy, block copy or equal proportion send into this delay circuit.
In one embodiment, capacitor C X is actually common ground end that a PMOS transistor has opposite end points and inverter and removes and to couple.
In another embodiment, wherein capacitor C X is and a common supply coupling.
This negative circuit can by the power supply of a CTAT (power supply that namely is inversely proportional to temperature) or regulating power supply drives.In another embodiment, this negative circuit can be driven by power supply or the adjusting power supply of a PTAT (power supply that namely is directly proportional with temperature).In another embodiment, this negative circuit is to be driven by a temperature independent power supply of deciding.
This negative circuit can by a CTAP (being that power supply and circuit power are inversely proportional to) power supply or regulating power supply drives.In another embodiment, this negative circuit can by a PTAP (being that power supply is directly proportional with circuit power) power supply or regulating power supply drives.In another embodiment, this negative circuit is to drive with the irrelevant power supply of deciding of circuit power by one.
This inverter power supply is controlled, and compares with the stroke that changes inverter and the output (such as the rise/fall of RC circuit) of therefore detecting this sequential circuit.
This inverter has following advantage: the operating voltage VDD that (1) is lower; (2) less circuit size (two metal oxide semiconductor transistors are only arranged inverter and operational amplifier has five or above metal oxide semiconductor transistor); (3) better simply design; (4) lower active electric current (inverter has a current path, and does not need required in an operational amplifier extracurrent mirror); And (5) higher operating rate (inverter has the delay in a stage).
Figure 18 has the calcspar of sharing the multiple delay circuit of the time of delay that current generator decides by one.
Delay system and the delay system among Figure 17 among Figure 18 are similar.Yet the delay system among Figure 17 only couples current generator and a delay circuit, and the delay system among Figure 18 couples current generator and a plurality of delay circuit.Delay system among Figure 18 can be adjusted by the electric current that changes current generator the time of delay of a plurality of delay circuits on the diverse location in the integrated circuit.For example, the reference current of current generator can change by controlling the pruning buffer, and this prunes buffer and can utilize for example change to prune buffer changes reference current with the time of delay of all a plurality of delay circuits of the reference current of adjustment dependence current generator size.Otherwise, adjust the time of delay of a plurality of delay circuits on the diverse location in the integrated circuit and must adjust individually the time of delay of each delay circuit.
Although a plurality of delay circuits are to share identical reference current, these a plurality of delay circuits can produce identical time of delay or different time of delay.In certain embodiments, these a plurality of delay circuits can change by the current mirror ratio that changes between these a plurality of delay circuits.For example, these a plurality of delay circuits can change the ratio of transistor width in the current replication block of transistor width and Fig. 3 in the current replication block of Fig. 4.In other example, a plurality of indivedual current mirror transistor are to connect abreast.In addition, for example the capacitance of the capacitor C X among Figure 17 also can change.
Figure 19 has a calcspar of sharing the multiple delay circuit of the time of delay that current generator decides by one for another kind of.Similarly be that single current generator control determines the reference current of the time of delay of multiple delay circuit with Figure 18.Each postpones block can have identical or different delay circuit.It shows the multiple example of different delay circuits to see also Figure 20～Figure 27.
Figure 20 to Figure 23 shows that collocation is decided the calcspar of the delay circuit of time of delay by a reference current of a current generator.
The input that the different delay circuits from Figure 20 to Figure 23 of Figure 24 to Figure 27 demonstration are corresponding and the sequential chart of output voltage track.
Figure 28 displays temperature compensates the graph of a relation from the circuit power compensating delay time that is produced by different delay blocks.
Producing the different delay circuits that postpone is to be got by the condition Imitating of different temperatures and power supply.These different delay circuits be respectively 5 nanosecond delay circuit, 10 nanosecond delay circuit, 15 nanosecond delay circuit and 20 nanosecond delay circuit.The emulation of the combination that these are different is :-10 ℃ and 3.3V power supply, 25 ℃ and 2.9V power supply, 25 ℃ and 3.3V power supply, 25 ℃ and 3.8V power supply, 35 ℃ and 3.3V power supply, 80 ℃ and 3.3V power supply.Its simulation result is presented at that each delay circuit has identical performance under the combination of different temperatures and power supply.
Can use different modes control this time of delay.When the current mirror ratio changes, for example change independent current mirror transistor or parallel connected multiple current mirror transistor other width.In addition, also can Change Example the capacitance of the capacitor C X among Figure 17 in this way.
Figure 29 shows the test flow chart of a test machine, and it can be adjusted automatically has in the integrated circuit single group of time of delay of pruning multiple delay block in the buffer.
In step 2910, this test machine is sent (i) test mode command and (ii) is pruned position=000 to integrated circuit to be tested.This prunes the size of reference current in the control lag circuit of position.In step 2920, the test-run a machine of testing oneself send the high level reference pulse to integrated circuit to be tested.In step 2930, respond the high level reference pulse that the test-run a machine of testing oneself is sent, this integrated circuit to be tested begins the counting of delay circuit control frequency (having by a cycle of pruning position control) and IC interior frequency to be tested.In step 2940, the test-run a machine of testing oneself send the low level reference pulse to integrated circuit to be tested.In step 2950, respond the low level reference pulse that the test-run a machine of testing oneself is sent, this integrated circuit to be tested finishes delay circuit control frequency, and transmits the count number of internal frequency to test machine from integrated circuit to be tested.In step 2960, whether the count number that this test machine determines this moment is greater than the desired value of frequency counting number.If no, then this frequency is too slow, then determines the pruning position in the integrated circuit to be tested or other delay circuit of thus reference current control need to be adjusted to accelerate frequency at this test machine of step 2970.In step 2970, be stored in the test machine and this flow process is got back to step 2920 with pruning value after the position increases.On the other hand, if the count number that this test machine determines this moment in step 2960, is stored in the value of pruning after the position increases in the test machine then in step 2980 greater than the desired value of frequency counting number.
Figure 30 shows that a meeting has the single group of calcspar of pruning the test macro of the time of delay of multiple delay block in the buffer in adjustment one integrated circuit automatically.
This test machine and testing integrated circuits couple.This test machine is sent test mode command with the automatic pruning of this delay circuit of initialization.This test machine also can send high level and low level reference pulse to integrated circuit to be tested with beginning or finish to have in the delay circuit frequency number by the time of delay of reference current control.Current generator in this integrated circuit to be tested has prunes the size that buffer is controlled reference current.This integrated circuit to be tested also comprise counter response from the reference pulse of test machine with to frequency counting.
Figure 31 is presented under the different technology conditions and postpones graph of a relation time of delay that block produces by difference.
Under different technology conditions simulated after being pruned by the automatic test pattern that discloses among Figure 29 and Figure 30 the time of delay that delay circuit produces.Its simulation result is presented at such as being that each delay circuit has identical performance under the different process such as NMOS critical voltage change, the change of PMOS critical voltage and resistance value change.
Can use different modes control this time of delay.When the current mirror ratio changes, for example change independent current mirror transistor or parallel connected multiple current mirror transistor other width.In addition, also can Change Example the capacitance of the capacitor C X among Figure 17 in this way.
Figure 32 shows the circuit diagram of this current generating circuit, the electric current of charging and/or discharge rate between the reference signal of its generation control in having the sequence circuit of pruning circuit.
Current generating circuit and the current generating circuit among Fig. 3 among Figure 32 are similar.Yet the current generating circuit among Figure 32 is to have the example of pruning circuit.In this example, the trim signal T0～T3 that certainly prunes the position buffer by open or this current mirror output of closing control in the transistor of the multi-element electric current that is increased change the output current of current mirror.A kind of example application is the current generator among Figure 20.
Although the present invention is described with reference to embodiment, right the present invention's creation is not subject to its detailed description.Substitute mode and revise pattern and in previous description, advise, and other substitute mode and modification pattern will by the person skilled in the art thought and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result person in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and modification pattern are intended to drop on the present invention among the category that enclose claim scope and equipollent thereof define.
Claims (27)
1. device comprises:
One integrated circuit produces a clock signal, comprises:
Sequence circuit, it has an output of switching between reference signal;
One electric current produces block, and it has an output current and controls at least (i) discharge rate between those reference signals, in the charge rate that (ii) switches between those reference signals one;
A plurality of current mirror blocks, it produces a plurality of versions that this electric current produces this output current of block, this discharge rate of this sequence circuit different piece of the Current Control of these a plurality of versions and at least one in this charge rate; And
This output of one level switching circuit and this sequence circuit couples, this level switching circuit has an output of this clock signal that determines this integrated circuit, wherein this output switching output level of this level switching circuit and respond a trigger point of this this level switching circuit of output arrival of this sequence circuit.
2. device according to claim 1, wherein this output of the decision of this sequence circuit and this level switching circuit and this clock signal.
3. device according to claim 1, wherein this electric current this output current of producing block comprises at least one in (i) power supply compensating component and (ii) the temperature-compensating composition.
4. device according to claim 1, wherein this electric current this output current of producing block comprises (i) power supply compensating component it has an adjustable power supply coefficient, and this power supply compensating component be directly proportional with power supply, inverse ratio or irrelevant at least one, it has an adjustable temperature coefficient with (ii) temperature-compensating composition, and this temperature-compensating composition be directly proportional with temperature, inverse ratio or irrelevant at least one, and above-mentioned (i) and (ii) at least one among both.
5. device according to claim 1, wherein this electric current this output current of producing block comprises at least a power supply compensating component it has an adjustable power supply coefficient, and this power supply compensating component be directly proportional with power supply, inverse ratio or irrelevant at least one.
6. device according to claim 1, wherein this electric current produce block this output current at least one temperature-compensating composition its have an adjustable temperature coefficient, and this temperature-compensating composition be directly proportional with temperature, inverse ratio or irrelevant at least one.
7. device according to claim 1, wherein this electric current this output current of producing block comprise (i) temperature-compensating composition and (ii) a power supply compensating component its have an adjustable power supply coefficient, and this power supply compensating component be directly proportional with power supply, inverse ratio or irrelevant at least one.
8. device according to claim 1, wherein this electric current this output current of producing block comprise (i) power supply compensating component and (ii) a temperature-compensating composition its have an adjustable temperature coefficient, and this temperature-compensating composition be directly proportional with temperature, inverse ratio or irrelevant at least one.
9. device according to claim 1, wherein the output current of these a plurality of versions is respectively a ratio of this output current.
10. device according to claim 1 more comprises:
One latch circuit, receive this output of this level switching circuit and produce this clock signal of this integrated circuit, this latch circuit comprises the logic gate that couples alternately, so that the input of another logic gate that couples alternately in the output of this logic gate that couples alternately and this latch circuit couples in this latch circuit, the different piece that this latch circuit has a plurality of inputs and this sequence circuit couples.
11. one kind produces the method for a clock signal from an integrated circuit, comprises:
To switch between a plurality of reference signals of being output in of a sequential circuit;
Produce an electric current, it controls (i) in the discharge rate between those reference signals and the charge rate that (ii) switches one at least between those reference signals;
Produce the electric current of a plurality of versions of this electric current, with this discharge rate of controlling at least this sequence circuit different piece and at least one in this charge rate; And
This output of switching the output level of a level switching circuit and responding this sequence circuit arrives a trigger point of this level switching circuit, and an output of this level switching circuit determines this clock signal of this integrated circuit.
12. method according to claim 11, wherein this output of the decision of this sequence circuit and this level switching circuit and this clock signal.
13. method according to claim 11, at least one in this discharge rate of this Current Control and this charge rate wherein comprises at least one in (i) power supply compensating component and (ii) the temperature-compensating composition.
14. method according to claim 11, at least one in this discharge rate of this Current Control and this charge rate wherein, it has an adjustable power supply coefficient to comprise (i) power supply compensating component, and this power supply compensating component be directly proportional with power supply, inverse ratio or irrelevant at least one, it has an adjustable temperature coefficient with (ii) temperature-compensating composition, and this temperature-compensating composition be directly proportional with temperature, inverse ratio or irrelevant at least one, and above-mentioned (i) and (ii) at least one among both.
15. method according to claim 11, at least one in this discharge rate of this Current Control and this charge rate wherein, at least it has an adjustable power supply coefficient to comprise a power supply compensating component, and this power supply compensating component be directly proportional with power supply, inverse ratio or irrelevant at least one.
16. method according to claim 11, at least one in this discharge rate of this Current Control and this charge rate wherein, it has an adjustable temperature coefficient at least one temperature-compensating composition, and this temperature-compensating composition be directly proportional with temperature, inverse ratio or irrelevant at least one.
17. method according to claim 11, at least one in this discharge rate of this Current Control and this charge rate wherein, comprise (i) temperature-compensating composition and (ii) a power supply compensating component its have an adjustable power supply coefficient, and this power supply compensating component be directly proportional with power supply, inverse ratio or irrelevant at least one.
18. method according to claim 11, at least one in this discharge rate of this Current Control and this charge rate wherein, comprise (i) power supply compensating component and (ii) a temperature-compensating composition its have an adjustable temperature coefficient, and this temperature-compensating composition be directly proportional with temperature, inverse ratio or irrelevant at least one.
19. method according to claim 11, wherein the electric current of these a plurality of versions is respectively at least one the ratio of this electric current in control this discharge rate and this charge rate.
20. method according to claim 11 more comprises:
Generation has this clock signal that a bolt-lock receives this integrated circuit of this level switching circuit, this bolt-lock comprises the logic gate that couples alternately, so that the input of another logic gate that couples alternately in the output of this logic gate that couples alternately and this bolt-lock couples in this bolt-lock, the different piece that this bolt-lock has a plurality of inputs and this sequence circuit couples.
21. a device comprises:
One integrated circuit produces an inhibit signal, comprises:
Delay circuit, it has an output of switching between reference signal;
One electric current produces block, and it has an output current and controls at least (i) discharge rate between those reference signals, in the charge rate that (ii) switches between those reference signals one;
One current mirror block, it produces the version that this electric current produces this output current of block, this discharge rate of this sequence circuit different piece of the Current Control of this version and at least one in this charge rate; And
This output of one level switching circuit and this sequence circuit couples, this level switching circuit has an output of this inhibit signal that determines this integrated circuit, wherein this output switching output level of this level switching circuit and respond a trigger point of this this level switching circuit of output arrival of this sequence circuit.
22. device according to claim 21, wherein this integrated circuit produces a plurality of inhibit signals that comprise this inhibit signal, and this device more comprises:
A plurality of delay circuits produce these a plurality of inhibit signals, and each delay circuit in these a plurality of delay circuits comprises:
This delay circuit has an output of switching between reference signal;
This current mirror block produces this version that this electric current produces this output current of block, this discharge rate of this sequence circuit different piece of the Current Control of this version and at least one in this charge rate; And
This output of this level switching circuit and this sequence circuit couples, this level switching circuit has this output that determines this inhibit signal in these a plurality of inhibit signals, wherein this output switching output level of this level switching circuit and respond a trigger point of this this level switching circuit of output arrival of this sequence circuit.
23. device according to claim 22, wherein this current mirror block of these a plurality of delay circuits produces the version of ratio that this electric current produces this output current of block, and wherein the specific currents size of the version of this ratio of this output current causes the corresponding time of delay in these a plurality of inhibit signals.
24. device according to claim 22, wherein this integrated circuit more comprises:
The storage stack buffer produces a size of this output current of block to control this electric current.
25. device according to claim 24 wherein should be organized memory buffer control by the time of delay of these a plurality of inhibit signals of these a plurality of delay circuits generations.
26. device according to claim 24, wherein this integrated circuit has a test pattern, and its output is according to a sum total number of the frequency signal counting of this group memory buffer change.
27. device according to claim 24, wherein this integrated circuit has a test pattern, and it changes this group memory buffer to compensate the different technology conditions in technique.
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| CN201110327244.7A CN103078607B (en) | 2011-10-25 | 2011-10-25 | Clock integrated circuit |
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| CN201110327244.7A CN103078607B (en) | 2011-10-25 | 2011-10-25 | Clock integrated circuit |
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| CN104917492A (en) * | 2015-07-06 | 2015-09-16 | 电子科技大学 | CMOS oscillator |
| CN107799136A (en) * | 2017-11-21 | 2018-03-13 | 上海华虹宏力半导体制造有限公司 | SONOS reads sequence circuit |
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| CN103078607B (en) | 2015-02-18 |
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