TWI473433B - Clock integrated circuit - Google Patents

Description

Clock integrated circuit

The present invention relates to an integrated circuit having a clock circuit that can tolerate variations such as temperature and power supply.

The operation of the clock circuit of the integrated circuit varies with factors such as temperature and power supply. Since these variations affect the final timing of the output clock signal, a number of studies have been conducted to address this problem, resulting in a more uniform output clock signal in the presence of the above variations.

For example, the clock circuit of the integrated circuit can rely on a reference signal generated by a combination of a voltage boost generated above a supply voltage and a voltage regulator. Such a circuit consumes a large amount of grain area and current.

Therefore, there is a demand, and it is hoped that these variability problems can be solved, but with less complicated structure and less cost.

The present invention provides an integrated circuit having a delay circuit that generates a signal. The integrated circuit has a delay circuit and includes a timing circuit, a current generating block, a plurality of current mirror blocks, and a level switching circuit.

This sequential circuit has an output that switches between reference signals.

The current generating block has an output control current that at least controls (i) a discharge rate between the reference signals, and (ii) one of the charging rates that are switched between the reference signals, the compensation circuit is provided by a supply voltage power supply.

The plurality of current mirroring blocks generate a plurality of versions of the output control current of the plurality of current generating blocks, the plurality of current versions controlling at least one of the discharge rate and the charging rate of different portions of the sequential circuit.

The level switching circuit is coupled to the output of the timing circuit, and the level switching circuit has an output of the clock signal that determines the integrated circuit having the delay circuit, wherein the output switching output of the level switching circuit is The bit arrives at a trigger point of the level switching circuit in response to the output of the timing circuit.

In an embodiment, the timing circuit and the level switching circuit determine the output of the clock signal.

In various embodiments, the output current of the current generating block includes at least one of a power compensation component and a temperature compensation component.

In such an embodiment having a temperature compensating component, the temperature compensating component has an adjustable temperature coefficient. In some embodiments having an adjustable temperature coefficient, the adjustable temperature coefficient includes at least one of proportional to temperature, inversely proportional, or unrelated.

In some embodiments having a temperature compensating component, the temperature compensating component has an adjustable temperature coefficient, and the adjustable temperature coefficient includes a voltage component associated with temperature that can be adjusted by more than one time.

In some embodiments having a temperature compensating component, the temperature compensating component has an adjustable temperature coefficient, and the adjustable temperature coefficient includes a voltage component associated with temperature that can be less than a one-fold correlation adjustment.

In some embodiments having a power compensation component, the power compensation component has an adjustable power factor. In some embodiments having an adjustable power factor, the power compensation component at a particular current value has a range of adjustable power factor. In some embodiments having an adjustable power factor, the adjustable power factor includes at least one of proportional to, inversely proportional to, or unrelated to temperature.

In some embodiments having a power compensation component, the power compensation component has an adjustable power factor, and the adjustable power factor includes a voltage component associated with the power source that can be adjusted by more than one-fold correlation.

In some embodiments having a power compensation component, the power compensation component has an adjustable power factor, and the adjustable power factor includes a voltage component associated with the power source that can be less than one-fold correlation adjustment.

In one embodiment, the versions of the plurality of output currents are each a ratio of the output current.

In an embodiment, a latch circuit is further included. The latch circuit receives the output of the level switching circuit and generates the clock signal of the integrated circuit having the delay circuit, the latch circuit includes an interactively coupled logic gate, such that the latching circuit is coupled to the latch The output of the logic gate is coupled to an input of another alternately coupled logic gate of the latch circuit, the latch circuit having a plurality of inputs coupled to different portions of the timing circuit.

Another object of the present invention is to provide a method of generating a clock signal from an integrated circuit having a delay circuit. The method includes the steps of: switching an output of a sequential circuit between a plurality of reference signals; generating a current that controls at least (i) a rate of discharge between the reference signals, (ii) at the reference signals One of a charging rate between the switching; generating a plurality of current versions of the current to control at least one of the discharging rate and the charging rate of the different portions of the sequential circuit, the plurality of current versions controlling the sequential circuit differently And at least one of the discharge rate and the charging rate; and switching an output level of the level switching circuit to a trigger point of the level switching circuit in response to the output of the timing circuit, the level switching circuit An output determines the clock signal of the integrated circuit having the delay circuit.

In an embodiment, the timing circuit and the level switching circuit determine the output of the clock signal.

In various embodiments, the output of the current generating block includes at least one of a reference voltage component and a temperature compensation component. In some embodiments having a temperature compensating component, the temperature compensating component has an adjustable temperature coefficient. In some embodiments having an adjustable temperature coefficient, the temperature compensating component has an adjustable temperature coefficient range at a particular current value. In some embodiments having an adjustable temperature coefficient, the adjustable temperature coefficient includes at least one of a voltage component that is temperature dependent and a temperature component that is inversely proportional to temperature.

In some embodiments having a temperature compensating component, the temperature compensating component has an adjustable temperature coefficient, and the adjustable temperature coefficient includes a voltage component associated with temperature that can be adjusted by more than one time.

In some embodiments having a temperature compensating component, the temperature compensating component has an adjustable temperature coefficient, and the adjustable temperature coefficient includes a voltage component associated with temperature that can be less than a one-fold correlation adjustment.

In one embodiment, the versions of the plurality of output currents are each a ratio of the output current.

In an embodiment, the method further includes generating the clock signal of the integrated circuit having the delay circuit receiving the level switching circuit, the latch comprising an interactively coupled logic gate, such that the latch An output of the alternately coupled logic gate is coupled to an input of another alternately coupled logic gate of the latch, the latch having a plurality of inputs coupled to different portions of the timing circuit.

It is still another object of the present invention to provide an apparatus for generating a plurality of delayed signals from an integrated circuit. The integrated circuit includes a current generating block and a plurality of delay circuits.

The current generating block has an output current that at least controls (i) a rate of discharge between the reference signals, and (ii) one of charging rates that are switched between the reference signals.

The plurality of delay circuits generate the plurality of delayed signals. Each of the plurality of delay circuits includes a delay circuit, a current mirror block, and a level switching circuit. The current mirroring block produces a version of the output current of the current generating block, the version of current controlling at least one of the discharging rate and the charging rate of different portions of the sequential circuit. The level switching circuit is coupled to the output of the timing circuit. The level switching circuit has an output for determining the delay signal of the integrated circuit, wherein the output of the level switching circuit switches the output level and the output of the sequential circuit reaches a trigger point of the level switching circuit .

An embodiment includes a single delay circuit.

In one embodiment, the current mirroring block produces a version of the ratio of the output current of the current generating block, wherein a specific current magnitude of the version of the ratio of the output current results in a corresponding delay time in the plurality of delayed signals .

In one embodiment, the integrated circuit further includes a set of memory registers to control the magnitude of the output current of the current generating block.

In one embodiment, the set of memory registers controls a delay time of the plurality of delayed signals generated by the plurality of delay circuits.

In one embodiment, the integrated circuit has a test mode that outputs a total number of clock signals counted according to one of the set of memory register changes.

In one embodiment, the integrated circuit has a test mode that varies the set of memory registers to compensate for different process conditions in the process.

The present invention discloses many different embodiments.

The present invention is related to U.S. Patent Application Nos. 12/631,661, 12/631,693, 12/631,705, and 12/834,369. It is cited here as a reference.

Figure 1 shows a block diagram of a multi-version integrated circuit clock circuit having a current that produces a discharge and/or rate between two of said reference signals.

The integrated circuit having the delay circuit is usually a one-loop structure having a sequential circuit 102, a level switching circuit 104, and a latch circuit 106. The latch circuit 106 generates a feedback signal from the latch circuit 106 to the timing circuit 102 and a clock output signal 110. The timing circuit 102 switches between two reference signals according to a time constant, such as a supply voltage reference signal and a ground reference signal. The output of this sequential circuit will rise from the low level reference to the high level reference and/or from the high level reference to the low level reference. The rate of rise and/or fall of the output of the sequential circuit is determined by the current generated by block 116. The current generated by block 116 is replicated by current mirror block 118 or sent to a plurality of locations in sequential circuit 102 in equal proportions.

The level switching circuit 104 monitors the output of the timing circuit 102 and changes its output depending on whether the timing circuit 102 is sufficiently high or low. Examples of the latch circuit 106 are an SR latch, an SR NAND latch, a JK latch, a gate SR latch, a gate D latch, a gate trigger latch, and the like. The latch circuit circuit 106 has two stable states and switches between the two stable states to generate a clock output signal 110.

2 is a circuit diagram of an integrated circuit clock circuit that can generate multiple versions of a current to control the rate of charge and/or discharge between the two reference signals being tracked by the sequential circuit 102.

The sequence shows parallel placed timing circuits 202A and 202B, parallel placed inverting circuits 204A and 204B, and a latch circuit 206. This timing circuits 202A and 202B are typically charged or discharged from a capacitor CX or CY to change the output voltage of OX or OY. The rise and/or fall rate of the output of this sequential circuit is determined by the current generated by the current generating block. The current generated by this current generator block is replicated by multiple current mirroring blocks or proportionally in sequential circuits 202A and 202B.

In the illustrated embodiment, the capacitor CX or CY is coupled to a common ground. Although not all possible variations are explicitly illustrated in the drawings, the techniques of the present invention include sequential circuits having capacitors CX or CY in all embodiments, wherein the timing circuits can be modified to couple capacitors CX or CY to a common ground.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor having opposite ends that are decoupled from the common ground of the inverter.

In another embodiment, the capacitor CX or CY is coupled to a common power source. Although not all possible variations are shown in the drawings, the techniques of the present invention include a sequential circuit having capacitors CX or CY in all embodiments, wherein the timing circuit can be modified to couple the capacitor CX or CY to a common power source.

The inverter circuits 204A and 204B are driven by a CTAT power supply or a power supply that is inversely proportional to temperature, which decreases as the temperature increases. In another embodiment, the inverter circuits 204A and 204B are driven by a PTAT power supply or a power supply proportional to temperature which increases with increasing temperature. In another embodiment, the inverter circuits 204A and 204B are driven by a temperature independent power supply.

The inverter circuits 204A and 204B are driven by a CTAP power supply (i.e., the power supply is inversely proportional to the circuit power supply). In another embodiment, the inverter circuits 204A and 204B are driven by a PTAP power supply (i.e., the power supply is proportional to the circuit power supply). In another embodiment, the inverter circuits 204A and 204B are driven by a constant power source independent of the circuit power supply.

The inverter power supply is controlled to change the stroke of the inverter and thus detect the output of the sequential circuit (such as the rise/fall of the RC circuit) for comparison.

This inverter has the following advantages over the op amp version: (1) lower operating voltage VDD; (2) smaller circuit size (inverter has only two MOS transistors and op amp has Five or more MOS transistors); (3) simpler design; (4) lower active current (inverter has a current path without the need for an additional current mirror in the op amp And; (5) a higher operating speed (the inverter has a phase delay).

The latch circuit 206 is alternately coupled such that the output of one logic gate is coupled to the input of another logic gate. One input of a logic gate is directly coupled to the output of another logic gate. The other input of the logic gate is directly coupled to the output of another logic gate via a timing circuit and a level detection circuit.

Figure 3 is a schematic diagram of a current generator that produces a discharge and/or charge rate that controls switching between reference circuit reference signals.

The current generating circuit, or i-generator, has two current generating components: a voltage reference component that varies according to a supply voltage (eg, proportional) and a temperature compensation component that varies according to a supply temperature (eg, proportional or inverse ratio).

Therefore, Figure 3 shows (i) the i-Vdd current source (according to the supply voltage variation) and (ii) the i-temp current source (according to temperature fluctuations). The output of this current generating circuit adds the two current components and outputs the combined current to the current mirror, or i-copy, block. As shown in the figure, the output has a plurality of transistors connected in series between the current mirror and the ground reference voltage. The plurality of series connected transistors have respective outputs nclamp and sdbias. The sdbias signal is the output signal of the current mirror, and the nclamp signal is a spliced signal of a stacked circuit design. A transistor such as an nclamp may not be used, at the expense of poor results.

The inverter circuits 204A and 204B are driven by a CTAP power supply (i.e., the power supply is inversely proportional to the circuit power supply). In another embodiment, the inverter circuits 204A and 204B are driven by a PTAP power supply (i.e., the power supply is proportional to the circuit power supply). In another embodiment, the inverter circuits 204A and 204B are driven by a constant power source independent of the circuit power supply.

Figure 4 is a schematic illustration of a current mirroring block that produces a current version that controls the switching and/or charging rate of switching between reference circuit reference signals.

The bias voltage of the transistor is generated by a current generating block, or i, a block, which is generated according to the output current. Thus, similar to a current mirror, the same transistor bias will be reflected in the current mirror, or i-copy, the output of the block re-copy current generation block, or I-generated block, the output current. Alternatively, the output of the block can be made proportional to the output current of the current generating block by adjusting the width of the transistor such that the current is mirrored, or i-copy.

As shown, the plurality of series-connected electro-crystalline systems connect a ground reference voltage to the current output terminal as in Figure 1, which is further coupled to the OX or OY node. The plurality of series connected transistors have respective inputs nclamp, sdbias and inputs (ENX or ENY). The sdbias signal is the output signal of the current mirror, and the nclamp signal is a spliced signal of a stacked circuit design. A transistor such as an nclamp may not be used, at the expense of poor results.

Figure 5 is a graph showing the relationship between time and OX or OY nodes for discharging and/or charging rates based on currents that control discharge and/or charging rate.

As shown in the figure, the discharge rate is either copied by current generation block, or I generated block, and mirrored by current, or i-copy, block or proportionally (and optionally proportionally) The output current is linearly proportional.

While the illustrated embodiment shows linear discharge, an alternate embodiment may also be linearly charged.

Fig. 6 is a graph showing the relationship between the time and the clock voltage outputted by the integrated circuit having the delay circuit.

Figures 7 and 8 show a graphical representation of the performance of the clock circuit described herein.

Figure 7 shows the relationship between the clock cycle and the supply voltage at different temperatures.

Figure 8 shows the relationship between clock cycle and temperature at different supply voltages.

As shown in the simulation results in Figures 7 and 8, the clock frequency has changed by only 1.5 nanoseconds from 70 nanoseconds in the temperature range [-10 °C ~ 80 °C] and the supply voltage range [2.7V~4V]. . This is only equivalent to a change of ±1.1%.

Figure 9 shows a circuit diagram of a temperature compensated current generator that does not have an adjustable temperature coefficient at a particular temperature in the temperature compensated current generator.

Hereinafter, in addition to the reference voltage Vref, different V1 and V2 are referred to as Vptat and Vctat.

I1=(V1-Vref)/R

I2=(V2-Vref)/R

ΔI=I2-I1=(V2-V1)/R=ΔV/R

TC=ΔI/ΔV=1/R, Iout=(Vptat-Vref)/R

Therefore, when the temperature coefficient (TC) is adjusted, the resistance value R and the output current must be adjusted regardless of whether the current output current is already an ideal value.

Fig. 10 is a circuit diagram of a temperature compensation current generator according to a first embodiment of the present invention, which has a temperature coefficient which can be adjusted according to a specific current value of the temperature compensation current generator.

Hereinafter, in addition to the reference voltage Vref, different V1 and V2 are referred to as Vptat and Vctat.

I1=(K1*V1-Vref)/R

I2=(K1*V2-Vref)/R

ΔI=I2-I1=K1*(V2-V1)/R=K1*ΔV/R

TC=ΔI/ΔV=K1/R, Iout=(K1*Vptat-Vref)/R

Suppose Iout=1, (K1*V-Vref)=R then TC=K1/(K1*V-Vref)

So different K1 will have different TCs

When the temperature coefficient TC is adjusted, the output current can be kept within the desired range by adjusting K1 and R.

11 is a circuit diagram of a temperature compensation current generator (which is a part of a current generating block) according to a second embodiment of the present invention, which has a temperature coefficient that can be adjusted according to a specific current value of the temperature compensation current generator .

Hereinafter, in addition to the reference voltage Vref, different V1 and V2 are referred to as Vptat and Vctat.

I1=(V1-(K2*Vref))/R

I2=(V2-(K2*Vref))/R

ΔI=I2-I1=(V2-V1)/R=ΔV/R

TC=ΔI/ΔV=1/R, Iout=(V-(K2*Vref))/R

So different K1 will have different TCs

When the temperature coefficient TC is adjusted, the output current can be kept within the desired range by adjusting K2 and R.

Figure 12 is a circuit diagram of a temperature compensated current generator (which is part of a current generating block) according to a third embodiment of the present invention, which has a temperature coefficient that can be adjusted according to a specific current value of the temperature compensating current generator .

Hereinafter, in addition to the reference voltage Vref, different V1 and V2 are referred to as Vptat and Vctat.

I1=((K1*V1)-(K2*Vref))/R

I2=((K1*V2)-(K2*Vref))/R

ΔI=I2-I1=K1*(V2-V1)/R=K1*ΔVptat/R

TC=ΔI/ΔV=K1/R, Iout=((K1*V)-(K2*Vref))/R

When the temperature coefficient TC is adjusted, the output current can be kept within the desired range by adjusting K1, K2, and R.

Figure 13 is a circuit diagram of a temperature compensated current generator (part of a current generating block) according to a first embodiment of the present invention in more detail, having a specific current value according to a temperature compensating current generator Adjust the temperature coefficient.

Figure 14 is a circuit diagram of a temperature compensated current generator (part of a current generating block) according to a second embodiment of the present invention in more detail, having a specific current value according to the temperature compensating current generator Adjust the temperature coefficient.

Figure 15 is a graph showing the relationship between temperature compensation current and temperature set by different circuits in accordance with the present invention.

Figure 16 is a block diagram showing a memory circuit of the present invention having an improved integrated circuit clock circuit.

Figure 16 is a schematic block diagram of an integrated circuit 1600 including a memory array 1612. A word line (or column) / block selection decoder and driver 1614 are coupled to, and have electrical communication therewith, a plurality of word line lines 1616 and a string selection line, along the memory cell array 1612 Arrange in the column direction. A one-line (row) decoder and driver 1618 is coupled to the plurality of bit lines 1620 arranged along the row of the memory array 1612 and electrically communicated with the memory cell array 1612 for reading data. Or write data to the memory cells of the memory cell array 1612. The address is provided through bus bar 1622 to word line and block select decoder 1614 and bit line decoder 1618. The sense amplifier and data input structures in block 1624, including current sources as read, program, and erase modes, are coupled to bit line decoder 1618 via bus 1626. The data is transferred from the input/output port on the integrated circuit 1600 through the data input line 1628 to the data input structure of block 1624. In the illustrated embodiment, other circuits 1630 are also included in the integrated circuit 1600, such as a general purpose processor or special purpose circuit, or a combination module supported by the memory array to provide a single wafer system function. The data is transmitted by the sense amplifier in block 1624, through data output line 1632, to the input/output port on integrated circuit 1600 or to other data destinations within or outside of integrated circuit 1600. The state mechanism and the modified clock circuit (as discussed herein) are coupled to circuit 1634 to control the bias voltage to adjust supply voltage current source 1636. In various embodiments, the circuit 1634 has a temperature dependent current generator having an adjustable temperature coefficient having an adjustable temperature coefficient range, for example, at a particular current value. In various embodiments, this circuit 1634 has multiple copies or a proportional version of the current that controls the charge and/or discharge rate that is switched between the two reference signals in the sequential circuit.

Figure 17 is a block diagram of a delay circuit having a delay time determined by a reference current of the current generator.

This delay circuit is a modified version of the clock circuit having a set of similar components in the second figure. This delay circuit typically charges or discharges capacitor CX to change the output voltage at CX. The rise and/or fall rate of the output of the delay circuit is determined by a reference current generated by the current generating block. The current generating block, or I generating block, is current mirrored by current, or i-copy, block copied or proportionally fed into the delay circuit.

In one embodiment, the capacitor CX is actually a PMOS transistor having opposite ends that are decoupled from the common ground of the inverter.

In another embodiment, the capacitor CX is coupled to a common power source.

The inverter circuit can be driven by a CTAT (ie, a power source that is inversely proportional to temperature) or an regulated power source. In another embodiment, the inverter circuit can be driven by a PTAT (ie, a power source proportional to temperature) or an regulated power source. In another embodiment, the inverter circuit is driven by a temperature independent power supply.

The inverter circuit can be driven by a CTAP (ie, the power supply is inversely proportional to the circuit power supply) or an regulated power supply. In another embodiment, the inverter circuit can be driven by a PTAP (ie, the power supply is proportional to the circuit power supply) or an regulated power supply. In another embodiment, the inverter circuit is driven by a constant power source independent of the circuit power supply.

The inverter power supply is controlled to change the stroke of the inverter and thus detect the output of the sequential circuit (such as the rise/fall of the RC circuit) for comparison.

This inverter has the following advantages: (1) lower operating voltage VDD; (2) smaller circuit size (inverter has only two MOS transistors and op amp has five or more gold) Oxygen semi-transistor); (3) simpler design; (4) lower active current (inverter has a current path without the need for an additional current mirror in the op amp); and (5) Higher operating speed (inverter has a phase delay).

Figure 18 is a block diagram of a multiple delay circuit having a delay time determined by a shared current generator.

The delay system in Fig. 18 is similar to the delay system in Fig. 17. However, the delay system of Fig. 17 only couples the current generator to one delay circuit, and the delay system of Fig. 18 couples the current generator with a plurality of delay circuits. The delay system of Fig. 18 can adjust the delay time of a plurality of delay circuits at different positions in the integrated circuit by changing the current of the current generator. For example, the reference current of the current generator can be changed by controlling the trim register, and the trim register can utilize, for example, changing the trim register to adjust all of the plurality of delay circuits that rely on the current reference of the current generator. The delay time changes the magnitude of the reference current. Otherwise, adjusting the delay time of multiple delay circuits at different locations in the integrated circuit must be individually adjusted for the delay time of each delay circuit.

Although multiple delay circuits share the same reference current, the multiple delay circuits can produce the same delay time or different delay times. In some embodiments, the plurality of delay circuits can be varied by varying the current mirror ratio between the plurality of delay circuits. For example, the plurality of delay circuits can change the ratio of the transistor width in the current replica block of FIG. 4 to the transistor width in the current replica block of FIG. In other examples, a plurality of individual current mirror transistors are connected in parallel. Further, for example, the capacitance value of the capacitor CX in Fig. 17 can also be changed.

Figure 19 is a block diagram of another multiple delay circuit having a delay time determined by a shared current generator. Similar to Fig. 18, a single current generator controls the reference current that determines the delay time of the multiple delay circuits. Each of the delay blocks may have the same or different delay circuits. See Figures 20~27 for a variety of examples of different delay circuits.

Figures 20 through 23 show block diagrams of a delay circuit with a reference current from a current generator to determine the delay time.

Figures 24 to 27 show timing diagrams of the input and output voltage traces corresponding to the different delay circuits of Figures 20-23.

Figure 28 shows the relationship between temperature compensation and circuit power supply compensation delay time generated by different delay blocks.

Delay circuits that produce different delays are simulated from different temperatures and power supplies. These different delay circuits are a 5 nanosecond delay circuit, a 10 nanosecond delay circuit, a 15 nanosecond delay circuit, and a 20 nanosecond delay circuit. The simulations of these different combinations are: -10 ° C and 3.3 V power supply, 25 ° C and 2.9 V power supply, 25 ° C and 3.3 V power supply, 25 ° C and 3.8 V power supply, 35 ° C and 3.3 V power supply, 80 ° C and 3.3 V power supply . The simulation results show that each delay circuit has the same performance under the combination of different temperatures and power supplies.

This delay time can be controlled in different ways. When the current mirror ratio is changed, for example, the individual widths of the individual current mirror transistors or the multiple current mirror transistors connected in parallel are changed. Further, it is also possible to change the capacitance value of the capacitor CX, for example, in FIG.

Figure 29 shows a test flow diagram of a test machine that automatically adjusts the delay time for multiple delay blocks in a single set of trim registers in an integrated circuit.

At step 2910, the tester sends (i) the test mode command and (ii) trim bit = 000 to the integrated circuit to be tested. This trim bit controls the magnitude of the reference current in the delay circuit. At step 2920, the high level reference pulse is sent from the test machine to the integrated circuit to be tested. In step 2930, in response to the high level reference pulse sent from the tester, the integrated circuit to be tested begins to delay the circuit control clock (having a period controlled by the trim bit) and the count of the internal clock of the integrated circuit to be tested. At step 2940, the low level reference pulse is sent from the test machine to the integrated circuit to be tested. In step 2950, in response to the low level reference pulse sent from the test machine, the integrated circuit to be tested ends the delay circuit control clock, and the number of counts of the internal clock transmitted from the integrated circuit to be tested is sent to the test machine. At step 2960, the tester determines if the number of counts at this time is greater than the target value of the number of clock counts. If not, then the pulse is too slow, then in step 2970 the tester determines that the trim bit in the integrated circuit to be tested or other delay circuit controlled by the reference current needs to be adjusted to speed up the clock. At step 2970, the increased value of the trim bit is stored in the test machine and the flow returns to step 2920. On the other hand, if in step 2960 the tester determines that the number of counts at this time is already greater than the target value of the number of clock counts, then in step 2980, the value of the trimmed bit increase is stored in the test machine.

Figure 30 shows a block diagram of a test system that automatically adjusts the delay time of a multi-delay block in a single set of pruning registers in an integrated circuit.

The test machine is coupled to the test integrated circuit. This test machine sends a test mode command to initialize the automatic trimming of this delay circuit. The tester also sends a high-level and low-level reference pulse to the integrated circuit to be tested to start or end the number of clocks in the delay circuit having a delay time controlled by the reference current. The current generator in the integrated circuit to be tested has a trim register to control the magnitude of the reference current. The integrated circuit to be tested also includes a counter responsive to a reference pulse from the test machine to count the clock.

Figure 31 shows the delay time relationship generated by different delay blocks under different process conditions.

The delay time generated by the delay circuit is simulated by the automatic test mode disclosed in Figs. 29 and 30 and simulated under different process conditions. The simulation results show that each delay circuit has the same performance under different processes such as NMOS threshold voltage variation, PMOS threshold voltage variation, and resistance value variation.

This delay time can be controlled in different ways. When the current mirror ratio is changed, for example, the individual widths of the individual current mirror transistors or the multiple current mirror transistors connected in parallel are changed. Further, it is also possible to change the capacitance value of the capacitor CX, for example, in FIG.

Figure 32 shows a circuit diagram of this current generating circuit that produces a current that controls the rate of charge and/or discharge between reference signals in a sequential circuit having a trim circuit.

The current generating circuit in Fig. 32 is similar to the current generating circuit in Fig. 3. However, the current generating circuit in Fig. 32 is an example having a trimming circuit. In this example, the trim signal T0~T3 of the self-trimming bit register changes the output current of the current mirror by turning on or off the transistor that controls the increased multi-element current in the current mirror output. An example application is the current generator in Figure 20.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

102‧‧‧Sequence circuit

104‧‧‧ level switching circuit

106‧‧‧Latch circuit

108‧‧‧Return signal

110‧‧‧clock signal

114‧‧‧ Current with charging and/or discharging switching between reference signals in a plurality of replica control sequential circuits

116‧‧‧ A circuit for generating a current for charging and/or discharging switching between reference signals in a sequential circuit

118‧‧‧current replication block

202A, 202B‧‧‧ sequential circuits

204A, 204B‧‧‧ inverter circuit

206‧‧‧Latch circuit

1700‧‧‧ integrated circuit

1712‧‧‧ memory cell array

1714‧‧‧Character line/block selection decoder and driver

1716‧‧‧ character line

1718‧‧‧ bit line decoder

1720‧‧‧ bit line

1722, 1726‧‧ ‧ busbar

1724‧‧‧Sense amplifier and data input structure

1728‧‧‧Data input line

1732‧‧‧ data output line

1736‧‧‧ bias adjustment supply voltage current source

1734‧‧‧ State Mechanism and Clock Circuit

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figure 1 shows a block diagram of a multi-version integrated circuit clock circuit having a current that produces a discharge and/or rate between two reference signals that control the timing circuit.

Figure 2 shows a circuit schematic of an integrated circuit clock circuit that can generate multiple versions of a current to control the rate of charge and/or discharge between the two reference signals in the sequential circuit.

Figure 3 is a schematic diagram of a current generator that produces a discharge and/or charge rate that controls switching between reference circuit reference signals.

Figure 4 is a schematic illustration of a current mirroring block that produces a current of a discharge and/or charging rate that is switched between reference signals that are replicated to control the timing circuit.

Figure 5 is a graph showing the relationship between time and OX or OY nodes for discharging and/or charging rates based on currents that control discharge and/or charging rate.

Fig. 6 is a graph showing the relationship between the time and the clock voltage outputted by the integrated circuit having the delay circuit.

Figure 7 shows the relationship between the clock cycle and the supply voltage at different temperatures.

Figure 8 shows the relationship between clock cycle and temperature at different supply voltages.

Figure 9 shows a circuit diagram of a temperature compensated current generator that does not have an adjustable temperature coefficient at a particular temperature in the temperature compensated current generator.

Figure 10 is a circuit diagram of a temperature compensated current generator (which is part of a current generating block) according to a first embodiment of the present invention, which has a temperature coefficient that can be adjusted according to a specific current value of the temperature compensating current generator .

11 is a circuit diagram of a temperature compensation current generator (which is a part of a current generating block) according to a second embodiment of the present invention, which has a temperature coefficient that can be adjusted according to a specific current value of the temperature compensation current generator .

Figure 12 is a circuit diagram of a temperature compensated current generator (which is part of a current generating block) according to a third embodiment of the present invention, which has a temperature coefficient that can be adjusted according to a specific current value of the temperature compensating current generator .

Figure 13 is a circuit diagram of a temperature compensated current generator (part of a current generating block) according to a first embodiment of the present invention in more detail, having a specific current value according to a temperature compensating current generator Adjust the temperature coefficient.

Figure 14 is a circuit diagram of a temperature compensated current generator (part of a current generating block) according to a second embodiment of the present invention in more detail, having a specific current value according to the temperature compensating current generator Adjust the temperature coefficient.

Figure 15 is a graph showing the relationship between temperature compensation current and temperature set by different circuits in accordance with the present invention.

Figure 16 is a block diagram showing a memory circuit of the present invention having an improved integrated circuit clock circuit.

Figure 17 is a block diagram of a delay circuit having a delay time determined by a reference current of the current generator.

Figure 18 is a block diagram of a multiple delay circuit having a delay time determined by a shared current generator.

Figure 19 is a block diagram of another multiple delay circuit having a delay time determined by a shared current generator.

Figures 20 through 23 show block diagrams of a delay circuit with a reference current from a current generator to determine the delay time.

Figures 24 to 27 show timing diagrams of the input and output voltage traces corresponding to the different delay circuits of Figures 20-23.

Figure 28 shows the relationship between temperature compensation and circuit power supply compensation delay time generated by different delay blocks.

Figure 29 shows a test flow diagram of a test machine that automatically adjusts the delay time for multiple delay blocks in a single set of trim registers in an integrated circuit.

Figure 30 shows a block diagram of a test system that automatically adjusts the delay time of a multi-delay block in a single set of pruning registers in an integrated circuit.

Figure 31 shows the delay time relationship generated by different delay blocks under different process conditions.

Figure 32 shows a circuit diagram of this current generating circuit that produces a current that controls the rate of charge and/or discharge between reference signals in a sequential circuit having a trim circuit.

102. . . Sequential circuit

104. . . Level switching circuit

106. . . Latch circuit

108. . . Feedback signal

110. . . Clock signal

114. . . Current having charging and/or discharging switching between reference signals in a plurality of replica control sequential circuits

116. . . Generating a circuit for controlling the charging and/or discharging current between reference signals in a sequential circuit

118. . . Current replica block

Claims (27)

A clock integrated circuit device comprising: an integrated circuit generating a clock signal, comprising: a sequential circuit having an output switched between reference signals; a current generating block having an output current at least controlled (i a rate of discharge between the reference signals, (ii) one of charging rates between the reference signals; a plurality of current mirroring blocks that produce a plurality of the output currents of the current generating block a version of the current that controls at least one of the discharge rate and the charge rate of the different portions of the sequential circuit; and a level switching circuit coupled to the output of the sequential circuit, the level switching circuit having Determining an output of the clock signal of the integrated circuit, wherein the output of the level switching circuit switches an output level and the output of the sequential circuit reaches a trigger point of the level switching circuit. The clock integrated circuit device of claim 1, wherein the timing circuit and the level switching circuit determine the output of the clock signal. The clock integrated circuit device of claim 1, wherein the output current of the current generating block comprises at least one of (i) a power compensation component and (ii) a temperature compensation component. The clock integrated circuit device of claim 1, wherein the output current of the current generating block comprises (i) a power compensation component having an adjustable power factor, and the power compensation component is The power supply is at least one of proportional, inverse or unrelated, and (ii) a temperature compensation component having an adjustable temperature coefficient, and the The temperature compensation component is at least one of proportional to temperature, inversely proportional or unrelated, at least one of the two. The clock integrated circuit device of claim 1, wherein the output current of the current generating block comprises at least a power compensation component having an adjustable power factor, and the power compensation component is formed by the power source. At least one of proportional, inverse or unrelated. The clock integrated circuit device of claim 1, wherein the output current of the current generating block has at least one temperature compensation component having an adjustable temperature coefficient, and the temperature compensation component is proportional to temperature At least one of the opposite or irrelevant. The clock integrated circuit device of claim 1, wherein the output current of the current generating block comprises (i) a temperature compensation component and (ii) a power compensation component having an adjustable power factor And the power compensation component is at least one of proportional to, proportional to, or unrelated to the power source. The clock integrated circuit device of claim 1, wherein the output current of the current generating block comprises (i) a power compensation component and (ii) a temperature compensation component having an adjustable temperature coefficient. And the temperature compensating component is at least one of proportional to temperature, inversely proportional, or unrelated. The clock integrated circuit device of claim 1, wherein the plurality of versions of the output current are respectively a ratio of the output current. The clock integrated circuit device of claim 1, further comprising: a latch circuit, receiving the output of the level switching circuit and generating the integrated circuit The clock signal, the latch circuit includes an interactively coupled logic gate such that an output of the alternately coupled logic gate in the latch circuit is coupled to an input of a logic gate coupled to the other of the latch circuits The latch circuit has a plurality of inputs coupled to different portions of the timing circuit. A method for generating a clock signal from an integrated circuit, comprising: switching an output of a sequential circuit between a plurality of reference signals; generating a current that controls at least (i) a discharge rate between the reference signals And (ii) one of charging rates for switching between the reference signals; generating a plurality of versions of the current of the current to control at least one of the discharge rate and the charging rate of different portions of the sequential circuit; And switching the output level of the level switching circuit and responding to the output of the timing circuit to a trigger point of the level switching circuit, an output of the level switching circuit determining the clock signal of the integrated circuit. The method of claim 11, wherein the timing circuit and the level switching circuit determine the output of the clock signal. The method of claim 11, wherein the current controls at least one of the discharge rate and the charging rate, comprising at least one of (i) a power compensation component and (ii) a temperature compensation component. The method of claim 11, wherein the current controls at least one of the discharge rate and the charging rate, comprising (i) a power compensation component having an adjustable power factor, and the power compensation component At least one of proportional to power supply, inversely proportional or unrelated, and (ii) a temperature compensating component having an adjustable temperature coefficient, and the temperature compensating component is at least one proportional to temperature, inversely proportional or irrelevant, At least one of the two. The method of claim 11, wherein the current control at least one of the discharge rate and the charging rate comprises at least a power compensation component having an adjustable power factor, and the power compensation component is The power supply is at least one of proportional, inverse, or unrelated. The method of claim 11, wherein the current controls at least one of the discharge rate and the charging rate, the at least one temperature compensating component having an adjustable temperature coefficient, and the temperature compensating component and temperature At least one of proportional, inverse or unrelated. The method of claim 11, wherein the current controls at least one of the discharge rate and the charging rate, comprising (i) a temperature compensation component and (ii) a power compensation component having an adjustable The power factor, and the power compensation component is at least one of proportional, inverse, or unrelated to the power source. The method of claim 11, wherein the current controls at least one of the discharge rate and the charging rate, comprising (i) a power compensation component and (ii) a temperature compensation component having an adjustable The temperature coefficient, and the temperature compensation component is at least one of proportional to, inversely proportional to, or unrelated to temperature. The method of claim 11, wherein the plurality of versions of current are respectively a ratio of the current that controls at least one of the discharge rate and the charge rate. The method of claim 11, further comprising: generating the clock signal of the integrated circuit having a latch receiving the level switching circuit, the latch comprising an interactively coupled logic gate, such that the plug The interaction in the lock The output of the logic gate is coupled to an input of another alternately coupled logic gate of the latch, the latch having a plurality of inputs coupled to different portions of the timing circuit. A clock integrated circuit device comprising: an integrated circuit generating a delayed signal, comprising: a delay circuit having an output switched between reference signals; a current generating block having an output current at least controlled (i a rate of discharge between the reference signals, (ii) one of charging rates between the reference signals; a current mirroring block that produces a version of the output current of the current generating block The current of the version controls at least one of the discharge rate and the charge rate of different portions of the sequential circuit; and a level switching circuit coupled to the output of the sequential circuit, the level switching circuit having the determined product One of the delayed signals of the body circuit outputs, wherein the output of the level switching circuit switches the output level and the output of the sequential circuit reaches a trigger point of the level switching circuit. The clock integrated circuit device of claim 21, wherein the integrated circuit generates a plurality of delayed signals including the delayed signal, and the device further comprises: a plurality of delay circuits generating the plurality of delayed signals, Each of the plurality of delay circuits includes: the delay circuit having an output that switches between reference signals; the current mirror block generating the version of the output current of the current generating block, the version The current is controlled by at least one of the discharge rate and the charge rate of the different portions of the sequential circuit; and the level switching circuit is coupled to the output of the sequential circuit, the level switching circuit having the plurality of delay signals determined The delay of the delay signal And wherein the output of the level switching circuit switches the output level and the output of the timing circuit reaches a trigger point of the level switching circuit. The clock integrated circuit device of claim 22, wherein the current mirror block of the plurality of delay circuits generates a version of the ratio of the output current of the current generating block, wherein the ratio of the output current The particular current magnitude of the version results in a corresponding delay time in the plurality of delayed signals. The clock integrated circuit device of claim 22, wherein the integrated circuit further comprises: a set of memory registers to control a magnitude of the output current of the current generating block. The clock integrated circuit device of claim 24, wherein the set of memory registers controls a delay time of the plurality of delayed signals generated by the plurality of delay circuits. The clock integrated circuit device of claim 24, wherein the integrated circuit has a test mode that outputs a total number of clock signal counts according to one of the set of memory register changes. The clock integrated circuit device of claim 24, wherein the integrated circuit has a test mode that varies the set of memory registers to compensate for different process conditions in the process.