CN107799136B - SONOS read sequence circuit - Google Patents
SONOS read sequence circuit Download PDFInfo
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- CN107799136B CN107799136B CN201711163472.9A CN201711163472A CN107799136B CN 107799136 B CN107799136 B CN 107799136B CN 201711163472 A CN201711163472 A CN 201711163472A CN 107799136 B CN107799136 B CN 107799136B
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- pmos
- nmos
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- time
- bypass current
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- Read Only Memory (AREA)
Abstract
The invention discloses a SONOS read timing circuit, which comprises: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and a capacitor; the first PMOS is connected with the first NMOS in series, and the second PMOS is connected with the second NMOS in series; the source electrodes of the first PMOS and the second PMOS are connected with a power supply; the grid electrodes of the first PMOS and the first NMOS are connected in parallel and then are connected with the input, and the serial node of the first PMOS and the first NMOS is connected with the grid electrodes of the second PMOS and the second NMOS; the serial node of the second PMOS and the second NMOS is an output port, and the source electrode of the second NMOS is grounded; one end of the capacitor is grounded, and the other end of the capacitor is connected with the grid electrodes of the second PMOS and the second NMOS; and the source electrode of the first NMOS is grounded through a bypass current source. The invention adopts the bypass current source with positive and negative temperature coefficients to redistribute the pre-charging time of the selected read unit and the time sequence of generating the comparison data '0' or '1' of the sensitive amplifier, thereby ensuring that the read sequence circuit can stably and effectively read the data at low temperature.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a SONOS read timing circuit of a nonvolatile memory.
Background
NVM (Non-volatile Memory), a Non-volatile Memory, has the characteristics of Non-volatility, access by bytes, high storage density, low energy consumption, and read-write performance close to DRAM. Electronic devices can quickly access the contents of the memory storage space (in most cases such devices access the contents in bytes and can also save them after power is lost). It does not periodically refresh the memory contents. This includes all forms of read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), and flash memory. It also includes battery-powered Random Access Memory (RAM).
A memory cell of a conventional SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, also called Silicon-oxynitride) device generally includes a SONOS memory transistor (referred to as a memory transistor for short) and a high voltage selection transistor (referred to as a selection transistor for short). The storage pipe is used for storing data, and the selection pipe is used for completing the selection of data addresses.
Fig. 1 is a read timing diagram of an NVM SONOS cell, wherein:
tcl, address setup time (setup time) selected to be read;
TPC is cell pre-charging time selected to be read;
tsa is the time for the sense amplifier to compare data "0" or "1";
tdy is the time required for the sense amplifier to latch and output the correct 0/1;
taa, one complete read cycle.
Wherein the longer the Tpc time, the worse the reading of "0"; tsa time becomes longer, reading either "0" or "1" would be beneficial;
the SONOS cell itself degrades by reading a "0" as the temperature decreases.
In summary, in the conventional circuit timing sequence, the 4-segment timing sequence is larger along with the temperature reduction, and since the reading of the "0" cell is weaker at low temperature, the longer time of the Tpc is more unfavorable for reading the "0".
Disclosure of Invention
The invention aims to provide a SONOS read timing circuit which has a temperature compensation function and enables the read circuit to work more stably.
To solve the above problems, the SONOS read timing sequence circuit according to the present invention includes:
the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and a capacitor;
the first PMOS is connected with the first NMOS in series, and the second PMOS is connected with the second NMOS in series;
the source electrodes of the first PMOS and the second PMOS are connected with a power supply;
the grid electrodes of the first PMOS and the first NMOS are connected in parallel and then are connected with the input, and the serial node of the first PMOS and the first NMOS is connected with the grid electrodes of the second PMOS and the second NMOS;
the serial node of the second PMOS and the second NMOS is an output port, and the source electrode of the second NMOS is grounded;
one end of the capacitor is grounded, and the other end of the capacitor is connected with the grid electrodes of the second PMOS and the second NMOS;
the source electrode of the first NMOS is grounded through a bypass current source;
the read timing current generates four timings during operation: the setup time Tcl for the address selected for reading, the precharge time Tpc for the cell selected for reading, the time Tsa for the sense amplifier to compare data "0" or "1", and one full read cycle Taa.
Further, the bypass current source can generate a negative temperature coefficient bypass current or a positive temperature coefficient bypass current.
Further, when generating the pre-charging time Tpc of the unit selected to be read, adopting a bypass current source with a negative temperature coefficient; a positive temperature coefficient bypass current source is used at time Tsa when the sense amplifier comparison data "0" or "1" is generated.
Furthermore, in a circuit generating the precharge time Tpc of the cell selected to be read and the time Tsa sequence of generating the comparison data "0" or "1" of the sensitive amplifier, the delay from the rising edge of the input signal to the rising edge of the output signal is realized by charging and discharging the capacitor through a bypass current source.
Further, the read timing is compensated by a bypass current source of positive and negative temperature coefficients, the precharge time Tpc of the cell selected for reading and the time Tsa timing for generating the sense amplifier comparison data "0" or "1" are redistributed, the precharge time Tpc of the cell selected for reading is designed to decrease as the temperature decreases, and the time Tsa of the sense amplifier comparison data "0" or "1" becomes larger as the temperature increases.
Further, the capacitor is a conventional capacitor, or is replaced by a MOS tube.
According to the SONOS read sequence circuit, when the pre-charging time Tpc of a unit selected to be read is generated, a bypass current source with a negative temperature coefficient is adopted; and a bypass current source with a positive temperature coefficient is adopted when the time Tsa of generating the comparison data '0' or '1' of the sensitive amplifier is generated, and the pre-charging time Tpc of the unit selected to be read and the time Tsa of generating the comparison data '0' or '1' of the sensitive amplifier are redistributed, so that the read sequence circuit can stably and effectively read data at low temperature.
Drawings
Fig. 1 is a read timing diagram of a prior SONOS read timing circuit.
Figure 2 is a read timing diagram compensated by the SONOS read timing circuit of the present invention.
FIG. 3 is a schematic diagram of a SONOS read timing circuit according to the present invention.
Detailed Description
Since the conventional SONOS read sequence circuit is weak in reading the "0" unit at low temperature, and the lengthening of the Tpc time is more unfavorable for reading the "0", the present invention proposes to redistribute the Tpc and Tsa at low temperature by using a temperature compensation method under the condition of fixed time Taa, and design the Tpc to be reduced along with the reduction of temperature, and simultaneously the Tsa to be increased along with the increase of temperature.
Based on the above technical idea, the SONOS read timing sequence circuit of the present invention includes:
the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and a capacitor;
the first PMOS is connected with the first NMOS in series, and the second PMOS is connected with the second NMOS in series;
the source electrodes of the first PMOS and the second PMOS are connected with a power supply;
the grid electrodes of the first PMOS and the first NMOS are connected in parallel and then are connected with the input, and the serial node of the first PMOS and the first NMOS is connected with the grid electrodes of the second PMOS and the second NMOS;
the serial node of the second PMOS and the second NMOS is an output port, and the source electrode of the second NMOS is grounded;
one end of the capacitor is grounded, and the other end of the capacitor is connected with the grid electrodes of the second PMOS and the second NMOS;
and the source electrode of the first NMOS is grounded through a bypass current source.
The bypass current source can generate a negative temperature coefficient bypass current or a positive temperature coefficient bypass current. When generating the pre-charging time Tpc of the unit selected to be read, adopting a bypass current source with a negative temperature coefficient; a positive temperature coefficient bypass current source is used at time Tsa when the sense amplifier comparison data "0" or "1" is generated.
And in the circuit generating the time series of the precharge time Tpc of the unit selected to be read and the time Tsa of generating the comparison data '0' or '1' of the sensitive amplifier, the delay from the rising edge of the input signal to the rising edge of the output signal is realized by charging and discharging the capacitor through the bypass current source.
The read timing is compensated by a bypass current source with positive and negative temperature coefficients, the precharge time Tpc of the cell selected to be read and the timing Tsa of the time for generating the sense amplifier comparison data "0" or "1" are redistributed, the precharge time Tpc of the cell selected to be read is designed to decrease with decreasing temperature, and the time Tsa of the sense amplifier comparison data "0" or "1" becomes larger with increasing temperature. The read sequence circuit can stably and effectively read data at low temperature.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A SONOS read timing circuit, comprising:
the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and a capacitor;
the first PMOS is connected with the first NMOS in series, and the second PMOS is connected with the second NMOS in series;
the source electrodes of the first PMOS and the second PMOS are connected with a power supply;
the grid electrodes of the first PMOS and the first NMOS are connected in parallel and then are connected with the input, and the serial node of the first PMOS and the first NMOS is connected with the grid electrodes of the second PMOS and the second NMOS;
the serial node of the second PMOS and the second NMOS is an output port, and the source electrode of the second NMOS is grounded;
one end of the capacitor is grounded, and the other end of the capacitor is connected with the grid electrodes of the second PMOS and the second NMOS;
the source electrode of the first NMOS is grounded through a bypass current source;
the read sequence circuit generates four sequences during operation: setup time Tcl for the address selected to be read, precharge time Tpc for the cell selected to be read, time Tsa for sense amplifier compare data "0" or "1", and one full read cycle Taa;
the bypass current source can generate a bypass current with a negative temperature coefficient or a bypass current with a positive temperature coefficient;
when generating the pre-charging time Tpc of the unit selected to be read, adopting a bypass current source with a negative temperature coefficient; a positive temperature coefficient bypass current source is used at time Tsa when the sense amplifier comparison data "0" or "1" is generated.
2. The SONOS read timing circuit of claim 1, wherein: and in the circuit generating the time series of the precharge time Tpc of the unit selected to be read and the time Tsa of generating the comparison data '0' or '1' of the sensitive amplifier, the delay from the rising edge of the input signal to the rising edge of the output signal is realized by charging and discharging the capacitor through the bypass current source.
3. The SONOS read timing circuit of claim 1, wherein: the read timing is compensated by a bypass current source with positive and negative temperature coefficients, the precharge time Tpc of the cell selected to be read and the timing Tsa of the time for generating the sense amplifier comparison data "0" or "1" are redistributed, the precharge time Tpc of the cell selected to be read is designed to decrease with decreasing temperature, and the time Tsa of the sense amplifier comparison data "0" or "1" becomes larger with increasing temperature.
4. The SONOS read timing circuit of claim 1, wherein: the capacitor is a conventional capacitor or is replaced by an MOS tube.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711163472.9A CN107799136B (en) | 2017-11-21 | 2017-11-21 | SONOS read sequence circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711163472.9A CN107799136B (en) | 2017-11-21 | 2017-11-21 | SONOS read sequence circuit |
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| CN107799136A CN107799136A (en) | 2018-03-13 |
| CN107799136B true CN107799136B (en) | 2021-01-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100440448B1 (en) * | 2002-04-12 | 2004-07-14 | 삼성전자주식회사 | Semiconductor integrated circuit device capable of securing time delay insensitive to temperature variation |
| CN101630532B (en) * | 2008-07-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | Sensitive amplifier used for electrically erasable read only memory and realization method thereof |
| CN103078607B (en) * | 2011-10-25 | 2015-02-18 | 旺宏电子股份有限公司 | Clock integrated circuit |
| CN102426851B (en) * | 2011-11-25 | 2014-02-19 | 中国科学院微电子研究所 | Read Timing Generation Circuit |
| CN104348457B (en) * | 2013-08-05 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Flash reads control circuit |
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