CN104348457A

CN104348457A - Flash read control circuit

Info

Publication number: CN104348457A
Application number: CN201310338010.1A
Authority: CN
Inventors: 刘芳芳; 姚翔
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-08-05
Filing date: 2013-08-05
Publication date: 2015-02-11
Anticipated expiration: 2033-08-05
Also published as: CN104348457B

Abstract

The invention discloses a Flash read control circuit. The Flash read control circuit comprises a clock signal generator, an adjustable delay module, a frequency dividing circuit and a read time sequence circuit, wherein the adjustable delay module comprises a first phase inverter and a second phase inverter; the first phase inverter is composed of a first PMOS (P-channel Metal Oxide Semiconductor) tube and a first NMOS (N-channel Metal Oxide Semiconductor) tube; the input end of the first phase inverter is connected with a clock signal; the second phase inverter is composed of a second PMOS tube and a second NMOS tube and outputs a delay signal; a third NMOS tube is connected between a source of the first NMOS tube and the ground; a fourth NMOS tube and a fifth NMOS tube are connected between the source of the first NMOS tube and the ground; gates of the third NMOS tube and the fifth NMOS tube are connected with the same offset; a gate of the fourth NMOS tube is connected with a delay adjusting signal to adjust delay by virtue of the delay adjusting signal. The delay time of a delay signal can be accurately adjusted, so that the establishment time and the establishment time margin can be accurately adjusted, and waste of a time sequence is avoided.

Description

Flash reads control circuit

Technical field

The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of Flash(flash memory) read control circuit.

Background technology

The signal that existing Flash reads control circuit generation is produced by clock sampling, and clock sampling needs certain settling time; Existing way will add between clock signal and sampled signal that a delay unit (delay cell) is used for ensureing the settling time of sampled signal.As shown in Figure 1, be the circuit diagram that existing Flash reads control circuit; Existing Flash reads control circuit and comprises:

Clock-signal generator 101, for generation of clock signal Tclk;

Delay unit 102, for generation of the time delayed signal Pclk of described clock signal;

Frequency dividing circuit 103, for generation of the fractional frequency signal Aclk of described clock signal;

Read sequence circuit 104, input connects described time delayed signal Pclk and described fractional frequency signal Aclk, export under the control of described time delayed signal Pclk and described fractional frequency signal Aclk and read clock signal, read clock signal to comprise: signal amplifies equalizing signal (Sense Amplifier Equiplirium, saeq), signal amplifies enable signal (Sense Amplifier Enable, saen) i.e. a saen1, signal amplifies enable signal two i.e. saen2.

As shown in Figure 2, it is the sequential chart that existing Flash reads control circuit, include in sequential chart: the sequential chart of clock signal Tclk, time delayed signal Pclk, described fractional frequency signal Aclk, saeq and saen2, has time delay tacs between the rising edge of clock signal Tclk and the rising edge of time delayed signal Pclk.Dotted line frame 105 is the rising edge of clock signal Tclk and the enlarged drawing of time delayed signal Pclk, can find out, the time delay tacs at each rising edge place of clock signal Tclk is fixing, and this time delay tacs size is determined by delay unit 102.

For initial stage design, for ensureing function and the performance of circuit, delay unit 102 leaves very large allowance after considering deviation.So, just there is following shortcoming: 1. delay unit 102 deviation and time delay tacs value are comparatively large, cause the waste of sequential; 2. can not precisely regulate settling time.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of Flash and reads control circuit, can the delay time of accurate adjustment time delayed signal, thus can accurate adjustment settling time and settling time allowance avoid the waste of sequential.

For solving the problems of the technologies described above, Flash provided by the invention reads control circuit and comprises:

Clock-signal generator, for generation of clock signal.

Adjustable delay module, for generation of the time delayed signal of described clock signal.

Frequency dividing circuit, for generation of the fractional frequency signal of described clock signal.

Read sequence circuit, input connects described time delayed signal and described fractional frequency signal, exports and read clock signal under the control of described time delayed signal and described fractional frequency signal.

Described adjustable delay module comprises:

The first inverter be made up of the first PMOS and the first NMOS tube, the source electrode of described first PMOS connects supply voltage, described first PMOS is connected with the drain electrode of described first NMOS tube, and described first PMOS is connected with the grid of described first NMOS tube and is connected described clock signal.

The second inverter be made up of the second PMOS and the second NMOS tube, the source electrode of described second PMOS connects supply voltage, described second PMOS is connected with the drain electrode of described second NMOS tube and exports described time delayed signal, described second PMOS is connected with the grid of described second NMOS tube and is connected the drain electrode of described first PMOS, the source ground of described second NMOS tube.

3rd NMOS tube, the drain electrode of described 3rd NMOS tube connects the source electrode of described first NMOS tube, and source ground, the grid of described 3rd NMOS tube connect the first bias voltage.

4th NMOS tube and the 5th NMOS tube, the drain electrode of described 4th NMOS tube connects the source electrode of described first NMOS tube, the source electrode of described 4th NMOS tube connects the drain electrode of described 5th NMOS tube, and the source ground of described 5th NMOS tube, the grid of described 5th NMOS tube connects described first bias voltage.

The grid of described 4th NMOS tube connects delay adjustment signal; Described delay adjustment signal is larger, and the source electrode of described first NMOS tube is larger to the electric current between ground, and the time delay between described time delayed signal and described clock signal is shorter; When the source voltage difference of described delay adjustment signal and described 4th NMOS tube is less than the threshold voltage of described 4th NMOS tube, the current branch of described 4th NMOS tube and described 5th NMOS tube composition is closed, the source electrode of described first NMOS tube is provided to the electric current between ground by the current branch of described 3rd NMOS tube, and the time delay between described time delayed signal and described clock signal is maximum.

Further improvement is, described adjustable delay module also comprises the 6th NMOS tube connecting into capacitance structure, and the grid of described 6th NMOS tube connects the drain electrode of described first PMOS, the source electrode of described 6th NMOS tube and all ground connection that drains.

The present invention, by the setting of adjustable delay module, can realize the accurate adjustment of the delay time of time delayed signal by delay adjustment signal, thus can accurate adjustment settling time and settling time allowance avoid the waste of sequential.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is the circuit diagram that existing Flash reads control circuit;

Fig. 2 is the sequential chart that existing Flash reads control circuit;

Fig. 3 is the circuit diagram that embodiment of the present invention Flash reads control circuit;

Fig. 4 is the circuit diagram of embodiment of the present invention adjustable delay module;

Fig. 5 is the sequential chart that embodiment of the present invention Flash reads control circuit.

Embodiment

As shown in Figure 3, be the circuit diagram that embodiment of the present invention Flash reads control circuit; Embodiment of the present invention Flash reads control circuit and comprises:

Clock-signal generator 1, for generation of clock signal Tclk.

Adjustable delay module 2, for generation of the time delayed signal Pclk of described clock signal Tclk.

Frequency dividing circuit 3, for generation of the fractional frequency signal Aclk of described clock signal Tclk.

Read sequence circuit 4, input connects described time delayed signal Pclk and described fractional frequency signal Aclk, exports and read clock signal under the control of described time delayed signal Pclk and described fractional frequency signal Aclk, described in read clock signal and comprise signal Saeq and Saen2.

As shown in Figure 4, be the circuit diagram of embodiment of the present invention adjustable delay module 2; Described adjustable delay module 2 comprises:

The first inverter be made up of the first PMOS MP1 and the first NMOS tube MN1, the source electrode of described first PMOS MP1 meets supply voltage Vpwr, described first PMOS MP1 is connected with the drain electrode of described first NMOS tube MN1, and described first PMOS MP1 is connected with the grid of described first NMOS tube MN1 and is connected described clock signal Tclk.

The second inverter be made up of the second PMOS MP2 and the second NMOS tube MN2, the source electrode of described second PMOS MP2 meets supply voltage Vpwr, described second PMOS MP2 is connected with the drain electrode of described second NMOS tube MN2 and exports described time delayed signal, described second PMOS MP2 is connected with the grid of described second NMOS tube MN2 and is connected the drain electrode of described first PMOS MP1, the source ground Vgnd of described second NMOS tube MN2.

The drain electrode of the 3rd NMOS tube MN3, described 3rd NMOS tube MN3 connects the source electrode of described first NMOS tube MN1, and source ground Vgnd, the grid of described 3rd NMOS tube MN3 meet the first bias voltage Vbias.

4th NMOS tube MN4 and the 5th NMOS tube MN5, the drain electrode of described 4th NMOS tube MN4 connects the source electrode of described first NMOS tube MN1, the source electrode of described 4th NMOS tube MN4 connects the drain electrode of described 5th NMOS tube MN5, the grid of the source ground Vgnd of described 5th NMOS tube MN5, described 5th NMOS tube MN5 meets described first bias voltage Vbias.

The grid of described 4th NMOS tube MN4 connects delay adjustment signal Trim<n:0>; Described delay adjustment signal Trim<n:0> is larger, and the source electrode of described first NMOS tube MN1 is larger to the electric current between ground Vgnd, and the time delay between described time delayed signal Pclk and described clock signal Tclk is shorter; When the source voltage difference of described delay adjustment signal Trim<n:0> and described 4th NMOS tube MN4 is less than the threshold voltage of described 4th NMOS tube MN4, the current branch of described 4th NMOS tube MN4 and described 5th NMOS tube MN5 composition is closed, the source electrode of described first NMOS tube MN1 is provided to the electric current between ground Vgnd by the current branch of described 3rd NMOS tube MN3, and the time delay between described time delayed signal Pclk and described clock signal Tclk is maximum.

Described adjustable delay module 2 also comprises the 6th NMOS tube connecting into capacitance structure, and the grid of described 6th NMOS tube connects the drain electrode of described first PMOS MP1, the source electrode of described 6th NMOS tube and all ground connection Vgnd that drains.

As shown in Figure 5, be the sequential chart that embodiment of the present invention Flash reads control circuit.Include in sequential chart: the sequential chart of clock signal Tclk, time delayed signal Pclk, described fractional frequency signal Aclk, saeq and saen2, has time delay tacs between the rising edge of clock signal Tclk and the rising edge of time delayed signal Pclk.Dotted line frame 5 is the rising edge of clock signal Tclk and the enlarged drawing of time delayed signal Pclk, can find out, by described delay adjustment signal Trim<n:0> is set to different value, the time delay tacs at the rising edge place of corresponding clock signal Tclk adjusts accordingly, and the time delay tacs0 as first rising edge place of clock signal Tclk is greater than the time delay tacs1 at second rising edge place.So the embodiment of the present invention can realize the accurate adjustment of the time delay tacs time of time delayed signal Pclk by delay adjustment signal Trim<n:0>, thus can accurate adjustment settling time and settling time allowance avoid the waste of sequential.

Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. Flash reads a control circuit, it is characterized in that, comprising:

Clock-signal generator, for generation of clock signal;

Adjustable delay module, for generation of the time delayed signal of described clock signal;

Frequency dividing circuit, for generation of the fractional frequency signal of described clock signal;

Read sequence circuit, input connects described time delayed signal and described fractional frequency signal, exports and read clock signal under the control of described time delayed signal and described fractional frequency signal;

Described adjustable delay module comprises:

The first inverter be made up of the first PMOS and the first NMOS tube, the source electrode of described first PMOS connects supply voltage, described first PMOS is connected with the drain electrode of described first NMOS tube, and described first PMOS is connected with the grid of described first NMOS tube and is connected described clock signal;

The second inverter be made up of the second PMOS and the second NMOS tube, the source electrode of described second PMOS connects supply voltage, described second PMOS is connected with the drain electrode of described second NMOS tube and exports described time delayed signal, described second PMOS is connected with the grid of described second NMOS tube and is connected the drain electrode of described first PMOS, the source ground of described second NMOS tube;

3rd NMOS tube, the drain electrode of described 3rd NMOS tube connects the source electrode of described first NMOS tube, and source ground, the grid of described 3rd NMOS tube connect the first bias voltage;

4th NMOS tube and the 5th NMOS tube, the drain electrode of described 4th NMOS tube connects the source electrode of described first NMOS tube, the source electrode of described 4th NMOS tube connects the drain electrode of described 5th NMOS tube, the source ground of described 5th NMOS tube, and the grid of described 5th NMOS tube connects described first bias voltage;

2. Flash reads control circuit as claimed in claim 1, it is characterized in that: described adjustable delay module also comprises the 6th NMOS tube connecting into capacitance structure, the grid of described 6th NMOS tube connects the drain electrode of described first PMOS, the source electrode of described 6th NMOS tube and all ground connection that drains.