CN107734375B - Video source synchronous clock generation method and device - Google Patents
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
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Abstract
The embodiment of the invention discloses a kind of video source synchronous clock generation methods, comprising: extracts the synchronizing information of multiple video sources respectively to obtain Multi-path synchronous information；It is selected from the Multi-path synchronous information all the way as first object synchronizing information；Generate customized synchronizing information；It is selected from the first object synchronizing information and the customized synchronizing information all the way as the second object synchronization information, wherein the second object synchronization information is for generating more video source synchronizing clock signals.The invention also discloses a kind of video source synchronous clock generation apparatus.Precise synchronization and better video treatment effect between different video source may be implemented in the present invention.
Description
Technical Field
The present invention relates to the field of video processing and display technologies, and in particular, to a method and an apparatus for generating a video source synchronization clock.
Background
In video processing apparatuses, the kinds of input video sources are increasing. When the processing device performs synchronous processing on a plurality of video sources, whether the used processing clocks are synchronous or not is often a crucial role. The non-uniformity of the synchronization signals in the video source synchronization process easily causes the problem of inconsistent processing clocks, thereby causing a series of video processing defects, such as poor video processing effect caused by processing clock deviation.
Disclosure of Invention
Embodiments of the present invention provide a video source synchronization clock generation method and a video source synchronization clock generation apparatus, which can achieve accurate synchronization between different video sources and a better video processing effect.
The embodiment of the invention provides a method for generating a video source synchronous clock, which comprises the following steps: respectively extracting the synchronous information of a plurality of video sources to obtain multi-path synchronous information; selecting one path from the multi-path synchronous information as first target synchronous information; generating self-defined synchronous information; and selecting one path from the first target synchronous information and the custom synchronous information as second target synchronous information, wherein the second target synchronous information is used for generating synchronous clock signals for multiple video sources.
In an embodiment of the present invention, the extracting synchronization information of a plurality of video sources to obtain multiple paths of synchronization information includes: acquiring multiple paths of decoded information obtained by respectively decoding the video signals of the multiple video sources, wherein each path of decoded information comprises synchronous information and video data; and respectively extracting the synchronous information from the multi-channel decoded information to obtain the multi-channel synchronous information.
In an embodiment of the present invention, the generating the custom synchronization information includes: controlling a phase-locked loop module to generate a logic code control clock signal; and generating a path of the self-defined synchronous information based on the logic code control clock signal and the control information.
In one embodiment of the present invention, the video source synchronization clock generating method further comprises: generating a synchronous clock signal for a multi-video source according to the second target synchronous information; and sending the synchronous clock signals to a plurality of back-end processing modules so as to synchronously process the multiple video sources.
In an embodiment of the present invention, any one of the multiple paths of synchronization information and the custom synchronization information includes field synchronization information and line synchronization information.
An embodiment of the present invention further provides a video source synchronous clock generating apparatus, including: the synchronous information extraction module group is used for respectively extracting the synchronous information of a plurality of video sources to obtain multi-channel synchronous information; the first selection module is used for selecting one path from the multi-path synchronous information as first target synchronous information; the user-defined synchronous information generating module is used for generating user-defined synchronous information; and the second selection module is used for selecting one path from the first target synchronization information and the custom synchronization information as second target synchronization information, wherein the second target synchronization information is used for generating a synchronous clock signal for multiple video sources.
In one embodiment of the present invention, the video source synchronous clock generating apparatus further comprises: the decoder group is used for decoding the video signals of the video sources respectively to obtain a plurality of paths of decoded information, wherein each path of decoded information comprises synchronous information and video data; and the synchronous information extraction module group is used for extracting synchronous information from the multi-channel decoded information respectively so as to obtain the multi-channel synchronous information.
In one embodiment of the present invention, the video source synchronous clock generating apparatus further comprises: and the clock signal generating module is used for generating synchronous clock signals for multiple video sources according to the second target synchronous information and sending the synchronous clock signals for the multiple video sources to the multiple back-end processing modules so as to synchronously process the multiple video sources.
In an embodiment of the present invention, any one of the multiple paths of synchronization information and the custom synchronization information includes field synchronization information and line synchronization information.
In an embodiment of the present invention, the custom synchronization information generating module includes: the phase-locked loop module is used for generating a clock signal for controlling logic codes; and the synchronous information generation module is used for generating one path of the self-defined synchronous information based on the logic code control clock signal and the control signal.
In an embodiment of the present invention, the synchronization information extraction module group, the first selection module, the custom synchronization information generation module, and the second selection module are integrated in a programmable logic device.
The above technical solution may have one or more of the following advantages: the embodiment of the invention obtains multi-channel synchronous information by extracting the synchronous information of a plurality of video sources, generates user-defined synchronous information required by a user based on a control signal provided by the user, selects one channel of synchronous information from the multi-channel synchronous information for the first time based on the user requirement as first target synchronous information, selects one channel of synchronous information from the first target synchronous information and the user-defined synchronous information for the second time based on the user requirement as second target synchronous information, and finally generates a synchronous clock signal for the multi-video source for synchronous processing of the multi-video source according to the obtained second target synchronous information, thereby realizing that the synchronous information meeting the user requirement is obtained by two-stage selection under the control of the control information provided by the user, and providing a high-efficiency multi-video source synchronous clock generating method which is easy for the user to independently control, the problem of inconsistent clocks caused by non-uniform synchronous signals in video source synchronous processing is solved, and a series of video processing defects caused by clock problems are reduced.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for generating a video source synchronization clock according to an embodiment of the present invention;
FIG. 2A is a schematic diagram of a video source synchronous clock generating apparatus according to another embodiment of the present invention;
fig. 2B is a detailed structural diagram of the video source synchronous clock generating apparatus in fig. 2A.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a method for generating a video source synchronization clock according to an embodiment of the present invention mainly includes:
s11, respectively extracting the synchronous information of a plurality of video sources to obtain multi-path synchronous information;
s13, selecting one path from the multi-path synchronous information as first target synchronous information; specifically, step S13 is, for example, a selection performed under the control of a first control signal provided by a user, so as to obtain first target synchronization information meeting the user requirement, where the selection process is, for example, implemented by a selector with a one-out-of-multiple function, it is foreseeable that, when the number of the multiple video sources is N, the corresponding selector needs to be capable of implementing a function of selecting 1 from M, where M > is N, and M and N are positive integers greater than or equal to 2;
s15, generating self-defined synchronous information; specifically, the customized synchronization information is generated under the control of a second control signal and a third control signal provided by a user, for example, so as to obtain the customized synchronization information meeting the user requirements;
and S17, selecting one path from the first target synchronous information and the custom synchronous information as second target synchronous information, wherein the second target synchronous information is used for generating synchronous clock signals for multiple video sources. Specifically, step S17 is, for example, a selection performed under the control of a fourth control signal provided by the user, so as to obtain second target synchronization information meeting the user requirement, where the selection process is, for example, implemented by a selector with a multiple-to-one function, and it is expected that, when the first target synchronization information and the custom synchronization information each include one path of synchronization information, the corresponding selector needs to be able to implement an L-to-1 function, where L > is 2, and L is a positive integer greater than or equal to 2.
Specifically, step S11 includes, for example, the steps of:
acquiring multiple paths of decoded information obtained by respectively decoding the video signals of the multiple video sources, wherein each path of decoded information comprises synchronous information and video data;
and respectively extracting the synchronous information from the multi-channel decoded information to obtain the multi-channel synchronous information.
Step S15 includes, for example, the steps of:
controlling a phase-locked loop module to generate a logic code control clock signal; specifically, the logic code control clock signal is generated, for example, in a case where the second control signal is an input signal for controlling the phase-locked loop module;
and generating one path of the self-defined synchronous information based on the clock signal for controlling the logic code and the third control signal. Finally, the function of generating the custom synchronization information meeting the user requirements according to the customization of the user can be realized through the second control signal and the third control signal. It is worth mentioning here that in other embodiments, the customized synchronization information may include multiple paths of customized synchronization information according to the user's needs, for example.
Further, the video source synchronous clock generating method, for example, after the step S17, further includes the steps of:
generating a synchronous clock signal for a multi-video source according to the second target synchronous information;
and sending the synchronous clock signals for the multiple video sources to a plurality of back-end processing modules so as to synchronously process the multiple video sources.
And any one of the multi-channel synchronous information and the custom synchronous information comprises field synchronous information VS and line synchronous information HS. Which information is specifically contained depends on the processing power and requirements of the system. The first control signal, the second control signal, the third control signal and the fourth control signal are signals obtained by an interactive mode that a customer operates a button of a corresponding function according to the requirement of the customer or inputs corresponding information on an input interface. All or part of the steps S11, S13, S15 and S17 are implemented by, for example, logic modules of a programmable logic device such as an FPGA, or by a specific physical circuit.
In summary, the embodiment of the invention generates the user-defined synchronization information required by the user according to the control signal provided by the user, and selecting one path of the multi-path synchronous information corresponding to the plurality of video sources as first target synchronous information by making a first selection according to a control signal provided by a user, and then, second selection is carried out, namely, one of the first target synchronous information and the custom synchronous information is selected as the second target synchronous information according to the control signal provided by the user, so that the synchronous signal meeting the user requirement is obtained through two-stage selection under the action of the control information provided by the user, an efficient video source synchronous clock generation method easy for the user to independently control is provided, the problem of clock inconsistency caused by the fact that the synchronous signals are not uniform in video source synchronous processing is solved, and a series of video processing defects caused by the clock problem are reduced.
As shown in fig. 2A and 2B, another embodiment of the present invention provides a video source synchronous clock generating device 10, which mainly includes: the system comprises a synchronization information extraction module group 11, a first selection module 12, a custom synchronization information generation module 13 and a second selection module 14. The synchronization information extraction module group 11 is configured to extract synchronization information of a plurality of video sources respectively to obtain multiple paths of synchronization information, where the plurality of video sources include, for example, video source 1, video source 2, video source 3, and video source 4, and correspondingly, the multiple paths of synchronization information include, for example, 4 paths, and the 4 paths of synchronization information respectively correspond to the video source 1, the video source 2, the video source 3, and the video source 4; the first selection module 12 is configured to select one path from the multiple paths of synchronization information as first target synchronization information according to a first control signal; the custom synchronization information generating module 13 is configured to generate custom synchronization information according to the second control signal and the third control signal; the second selecting module 14 is configured to select one path from the first destination synchronization information and the custom synchronization information as second destination synchronization information according to a fourth control signal, where the second destination synchronization information is used to generate a synchronization clock signal for a multi-video source. It should be noted that the plurality of video sources are not limited to include 4 video sources, and may be any video sources not less than 2 in other embodiments as required; the first control signal, the second control signal, the third control signal and the fourth control signal are signals obtained by an interactive mode that a customer operates a button of a corresponding function according to the requirement of the customer or inputs corresponding information on an input interface. Specifically, the selection function of the first selection module 12 is implemented by, for example, a selector with a one-out-of-multiple function, and it is desirable that the selector is capable of implementing a 1-out-of-M function, where when the number of the multiple video sources is N, the corresponding selector is capable of implementing a 1-out-of-M function, where M > ═ N, and M and N are positive integers greater than or equal to 2; for example, in the present embodiment, the number of video sources is 4, and accordingly, M > -4; similarly, it is also foreseen that, when the first target synchronization information and the custom synchronization information each include one path of synchronization information, the selection function of the second selection module 14 is implemented by a selector with an L-select-1 function, for example, where L > is 2, and L is a positive integer greater than or equal to 2.
Further, the video source synchronization clock generating apparatus 10, for example, further includes: a decoder group 15, where the decoder group 15 includes, for example, a decoder 151, a decoder 153, a decoder 155, and a decoder 157, and the decoder 151, the decoder 153, the decoder 155, and the decoder 157 decode video signals of a video source 1, a video source 2, a video source 3, and a video source 4 respectively to obtain multiple paths of decoded information, where each path of decoded information includes synchronization information and video data; the synchronization information extraction module group 11 includes a synchronization information extraction module 111, a synchronization information extraction module 113, a synchronization information extraction module 115, and a synchronization information extraction module 117, which are respectively configured to extract synchronization information from the 4 decoded information channels to obtain 4 synchronization information channels corresponding to video source 1, video source 2, video source 3, and video source 4, respectively. Specifically, the number of the decoders, the number of the synchronization information extraction modules, and the number of the video sources are the same, and a one-to-one correspondence relationship is formed among the decoders, the synchronization information extraction modules, and the video sources; for example, in this embodiment, video source 1, decoder 151 and synchronization information extraction module 111 form a path in a one-to-one correspondence manner, video source 2, decoder 153 and synchronization information extraction module 113 form a path in a one-to-one correspondence manner, video source 3, decoder 155 and synchronization information extraction module 115 form a path in a one-to-one correspondence manner, and video source 4, decoder 157 and synchronization information extraction module 117 form a path in a one-to-one correspondence manner.
Further, the video source synchronization clock generating apparatus 10, for example, further includes: a clock signal generating module 16, wherein the clock signal generating module 16 is configured to generate a synchronous clock signal for multiple video sources according to the second target synchronization information and send the synchronous clock signal for multiple video sources to the multiple back-end processing modules 20 for synchronous processing of multiple video sources. The number of the back-end processing modules 20 is not limited to 3 shown in fig. 2B, and may be any positive integer greater than or equal to 2.
The custom synchronization information generation module 13 includes, for example: the phase-locked loop module 131, the phase-locked loop module 131 is configured to generate a logic code control clock signal according to the second control signal; and a synchronization information generating module 133, where the synchronization information generating module 133 is configured to generate one path of the customized synchronization information based on the clock signal for logic code control and the third control signal. Finally, the function of generating the custom synchronization information meeting the user requirements according to the customization of the user can be realized through the second control signal and the third control signal. It is worth mentioning here that in other embodiments, the customized synchronization information may include multiple paths of customized synchronization information according to the user's needs, for example.
The clock signal generation module 16 includes, for example, a clock generation chip GS 4911B. The synchronization information extraction module 11, the first selection module 12, the custom synchronization information generation module 13, and the second selection module 14 are, for example, integrated in a programmable logic device such as an FPGA, and are implemented by a logic module of the FPGA, and in other embodiments, the synchronization information extraction module 11, the first selection module 12, the custom synchronization information generation module 13, and the second selection module 14 may also be implemented by a specific physical circuit. . Any one of the multiple paths of synchronization information and the custom synchronization information includes, for example, field synchronization information VS and line synchronization information HS, which depend on the processing capability and requirements of the clock generation chip used by the clock signal generation module 16, and the clock generation chip GS4911B used in this embodiment needs the field synchronization information VS and the line synchronization information HS. The function of the clock generation chip GS4911B is to generate corresponding standard clock signals according to the input VS and HS information, and the generated clock can be supported to 165 MHz. It should be noted that in other embodiments, the GS4911B may be replaced by another clock generation chip, and the chip may be used as a substitute chip as long as it can generate an accurate clock under the condition of completing the input VS and HS signals.
The following describes a specific process of extracting synchronization information of the video source 1 by taking the video source 1 as an example:
firstly, a video signal of a video source 1 is input into a decoder 151 corresponding to the video source 1 and decoded to obtain decoded information containing synchronization information and video data of the corresponding video source 1; then, the decoded information corresponding to the video source 1 is sent to the synchronization information extraction module 111 corresponding to the video source 1 to extract the synchronization information, so as to obtain the field synchronization information VS and the line synchronization information HS corresponding to the video source 1. The synchronization information extraction process corresponding to video source 2, video source 3, and video source 4 refers to video source 1.
The specific working principle of the embodiment of the invention is as follows:
first, first target synchronization information and custom synchronization information are acquired. The specific process of acquiring the first target synchronization information comprises the following steps: the synchronization information of the plurality of video sources is respectively acquired, then the synchronization information of the plurality of video sources is sent to the first selection module 12, and then the first selection module 12 is controlled by the first control signal to perform first selection, one of the video sources is selected by using a one-out-of-multiple function, namely the synchronization information of one video source selected by the user through the first control signal is output as first target synchronization information. The specific process of obtaining the custom synchronization information comprises the following steps: the clock signal for controlling logic code required by the user is obtained through the phase-locked loop module 131 according to the third control signal provided by the user, and then the synchronization information generating module 133 is controlled according to the clock signal for controlling logic code and the second control signal provided by the user to generate the synchronization information required by the user, that is, the self-defined synchronization information. Wherein the synchronization information generation module 133 is implemented by logic code stored inside a programmable logic device, such as an FPGA, for example. It can be known that the customized synchronization information is the specific synchronization information required by the user and generated by the customized synchronization information generation module 13 according to the third control signal and the fourth control signal provided by the user, and therefore, the customized synchronization information is not dependent on the video source.
Then, second target synchronization information is acquired. The specific process is as follows: the first target synchronization information and the custom synchronization information are input into the second selection module 14, and the second selection module 14 performs second selection under the control of a fourth control signal provided by the user, and selects one of the first target synchronization information and the custom synchronization information as the second target synchronization information according to the user requirement by using a one-out-of-multiple function.
Then, a synchronous clock signal for a multi-video source is generated. The specific process is as follows: the clock generation chip GS4911B in the clock signal generation module 16 generates the synchronous clock signal for the multiple video sources finally required by the user according to the second target synchronization information. Since the multi-video source synchronization clock signal is finally output by the dedicated clock generation chip GS4911B, and the second destination synchronization information obtained by the clock generation chip GS4911B is the unique synchronization information selected by the client through the fourth control signal, the generated multi-video source synchronization clock signal is only related to the unique synchronization information, that is, the second destination synchronization information, and is not necessarily linked to each video source clock of the front-end circuit, so that the independence of the multi-video source synchronization clock signal finally output by the dedicated clock generation chip GS4911B can be improved.
Finally, the synchronous clock signals for the multiple video sources are uniformly distributed to the back-end processing modules 20, and a uniform clock signal is provided for them. In the distribution process, errors among paths through which the synchronous clock signals for the multiple video sources pass are negligible, so that clock consistency of each back-end processing module receiving the synchronous clock signals for the multiple video sources is guaranteed.
In summary, in the embodiment of the present invention, under the control of the first control signal, the second control signal, the third control signal, and the fourth control signal provided by the user, the first selection module 12 selects the synchronization information of one video source as the first target synchronization information, and the second selection module 14 selects one of the first target synchronization information and the customized synchronization information as the final second target synchronization information, that is, the required second target synchronization information is obtained by sequentially performing a second selection, so as to generate the synchronization clock signals for multiple video sources according to the selected second target synchronization information and provide the synchronization clock signals for each back-end processing module 20 for use, thereby finally realizing a video source synchronization clock generation apparatus with high efficiency and easy autonomous control by the user, and solving the problem of clock inconsistency caused by non-unity of the synchronization signals in video source synchronization processing, a series of video processing defects caused by clock problems are reduced.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and/or method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units/modules is only one logical division, and there may be other divisions in actual implementation, for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units/modules described as separate parts may or may not be physically separate, and parts displayed as units/modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
The integrated units/modules, which are implemented in the form of software functional units/modules, may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A method for video source synchronous clock generation, comprising:
respectively extracting the synchronous information of a plurality of video sources to obtain multi-path synchronous information;
selecting one path from the multi-path synchronous information as first target synchronous information;
generating self-defined synchronous information;
selecting one path from the first target synchronous information and the custom synchronous information as second target synchronous information, wherein the second target synchronous information is used for generating synchronous clock signals for multiple video sources,
wherein,
the generating the custom synchronization information comprises:
controlling a phase-locked loop module to generate a logic code control clock signal;
and generating a path of the self-defined synchronous information by using a clock signal and a control signal based on the logic code control.
2. The video source synchronous clock generating method as claimed in claim 1, wherein said extracting synchronization information of a plurality of video sources to obtain multi-path synchronization information comprises:
acquiring multiple paths of decoded information obtained by respectively decoding the video signals of the multiple video sources, wherein each path of decoded information comprises synchronous information and video data;
and respectively extracting the synchronous information from the multi-channel decoded information to obtain the multi-channel synchronous information.
3. The video source synchronous clock generating method as claimed in claim 1, further comprising:
generating a synchronous clock signal for a multi-video source according to the second target synchronous information;
and sending the synchronous clock signals for the multiple video sources to a plurality of back-end processing modules so as to synchronously process the multiple video sources.
4. The video source synchronous clock generating method of claim 1, wherein any one of the plurality of pieces of synchronization information and the custom synchronization information comprises field synchronization information and line synchronization information.
5. A video source synchronous clock generating apparatus, comprising:
the synchronous information extraction module group is used for respectively extracting the synchronous information of a plurality of video sources to obtain multi-channel synchronous information;
the first selection module is used for selecting one path from the multi-path synchronous information as first target synchronous information;
the user-defined synchronous information generating module is used for generating user-defined synchronous information;
a second selection module, configured to select one path from the first destination synchronization information and the custom synchronization information as second destination synchronization information, where the second destination synchronization information is used to generate a synchronization clock signal for multiple video sources,
wherein,
the custom synchronization information generation module comprises:
the phase-locked loop module is used for generating a clock signal for controlling logic codes; and
and the synchronous information generation module is used for generating one path of the self-defined synchronous information based on the logic code control clock signal and the control signal.
6. The video source synchronous clock generating apparatus as claimed in claim 5, further comprising: the decoder group is used for decoding the video signals of the video sources respectively to obtain a plurality of paths of decoded information, wherein each path of decoded information comprises synchronous information and video data;
and the synchronous information extraction module group is used for extracting synchronous information from the multi-channel decoded information respectively so as to obtain the multi-channel synchronous information.
7. The video source synchronous clock generating apparatus as claimed in claim 5, further comprising:
and the clock signal generating module is used for generating synchronous clock signals for multiple video sources according to the second target synchronous information and sending the synchronous clock signals for the multiple video sources to the multiple back-end processing modules so as to synchronously process the multiple video sources.
8. The video source synchronous clock generating apparatus of claim 5, wherein any of the plurality of pieces of synchronization information and the custom synchronization information comprises field synchronization information and line synchronization information.
9. The video source synchronous clock generating apparatus of claim 5, wherein the synchronization information extraction module, the first selection module, the custom synchronization information generation module, and the second selection module are integrated into a programmable logic device.
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| JP5194564B2 (en) * | 2007-05-29 | 2013-05-08 | ソニー株式会社 | Image processing apparatus and method, program, and recording medium |
| CN101615906B (en) * | 2008-10-28 | 2012-10-03 | 东莞理工学院 | Clock-synchronization digital phase-locking method and device |
| CN102740061B (en) * | 2012-06-14 | 2014-07-16 | 北京蛙视通信技术有限责任公司 | High-definition optical transceiver and multimedia video digital signal processing method |
| CN103986462B (en) * | 2014-05-30 | 2017-01-04 | 中国电子科技集团公司第五十八研究所 | Possesses the Fast Frequency Estimation circuit of high-speed interface |
| CN105653748B (en) * | 2014-11-14 | 2019-03-08 | 京微雅格（北京）科技有限公司 | A kind of distribution method and Clock Tree framework of Clock Tree resource |
| CN104469462B (en) * | 2014-12-03 | 2017-12-12 | 成都德芯数字科技股份有限公司 | A kind of digital video signal processing system and method |
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