CN112637443B - Source synchronous phase locking method, device, system and plug-in card type video processing equipment - Google Patents
Source synchronous phase locking method, device, system and plug-in card type video processing equipment Download PDFInfo
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Abstract
The embodiment of the invention discloses a source synchronous phase locking method, a device and a system and plug-in card type video processing equipment, wherein the source synchronous phase locking method comprises the following steps: receiving a source synchronous phase-locked mapping relation table; selecting a target synchronous signal from a plurality of synchronous signals according to a source synchronous phase-locked mapping relation table and outputting the target synchronous signal to a target synchronous signal input interface of a target output device, so that the target synchronous signal is used as a reference synchronous signal of an output video source corresponding to the target synchronous signal input interface; the plurality of synchronous signals comprise synchronous signals of an input video source of at least one input device and synchronous signals of an output video source of at least one output device, and the target output device belongs to the at least one output device. The invention solves the problem of complex system wiring caused by the need of connecting the input device corresponding to each input video source with the output device corresponding to each output video source.
Description
Technical Field
The present invention relates to the field of signal synchronization technologies, and in particular, to a method, an apparatus, a system, and a card-inserted video processing device for source synchronization phase locking.
Background
In the field of video processing, when a device outputs a video stream, it needs to keep synchronization with an input video source or an externally accessed video source, where synchronization refers to that a field signal of the output video stream keeps synchronization with a field signal of the input video source or the externally accessed video source, and the output video stream keeps consistent with the input video stream at an output frame rate from a macroscopic view, and keeps synchronization on a picture, which is called a genlock (genlock) function.
Referring to fig. 1, in the conventional genlock implementation, vs (field signal) of an external input video source is generally introduced into an FPGA through a GPIO of the FPGA, and the FPGA is internally provided with an internal adjusting module, so that the field signal of an output video stream is consistent with the field signal of the input external source, and the genlock function of the external source is realized. The function of the internal adjusting module is that: when the output video field signal is ahead of the input video source video field signal, the pixel clock is slowly turned high, the field signal is shortened due to the improvement of the pixel clock, the output field signal is shortened, the output field signal is aligned with the input field signal slowly, and conversely when the output video source video field signal is behind the input video source video field signal, the output clock frequency is reduced, the field signals of the output video source video field signal and the input video source video field signal are aligned, and the output field signal and the input field signal can be kept consistent all the time through repeated adjustment in the mode.
However, this implementation is simple for a single board system, and for a matrix switcher, on a device with multiple input cards and multiple output cards cascaded, the system routing would be very complex if all the field signals of the output video source were delivered to each output card.
Disclosure of Invention
The embodiment of the invention provides a source synchronous phase locking method, a device, a system and plug-in card type video processing equipment, which are used for solving the problem that a matrix type video switcher cannot realize a genlock function when the cascade scale is large.
In one aspect, an embodiment of the present invention provides a source synchronous phase locking method, including:
receiving a source synchronous phase-locked mapping relation table;
Selecting a target synchronizing signal from a plurality of synchronizing signals according to the source synchronizing phase-locking mapping relation table and outputting the target synchronizing signal to a target synchronizing signal input interface of a target output device, so that the target synchronizing signal is used as a reference synchronizing signal of an output video source corresponding to the target synchronizing signal input interface;
wherein the plurality of synchronization signals includes a synchronization signal of an input video source of at least one input device and a synchronization signal of an output video source of at least one output device, and the target output device belongs to the at least one output device.
The invention takes a plurality of synchronous signals as the signals which can be optionally synchronized, so after the corresponding relation of the video sources which need to be synchronized is directly determined according to the source synchronous phase-locking mapping relation table, the signals which need to be synchronized can be directly selected from the plurality of synchronous signals as the target synchronous signals according to the corresponding relation, and the target synchronous signals can be directly output to the target synchronous signal input interface of the target output device after the target synchronous signals are determined, thereby realizing synchronous phase locking of the signals and avoiding the problem that the system wiring is very complex because the input device corresponding to each input video source needs to be connected with the output device corresponding to each output video source.
In one embodiment of the present invention, the selecting, according to the source synchronization phase lock mapping table, a target synchronization signal from a plurality of synchronization signals to be output to a target synchronization signal input interface of a target output device includes:
Controlling a target input device in the at least one input device to output a specified target synchronous signal as one of the plurality of synchronous signals according to the source synchronous phase-locked mapping relation table;
selecting the specified synchronization signal from the plurality of synchronization signals as the target synchronization signal to be output to the target synchronization signal input interface of the target output device;
wherein the plurality of synchronization signals includes a synchronization signal of one of a plurality of input video sources of each of the at least one input device and a synchronization signal of each of a plurality of output video sources of each of the at least one input device.
In one embodiment of the present invention, the plurality of synchronization signals includes a synchronization signal of each of a plurality of input video sources of each of the input devices and a synchronization signal of each of a plurality of output video sources of each of the output devices.
On the other hand, the embodiment of the invention also provides a source synchronous phase locking device, which comprises:
The receiving module is used for receiving the source synchronous phase-locked mapping relation table;
The synchronous phase locking module is used for selecting a target synchronous signal from a plurality of synchronous signals according to the source synchronous phase locking mapping relation table and outputting the target synchronous signal to a target synchronous signal input interface of a target output device so as to take the target synchronous signal as a reference synchronous signal of an output video source corresponding to the target synchronous signal input interface;
wherein the plurality of synchronization signals includes a synchronization signal of an input video source of at least one input device and a synchronization signal of an output video source of at least one output device, and the target output device belongs to the at least one output device.
In one embodiment of the present invention, the genlock module includes:
an input control unit, configured to control a target input device of the at least one input device to output a specified synchronization signal as one of the plurality of synchronization signals according to the source synchronization phase lock mapping relationship table;
A multiplexing unit configured to select the specified synchronization signal from the plurality of synchronization signals as the target synchronization signal input interface from which the specified synchronization signal is output to the target output device;
wherein the plurality of synchronization signals includes a synchronization signal of one of a plurality of input video sources of each of the at least one input device and a synchronization signal of each of a plurality of output video sources of each of the at least one input device.
In one embodiment of the present invention, the plurality of synchronization signals includes a synchronization signal of each of a plurality of input video sources of each of the input devices and a synchronization signal of each of a plurality of output video sources of each of the output devices.
In one embodiment of the present invention, the plurality of synchronization signals further includes a synchronization signal of an external synchronization phase lock source.
In yet another aspect, an embodiment of the present invention further provides a source synchronous phase-locked system, including:
The microcontroller is used for receiving a source synchronous phase-locking instruction and responding to the source synchronous phase-locking instruction to output a video source synchronous phase-locking mapping relation table;
the programmable logic device is configured to perform the source synchronous phase locking method according to any one of the foregoing embodiments.
In yet another aspect, an embodiment of the present invention further provides a card-inserting type video processing apparatus, including a switch back board, and at least one input device and at least one output device electrically connected to the switch back board; the exchange backboard is provided with:
The microcontroller is used for receiving a source synchronous phase-locking instruction and responding to the source synchronous phase-locking instruction to output a video source synchronous phase-locking mapping relation table;
a programmable logic device electrically connected to the microcontroller and configured to:
receiving a source synchronous phase-locked mapping relation table;
Selecting a target synchronizing signal from a plurality of synchronizing signals according to the source synchronizing phase-locking mapping relation table and outputting the target synchronizing signal to a target synchronizing signal input interface of a target output device, so that the target synchronizing signal is used as a reference synchronizing signal of an output video source corresponding to the target synchronizing signal input interface;
Wherein the plurality of synchronization signals includes a synchronization signal of an input video source of the at least one input device and a synchronization signal of an output video source of the at least one output device, and the target output device belongs to the at least one output device.
In one embodiment of the present invention, each of the input devices is provided with a synchronization signal output interface, and the synchronization signal output interface of the input device is electrically connected to a GPIO port of the programmable logic device; each output device is provided with a plurality of synchronous signal output interfaces and a plurality of synchronous signal input interfaces, the synchronous signal output interfaces are respectively and electrically connected with the GPIO ports of the programmable logic device, and the synchronous signal input interfaces are respectively and electrically connected with the GPIO ports of the programmable logic device.
In one embodiment of the present invention, each of the input devices is provided with a plurality of synchronization signal output interfaces, and the plurality of synchronization signal output interfaces of the input device are respectively and electrically connected with a plurality of GPIO ports of the programmable logic device; each output device is provided with a plurality of synchronous signal output interfaces and a plurality of synchronous signal input interfaces, the synchronous signal output interfaces of the output device are respectively and electrically connected with the GPIO ports of the programmable logic device, and the synchronous signal input interfaces of the output device are respectively and electrically connected with the GPIO ports of the programmable logic device.
In one embodiment of the present invention, the card-inserted video processing apparatus further includes:
And the external synchronous phase-locked source is electrically connected with the GPIO port of the programmable logic device and used for providing a synchronous signal to the programmable logic device as one of the synchronous signals.
The invention has the beneficial effects that:
The invention takes a plurality of synchronous signals as the signals which can be optionally synchronized, so after the corresponding relation of the video sources which need to be synchronized is directly determined according to the source synchronous phase-locking mapping relation table, the signals which need to be synchronized can be directly selected from the plurality of synchronous signals as the target synchronous signals according to the corresponding relation, and the target synchronous signals can be directly output to the target synchronous signal input interface of the target output device after the target synchronous signals are determined, thereby realizing synchronous phase locking of the signals and avoiding the problem that the system wiring is very complex because the input device corresponding to each input video source needs to be connected with the output device corresponding to each output video source.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a genlock implementation as provided in the prior art;
Fig. 2 is a schematic flow chart of a source synchronous phase locking method according to an embodiment of the present invention;
Fig. 3 is a schematic diagram of an apparatus capable of implementing signal synchronization according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another apparatus capable of implementing signal synchronization according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a source synchronous phase locking device according to an embodiment of the present invention;
Fig. 6 is a schematic structural diagram of a genlock module according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of a source synchronous phase-locked system according to an embodiment of the present invention;
Fig. 8 is a schematic structural diagram of a card-inserting type video processing device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
[ First embodiment ]
For the above reasons, please refer to fig. 2, an embodiment of the present invention provides a source synchronization phase locking method, which includes:
step1, receiving a source synchronous phase-locked mapping relation table;
Step 2, selecting a target synchronizing signal from a plurality of synchronizing signals according to a source synchronizing phase-locking mapping relation table and outputting the target synchronizing signal to a target synchronizing signal input interface of a target output device, so that the target synchronizing signal is used as a reference synchronizing signal of an output video source corresponding to the target synchronizing signal input interface;
the plurality of synchronous signals comprise synchronous signals of an input video source of at least one input device and synchronous signals of an output video source of at least one output device, and the target output device belongs to the at least one output device.
As an alternative example, the source synchronization phase-locked mapping table is used for representing a corresponding relationship between a video source output by a synchronizing signal output interface of an input device and a video source input by a synchronizing signal input interface of an output device, and may also represent a corresponding relationship between a video source output by a synchronizing signal output interface of an output device and a video source input by a synchronizing signal input interface of an output device, for example, the source synchronization phase-locked mapping table represents that a y 1 video source output by a synchronizing signal output interface of an x 1 input device and a video source input by a y 4 synchronizing signal input interface of an x 4 output device realize signal synchronization, and for example, the source synchronization phase-locked mapping table represents that a video source output by a y 2 synchronizing signal output interface of an x 2 output device and a video source interface input by a y 3 synchronizing signal input interface of an x 3 output device realize signal synchronization.
Alternatively, the source lock phase mapping table may be specified by a user, by which a signal synchronization relationship between a video source output by a synchronization signal output interface of the input device and a video source input by a synchronization signal input interface of the output device is determined, or a signal synchronization relationship between a video source output by a synchronization signal output interface of the output device and a video source input by a synchronization signal input interface of the output device is determined. For example, the user designates that the video source inputted by the y 1 th input of the x 1 th input device and the video source inputted by the y 41、y42、y43 th synchronization signal input interface of the x 3 th output device achieve signal synchronization.
Therefore, the source synchronization phase-locked mapping relation table of the present embodiment can reflect the device that needs to perform signal synchronization, that is, according to the mapping relation table, the target synchronization signal that needs to perform signal synchronization in the multiple synchronization signals can be obtained, and meanwhile, the target synchronization signal that needs to achieve signal synchronization with the target synchronization signal input interface of the target output device can also be obtained, that is, signal synchronization with the target synchronization signal input interface of the target output device is achieved, so after the source synchronization phase-locked mapping relation table is received, the required target synchronization signal can be selected from the multiple synchronization signals according to the source synchronization phase-locked mapping relation table, and the target synchronization signal is output to the target synchronization signal input interface of the target output device, and finally, the target synchronization signal is used as the reference synchronization signal of the output video source corresponding to the target synchronization signal input interface, thereby achieving the genlock function.
The input device of this embodiment may be one or more, and each input device may be provided with one or more synchronization signal output interfaces, and each input device may simultaneously provide synchronization signals of multiple input video sources, where when the number of synchronization signal output interfaces of each input device is one, it may be connected to an interface of a device capable of implementing synchronization signals through the synchronization signal output interfaces, where the device may be, for example, an FPGA (Field Programmable GATE ARRAY ), and the interface may be, for example, a GPIO (General-purpose input/output), and optionally, the device and the interface may be other devices and interfaces capable of implementing signal synchronization. The selector in the input device can select the synchronous signal of an input video source needing to realize signal synchronization to output the synchronous signal through the synchronous signal output interface of the input device, and take the synchronous signal as a target synchronous signal to be output to the FPGA, so that when the synchronous signal of a certain input video source of the input device is required to be taken as the target synchronous signal, the synchronous signal of the input video source of the input device can be selected to be output to the FPGA through the synchronous signal output interface as the target synchronous signal; in addition, when the number of the synchronous signal output interfaces of the input device is multiple and each synchronous signal output interface can be respectively connected to a GPIO interface of an FPGA, each synchronous signal of each input device is correspondingly transmitted to the FPGA, and when the synchronous signal output by a certain synchronous signal output interface of the input device is required to be used as a target synchronous signal, the synchronous signal output by the synchronous signal output interface of the input device can be directly selected as the target synchronous signal; in addition, the synchronization signal in this embodiment may be a synchronization signal output by the output device, for example, a plurality of synchronization signal input interfaces and a plurality of synchronization signal output interfaces may be provided on each output device, and each synchronization signal input interface and each synchronization signal output interface of the output device are connected to the FPGA through one GPIO interface, so that the synchronization signal output by the synchronization signal output interface of the output device may be used as a target synchronization signal, and when the output device and the output device are required to implement synchronization phase locking according to the source synchronization phase locking mapping table, the synchronization signal output by the synchronization signal output interface of the output device may be correspondingly selected as the target synchronization signal. When the synchronous signal output interface of a certain output device needs to realize signal synchronization, the synchronous signal output interface can be used as a target synchronous signal output interface.
Referring to fig. 3, in order to better understand the technical solution of the embodiment of the present invention, the following several specific implementations of the embodiment will be described, where the input device of the embodiment may be, for example, an input card, the output device of the embodiment may be, for example, an output card, and fig. 3 includes n+1 input cards, m+1 output cards, and an FPGA, and a selector is installed on the FPGA, each input card is correspondingly provided with a synchronization signal output interface, where the synchronization signal output interface is connected with a GPIO interface of the FPGA, each input card may simultaneously provide synchronization signals of multiple input video sources and output to the FPGA through the synchronization signal output interfaces of the input card, and each output card is correspondingly provided with a plurality of synchronization signal input interfaces and synchronization signal output interfaces, where the number of the synchronization signal input interfaces of each output card is equal to the number of the synchronization signal output interfaces.
(1) According to the source synchronous phase-locked mapping relation table, the y 1 th input video source of the x 1 th input card and the y 4 th synchronous signal input interface of the x 4 Zhang Shuchu th card are needed to realize genlock: the y 1 input video source of the x 1 th input card can be selected through a selector of the FPGA, and then the y 1 input video source of the x 1 th input card is output to the y 4 synchronous signal input interface of the x 4 Zhang Shuchu th input card through a synchronous signal output interface of the x 1 th input card through the FPGA.
(2) According to the source synchronous phase-locked mapping relation table, the y 1 th input video source of the x 1 th input card and the y 41、y42、y43 th synchronous signal input interface of the x 3 Zhang Shuchu th card are required to realize genlock: the y 1 input video source of the x 1 th input card can be selected through a selector of the FPGA, and then the y 1 input video source of the x 1 th input card is output to the y 41、y42、y43 synchronous signal input interface of the x 4 Zhang Shuchu th input card through a synchronous signal output interface of the x 1 th input card through the FPGA.
(3) According to the source synchronous phase-locked mapping relation table, the y 1 input video source of the x 1 th input card, the y 41、y42、y43、y44 synchronous signal input interface of the x 4 Zhang Shuchu th card and the y 51、y52、y53 synchronous signal input interface of the x 5 Zhang Shuchu th card are required to realize genlock: the y 1 input video source of the x 1 th input card can be selected through a selector of the FPGA, and then the y 1 input video source of the x 1 th input card is output to the y 41、y42、y43、y44 synchronous signal input interface of the x 4 Zhang Shuchu th card and the y 51、y52、y53 synchronous signal input interface of the x 5 Zhang Shuchu th card through the synchronous signal output interface of the x 1 th input card through the FPGA.
(4) According to the source synchronous phase-locked mapping relation table, the y 2 output video source of the x 2 Zhang Shuchu th card and the y 3 synchronous signal input interface of the x 3 Zhang Shuchu th card are needed to realize genlock: then the y 2 input video source of the x 2 Zhang Shuchu th card can be selected through a selector of the FPGA, and then the synchronous signal output by the y 2 synchronous signal output interface of the x 2 Zhang Shuchu th card is output to the y 3 synchronous signal input interface of the x 3 Zhang Shuchu th card through the FPGA.
(5) According to the source synchronous phase-locked mapping relation table, the y 2 output video source of the x 2 Zhang Shuchu th card and the y 31、y32、y33 synchronous signal input interface of the x 3 Zhang Shuchu th card are needed to realize genlock: then the y 2 input video source of the x 2 Zhang Shuchu th card can be selected through a selector of the FPGA, and then the synchronous signal output by the y 2 output interface of the x 2 Zhang Shuchu th card is output to the y 31、y32、y33 target synchronous signal input interface of the x 3 Zhang Shuchu th card through the FPGA.
It should be noted that, in this embodiment, the number of output interfaces of each output card is not specifically limited, and those skilled in the art may define the number according to specific requirements.
Similarly, the plurality of input video sources of the input card may be output through one synchronization signal output interface, and each synchronization signal output interface is connected to the FPGA through one GPIO interface, so as to implement the above-mentioned various embodiments, which are not described herein again.
In matrix video switchers, the number of input video sources is generally very large, and the input video sources are on different single boards and are not connected with each other, and there are a plurality of same output video streams, and the output video streams are also on different single boards; on the system, if the genlock function of any input video source is to be realized, all field signals of the input video source need to be transmitted to each FPGA, so that a large amount of GPIOs are wasted, and as the cascade scale is increased, the number of GPIOs is required to be increased more and more, and finally the bearing capacity of the FPGA is exceeded, so that the genlock function cannot be realized.
Based on the above-mentioned problems, therefore, step 1 of the present embodiment may specifically include steps 1.1-1.2, wherein,
Step 1.1, controlling a target input device in at least one input device to output a designated synchronous signal as one of a plurality of synchronous signals according to a source synchronous phase-locked mapping relation table;
step 1.2, selecting a designated synchronous signal from a plurality of synchronous signals as a target synchronous signal to be output to a target synchronous signal input interface of a target output device; wherein the plurality of synchronization signals includes a synchronization signal of one of a plurality of input video sources of each of the at least one input device and a synchronization signal of each of a plurality of output video sources of each of the at least one output device.
Specifically, in order to reduce the number of interfaces between the input devices and the FPGA, only one synchronization signal output interface may be provided on each input device, and the synchronization signal output interface is connected to one GPIO interface of the FPGA, where a selector on each input device may select one of the synchronization signals to be output to the FPGA through the synchronization signal output interface, and the input devices connected to the FPGA may provide a default signal as a synchronization signal to be input to the FPGA during normal operation, for example, a signal corresponding to a first input video source of each default input device is input to the FPGA as a synchronization signal, so after a source synchronization phase-locked mapping table is determined, a signal to be synchronized may be determined, and when it is determined that a synchronization signal corresponding to a certain input video source of a certain input device needs to be output as a target synchronization signal according to the source synchronization phase-locked mapping table, the FPGA needs to control the input device corresponding to be used as a target input device, and the designated synchronization signal is a signal that the FPGA controls the target input device, so that the target input device outputs the designated synchronization signal to one of the synchronization signal on the FPGA, and then all the signals may be directly selected from the designated synchronization signals as the target signals (i.e. the target signals need to be output to the target synchronization signals) to be directly output to the FPGA.
Therefore, the synchronous signal which can be selected can be a synchronous signal selected from the synchronous signals of the corresponding input video sources on each input device and transmitted to the FPGA through a GPIO interface, so that the selector can select from the synchronous signals output to the FPGA; and all the synchronous signals output from all the synchronous signal output interfaces on each output device can be correspondingly transmitted to the FPGA through one GPIO, so that the selector can select from the synchronous signals output to the FPGA.
According to the embodiment, each input device can correspond to a plurality of input video sources, the input device can be connected with the FPGA through one synchronous signal output interface, the situation that field signals of each input video source are required to be transmitted to the FPGA through one GPIO to cause GPIO waste is avoided, the input video sources corresponding to each input device can be adjusted according to the cascade scale and the bearing capacity of the FPGA, and therefore the number of GPIOs for inputting synchronous signals can be greatly reduced.
Referring to fig. 4, for example, the number of input cards is 8, that is, input cards 0-7, each input card provides synchronization signals of 4 input video sources, each input card is provided with 1 synchronization signal output interface, and each synchronization signal output interface is connected with the FPGA through one GPIO interface, so that a selector on the input card can select a synchronization signal of one input video source to transmit to the FPGA as a target synchronization signal, that is, 8 input cards can simultaneously provide 8 synchronization signals for the FPGA, and the number of output cards is 8, that is, output cards 0-7, each output card provides synchronization signals of 4 output video sources, each output card is provided with 4 synchronization signal output interfaces, each synchronization signal output interface is connected with the FPGA through 1 GPIO interface, each synchronization signal of each output video source can simultaneously provide 4 synchronization signals for the FPGA through 1 synchronization signal output interface, 8 output cards can simultaneously provide 32 synchronization signals for the FPGA, and finally 8 input cards and8 output cards can simultaneously provide a total of 40 synchronization signals for the FPGA.
In a specific embodiment, the plurality of synchronization signals includes a synchronization signal of each of a plurality of input video sources of each input device and a synchronization signal of each of a plurality of output video sources of each output device.
That is, the synchronization signals that can be selected may also be all the synchronization signals output from all the synchronization signal output interfaces on each input device, which are correspondingly transmitted to the FPGA through one GPIO, so that the selector selects from the synchronization signals output to the FPGA; or all the synchronous signals output from all the synchronous signal output interfaces of each output device are correspondingly transmitted to the FPGA through one GPIO, so that the selector can select from the synchronous signals output to the FPGA.
Referring to fig. 4 again, for example, the number of input cards is 8, that is, input cards 0-7, each input card is provided with synchronizing signals of 4 input video sources, each input card is provided with 4 synchronizing signal output interfaces, each output card can simultaneously provide 4 synchronizing signals for the FPGA through 1 GPIO interface, then 8 input cards can simultaneously provide 32 synchronizing signals for the FPGA, the number of output cards is also 8, that is, output cards 0-7, each output card provides synchronizing signals of 4 output video sources, each output card is provided with 4 synchronizing signal output interfaces, each output card is connected with the FPGA through 1 GPIO interface, each output card can simultaneously provide 4 synchronizing signals for the FPGA, then 8 output cards can simultaneously provide 32 synchronizing signals for the FPGA, finally 8 input cards and 8 output cards can provide 64 synchronizing signals for the FPGA, and the total available synchronizing signals are 64.
In addition, the plurality of synchronization signals in this embodiment further include synchronization signals of an external synchronization phase-locked source, that is, an externally accessed video source (i.e., an external synchronization phase-locked source) can also keep signal synchronization, and the externally accessed video source provides synchronization signals needed to realize signal synchronization for the FPGA, so that the synchronization signals of the external synchronization phase-locked source and at least one synchronization signal input interface of at least one output device can be selected according to the source synchronization phase-locked mapping relationship table to realize signal synchronization.
The source synchronous phase locking method provided by the embodiment can select one synchronous signal needing to realize signal synchronization from a plurality of synchronous signals as a target synchronous signal according to the source synchronous phase locking mapping relation table, and transmit the target synchronous signal to an output device needing to perform signal synchronization.
[ Second embodiment ]
Referring to fig. 5, the present embodiment further provides a source synchronous phase locking device based on the above embodiment, where the source synchronous phase locking device may include a receiving module and a synchronous phase locking module, where,
The receiving module is used for receiving the source synchronous phase-locked mapping relation table;
the synchronous phase locking module is used for selecting a target synchronous signal from a plurality of synchronous signals according to the source synchronous phase locking mapping relation table and outputting the target synchronous signal to a target synchronous signal input interface of the target output device so as to take the target synchronous signal as a reference synchronous signal of an output video source corresponding to the target synchronous signal input interface;
Wherein the plurality of synchronization signals include a synchronization signal of an input video source of at least one input device and a synchronization signal of an output video source of at least one output device, and the target output device belongs to the at least one output device.
Referring to fig. 6, in one embodiment, the genlock module includes:
An input control unit for controlling a target input device of the at least one input device to output a specified synchronization signal as one of a plurality of synchronization signals according to the source synchronization phase lock mapping relation table;
a multiplexing unit for selecting a specified synchronization signal from the plurality of synchronization signals as a target synchronization signal to be output to a target synchronization signal input interface of a target output device;
Wherein the plurality of synchronization signals includes a synchronization signal of one of the plurality of input video sources of each input device and a synchronization signal of each of the plurality of output video sources of each output device.
In a particular embodiment, the plurality of synchronization signals includes a synchronization signal for each of a plurality of input video sources for each input device and a synchronization signal for each of a plurality of output video sources for each output device.
In a specific embodiment, the plurality of synchronization signals further includes a synchronization signal of an external synchronization phase lock source.
The source synchronous phase locking device provided by the embodiment can select one synchronous signal needing to realize signal synchronization from a plurality of synchronous signals as a target synchronous signal according to the source synchronous phase locking mapping relation table, and transmit the target synchronous signal to an output device needing to perform signal synchronization.
The source synchronous phase locking device provided by the embodiment of the invention has similar implementation principle and technical effect to the source synchronous phase locking method of the above embodiment, and is not repeated here.
[ Third embodiment ]
Referring to fig. 7, the present embodiment further provides a source synchronous phase-locked system based on the above embodiment, where the source synchronous phase-locked system may include a microcontroller and a programmable logic device, where,
The microcontroller is used for receiving the source synchronous phase-locking instruction and responding to the source synchronous phase-locking instruction to output a video source synchronous phase-locking mapping relation table;
The programmable logic device is used for receiving the source synchronous phase-locked mapping relation table; selecting a target synchronous signal from a plurality of synchronous signals according to a source synchronous phase-locked mapping relation table and outputting the target synchronous signal to a target synchronous signal input interface of a target output device, so that the target synchronous signal is used as a reference synchronous signal of an output video source corresponding to the target synchronous signal input interface; wherein the plurality of synchronization signals includes a synchronization signal of an input video source of the at least one input device and a synchronization signal of an output video source of the at least one output device, and the target output device belongs to the at least one output device.
That is, the microcontroller of the present embodiment receives a source lock phase command sent by an upper stage (e.g., an upper computer), and then the microcontroller can send a relationship to be lock phase to a programmable logic device in a source lock phase mapping relationship table manner according to the obtained source lock phase command, and the programmable logic device can implement signal synchronization according to the received source lock phase mapping relationship table.
In a specific embodiment, the programmable logic device is specifically configured to control a target input device in the at least one input device to output a specified synchronization signal as one of a plurality of synchronization signals according to the source synchronization phase lock mapping relationship table; a target synchronization signal input interface for selecting a specified synchronization signal from the plurality of synchronization signals as a target synchronization signal to be output to the target output device; wherein the plurality of synchronization signals includes a synchronization signal of one of the plurality of input video sources of each input device and a synchronization signal of each of the plurality of output video sources of each output device.
In a particular embodiment, the plurality of synchronization signals includes a synchronization signal for each of a plurality of input video sources for each input device and a synchronization signal for each of a plurality of output video sources for each output device.
In a specific embodiment, the plurality of synchronization signals further includes a synchronization signal of an external synchronization phase lock source.
The source synchronous phase locking device provided by the embodiment can select one synchronous signal needing to realize signal synchronization from a plurality of synchronous signals as a target synchronous signal according to the source synchronous phase locking mapping relation table, and transmit the target synchronous signal to an output device needing to perform signal synchronization.
Preferably, the microcontroller may be, for example, an FPGA and the programmable logic device may be, for example, an MCU.
The source synchronous phase locking system provided by the embodiment of the invention has similar implementation principle and technical effect to the source synchronous phase locking method of the above embodiment, and is not repeated here.
[ Fourth embodiment ]
Referring to fig. 8, the present embodiment further provides a card-inserting type video processing apparatus on the basis of the above embodiment, where the card-inserting type video processing apparatus may include a switch back board and at least one input device and at least one output device electrically connected to the switch back board; the switch back board is provided with a microcontroller and a programmable logic device, wherein,
The microcontroller is used for receiving the source synchronous phase-locking instruction and responding to the source synchronous phase-locking instruction to output a video source synchronous phase-locking mapping relation table;
The programmable logic device is electrically connected with the microcontroller and is used for receiving the source synchronous phase-locked mapping relation table; selecting a target synchronous signal from a plurality of synchronous signals according to a source synchronous phase-locked mapping relation table and outputting the target synchronous signal to a target synchronous signal input interface of a target output device, so that the target synchronous signal is used as a reference synchronous signal of an output video source corresponding to the target synchronous signal input interface; wherein the plurality of synchronization signals includes a synchronization signal of an input video source of the at least one input device and a synchronization signal of an output video source of the at least one output device, and the target output device belongs to the at least one output device.
That is, the microcontroller of this embodiment receives a source lock command sent by an upper stage (e.g., an upper computer), and then the microcontroller can send a relation to be lock-locked to a programmable logic device in a source lock mapping relation table according to the obtained source lock command, and then the programmable logic device can select a desired target lock signal from a plurality of lock signal types according to the received source lock mapping relation table, and output the target lock signal to a target lock signal input interface of a target output device, and finally use the target lock signal as a reference lock signal of an output video source corresponding to the target lock signal input interface, thereby implementing a normal function.
Preferably, the microcontroller may be, for example, an FPGA and the programmable logic device may be, for example, an MCU.
In a specific embodiment, the programmable logic device is specifically configured to control the target input device of the at least one input device to output a target synchronization signal as one of a plurality of synchronization signals according to the source synchronization phase lock mapping relationship table; a target synchronizing signal input interface for selecting a target synchronizing signal from the plurality of synchronizing signals and outputting the selected target synchronizing signal to the target output device; wherein the plurality of synchronization signals includes a synchronization signal of one of the plurality of input video sources of each input device and a synchronization signal of each of the plurality of output video sources of each output device.
Further, each input device is provided with a synchronous signal output interface, and the synchronous signal output interfaces of the input devices are electrically connected with one GPIO port of the programmable logic device; each output device is provided with a plurality of synchronous signal output interfaces and a plurality of synchronous signal input interfaces, the plurality of synchronous signal output interfaces are respectively and electrically connected with a plurality of GPIO ports of the programmable logic device, and the plurality of synchronous signal input interfaces are respectively and electrically connected with a plurality of GPIO ports of the programmable logic device.
Referring to fig. 3 again, for example, the input device is an input card, the microcontroller is an MCU, the programmable logic device is an FPGA, and a selector is disposed on the FPGA, the input card includes input cards 0-N, each input card can provide synchronization signals of a plurality of output video sources, each input card is provided with a synchronization signal output interface, and the synchronization signal output interface is electrically connected to a GPIO interface of the FPGA, so that the selector in the input card can select a video signal of an input video source to transmit to the FPGA through the synchronization signal output interface; each output card can be provided with a plurality of synchronous signal output interfaces and a plurality of synchronous signal input interfaces, each synchronous signal output interface is electrically connected with the FPGA through a GPIO interface, and each synchronous signal input interface is electrically connected with the FPGA through a GPIO interface.
The plug-in card type video processing device of the embodiment is provided with a plurality of input devices and a plurality of output devices, each input device can be provided with only one synchronous signal output interface, and can also be provided with a plurality of synchronous signal output interfaces, the programmable logic device can transmit the source synchronous phase-locked mapping relation table to the programmable logic device according to a preset source synchronous phase-locked mapping relation table, the selector can select synchronous signals which need to be subjected to signal synchronization according to an instruction of a superior level (such as an upper computer), the synchronous signals can be synchronous signals of an input video source on the input device, can also be synchronous signals of an external video source, can also be synchronous signals of an output video source on the output device, and can also be synchronous signals of the output video source on the output device, and then the programmable logic device transmits the selected synchronous signals to the target synchronous signal input interface of the target output device, so that a genlock function is realized, and the number of interfaces of the programmable logic device only needs to be equal to the sum of the number of the synchronous signal output interfaces of the input cards and the number of the synchronous signal input interfaces of the output cards, so that the whole programmable logic device can be realized, and the whole system can be realized by the method of increasing the number of the synchronous signal output interfaces of the input cards and the output interfaces of the programmable logic device is also can be greatly reduced.
The implementation principle and technical effects of the plug-in card type video processing device provided by the embodiment of the present invention are similar to those of the source synchronous phase locking method in the above embodiment, and are not repeated here.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and matched without conflict in technical features, contradiction in structure, and departure from the purpose of the present invention.
In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and/or methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and the division of the units/modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units/modules described as separate units may or may not be physically separate, and units/modules may or may not be physically units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the embodiment.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. A method of source synchronous phase locking comprising:
Receiving a source synchronous phase-locked mapping relation table; the source synchronous phase-locked mapping relation table is used for representing the corresponding relation of synchronization between a video source output by a synchronous signal output interface of an input device and a video source input by a synchronous signal input interface of the output device, or representing the corresponding relation of synchronization between the video source output by the synchronous signal output interface of the output device and the video source input by the synchronous signal input interface of the output device;
Selecting a target synchronizing signal from a plurality of synchronizing signals according to the source synchronizing phase-locking mapping relation table and outputting the target synchronizing signal to a target synchronizing signal input interface of a target output device, so that the target synchronizing signal is used as a reference synchronizing signal of an output video source corresponding to the target synchronizing signal input interface;
wherein the plurality of synchronization signals includes a synchronization signal of an input video source of at least one input device and a synchronization signal of an output video source of at least one output device, and the target output device belongs to the at least one output device.
2. The source lock phase method as claimed in claim 1, wherein the selecting the target synchronization signal from the plurality of synchronization signals according to the source lock phase mapping table to output to the target synchronization signal input interface of the target output device comprises:
controlling a target input device in the at least one input device to output a designated synchronous signal as one of the synchronous signals according to the source synchronous phase-locked mapping relation table;
selecting the specified synchronization signal from the plurality of synchronization signals as the target synchronization signal to be output to the target synchronization signal input interface of the target output device;
wherein the plurality of synchronization signals includes a synchronization signal of one of a plurality of input video sources of each of the at least one input device and a synchronization signal of each of a plurality of output video sources of each of the at least one input device.
3. The source lock method of claim 1, wherein the plurality of synchronization signals includes a synchronization signal of each of a plurality of input video sources of each of the input devices and a synchronization signal of each of a plurality of output video sources of each of the output devices.
4. A source lock phase method as claimed in any one of claims 1 to 3, wherein the plurality of synchronization signals further comprises a synchronization signal of an external lock phase source.
5. A source synchronous phase lock device, comprising:
The receiving module is used for receiving the source synchronous phase-locked mapping relation table; the source synchronous phase-locked mapping relation table is used for representing the corresponding relation of synchronization between a video source output by a synchronous signal output interface of an input device and a video source input by a synchronous signal input interface of the output device, or representing the corresponding relation of synchronization between the video source output by the synchronous signal output interface of the output device and the video source input by the synchronous signal input interface of the output device;
The synchronous phase locking module is used for selecting a target synchronous signal from a plurality of synchronous signals according to the source synchronous phase locking mapping relation table and outputting the target synchronous signal to a target synchronous signal input interface of a target output device so as to take the target synchronous signal as a reference synchronous signal of an output video source corresponding to the target synchronous signal input interface;
wherein the plurality of synchronization signals includes a synchronization signal of an input video source of at least one input device and a synchronization signal of an output video source of at least one output device, and the target output device belongs to the at least one output device.
6. The source lock phase apparatus of claim 5, wherein the lock phase module comprises:
an input control unit, configured to control a target input device of the at least one input device to output a specified synchronization signal as one of the plurality of synchronization signals according to the source synchronization phase lock mapping relationship table;
A multiplexing unit configured to select the specified synchronization signal from the plurality of synchronization signals as the target synchronization signal input interface from which the specified synchronization signal is output to the target output device;
wherein the plurality of synchronization signals includes a synchronization signal of one of a plurality of input video sources of each of the at least one input device and a synchronization signal of each of a plurality of output video sources of each of the at least one input device.
7. The source lock device of claim 5, wherein the plurality of synchronization signals includes a synchronization signal for each of a plurality of input video sources for each of the input devices and a synchronization signal for each of a plurality of output video sources for each of the output devices.
8. A source lock phase apparatus as claimed in any one of claims 5 to 7, wherein the plurality of synchronization signals further comprises a synchronization signal of an external lock phase source.
9. A source synchronous phase lock system, comprising:
The microcontroller is used for receiving a source synchronous phase-locking instruction and responding to the source synchronous phase-locking instruction to output a video source synchronous phase-locking mapping relation table;
a programmable logic device for performing the source synchronous phase locking method as claimed in any one of claims 1 to 4.
10. A plug-in card type video processing equipment comprises a switching backboard, at least one input device and at least one output device, wherein the at least one input device and the at least one output device are electrically connected with the switching backboard; the method is characterized in that the exchange backboard is provided with:
The microcontroller is used for receiving a source synchronous phase-locking instruction and responding to the source synchronous phase-locking instruction to output a video source synchronous phase-locking mapping relation table;
a programmable logic device electrically connected to the microcontroller and configured to:
Receiving a source synchronous phase-locked mapping relation table; the source synchronous phase-locked mapping relation table is used for representing the corresponding relation of synchronization between a video source output by a synchronous signal output interface of an input device and a video source input by a synchronous signal input interface of the output device, or representing the corresponding relation of synchronization between the video source output by the synchronous signal output interface of the output device and the video source input by the synchronous signal input interface of the output device;
Selecting a target synchronizing signal from a plurality of synchronizing signals according to the source synchronizing phase-locking mapping relation table and outputting the target synchronizing signal to a target synchronizing signal input interface of a target output device, so that the target synchronizing signal is used as a reference synchronizing signal of an output video source corresponding to the target synchronizing signal input interface;
Wherein the plurality of synchronization signals includes a synchronization signal of an input video source of the at least one input device and a synchronization signal of an output video source of the at least one output device, and the target output device belongs to the at least one output device.
11. The card-inserted video processing apparatus of claim 10 wherein each of the input devices is provided with a synchronization signal output interface and the synchronization signal output interface of the input device is electrically connected to a GPIO port of the programmable logic device; each output device is provided with a plurality of synchronous signal output interfaces and a plurality of synchronous signal input interfaces, the synchronous signal output interfaces are respectively and electrically connected with the GPIO ports of the programmable logic device, and the synchronous signal input interfaces are respectively and electrically connected with the GPIO ports of the programmable logic device.
12. The card-inserted video processing apparatus of claim 10 wherein each of the input devices is provided with a plurality of synchronization signal output interfaces, and the plurality of synchronization signal output interfaces of the input device are respectively electrically connected to a plurality of GPIO ports of the programmable logic device; each output device is provided with a plurality of synchronous signal output interfaces and a plurality of synchronous signal input interfaces, the synchronous signal output interfaces of the output device are respectively and electrically connected with the GPIO ports of the programmable logic device, and the synchronous signal input interfaces of the output device are respectively and electrically connected with the GPIO ports of the programmable logic device.
13. The plug-in video processing apparatus according to any one of claims 10 to 12, wherein the plug-in video processing apparatus further comprises:
And the external synchronous phase-locked source is electrically connected with the GPIO port of the programmable logic device and used for providing a synchronous signal to the programmable logic device as one of the synchronous signals.
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