CN103986462B - Possesses the Fast Frequency Estimation circuit of high-speed interface - Google Patents

Abstract

The invention provides a kind of Fast Frequency Estimation circuit possessing high-speed interface, this frequency measurement circuit includes high-speed interface input block, clock adjustment unit, frequency measurement arithmetic element, high-speed interface output unit and control unit.Described Fast Frequency Estimation circuit possesses high-speed-differential LVDS input/output interface, can arrange according to outside and adjust the time delay of clock on high-speed interface bus, frequency measurement arithmetic element provides eight kinds of Frequency Measurement Algorithms to arrange optional, uses SPI interface/I2C interface to realize the relevant configuration to circuit.The present invention can adapt to the ultrahigh speed frequency measurement requirement under high throughput rate, has configuration mode flexibly, can take into account analysis quick for note number and the quick high accuracy analysis to continuous long signal；The high-speed interface that this circuit possesses, can directly be connected with prime high-speed ADC circuit；The clock adjustment unit that this circuit possesses, reduces the high-speed interface bit error rate；The data of high-speed interface captured in real time can be read by external equipment, and then judge that high-speed interface work is the most normal.

Description

Possesses the Fast Frequency Estimation circuit of high-speed interface

Technical field

The present invention relates to a kind of communication and signal processing integrated circuit, a kind of Fast Frequency Estimation circuit possessing high-speed interface.

Background technology

Utilize wireless signal to communicate and detection field various, generally require to obtain and receive signal spectrum signal characteristic. Analyzing and receive the method for signal spectrum feature a lot, along with digital technology and the development of software engineering, all-digital receiver device exists Association area application gradually increases.Basic digital receiver is to be stored by the digital signal received, and it is soft to pass budgets Part analyzes signal characteristic.But, along with the electromagnetic environment gone from bad to worse and increasing the demand of signal processing real-time capacity, Information processing rate is brought into schedule faster.The software execution that the contrast of hardware computation conversion speed is traditional, saves fortune 3-5 order of magnitude of evaluation time；But special hardware computation mode is poor due to motility, computing cost is high.

Therefore design one possesses high-speed interface and software configurable Fast Frequency Estimation circuit can solve the problem that motility and computing are ageing Between contradiction.

Summary of the invention

It is an object of the invention to overcome the deficiencies in the prior art, it is proposed that a kind of Fast Frequency Estimation circuit possessing high-speed interface, in fact Shi Xinggao, it is possible to adapt to the ultrahigh speed frequency measurement requirement under high throughput rate.

The technical scheme provided according to the present invention, described in possess the Fast Frequency Estimation circuit of high-speed interface and include: high-speed interface input is single Unit, clock adjustment unit, frequency measurement arithmetic element, high-speed interface output unit, control unit；Described high-speed interface input block Connecting control unit, clock adjustment unit and frequency measurement arithmetic element respectively, it is single that described high-speed interface output unit connects control respectively Unit, clock adjustment unit and frequency measurement arithmetic element；Described control unit arranges high-speed interface input block, clock adjustment unit, Frequency measurement arithmetic element, the duty of high-speed interface output unit；

Described high-speed interface input block, by control unit control, receives data and bit synchronization clock simultaneously, and the data received are entered Entering frequency measurement arithmetic element, the bit synchronization clock received enters clock adjustment unit；Described high-speed interface input block includes: LVDS Receptor, positive edge trigger trapping module, negative edging trigger trapping module, high-speed interface control module, first in first out buffering mould Block；The output of described LVDS receiver is simultaneously connected with positive edge and triggers trapping module, negative edging trigger trapping module, and positive edge is touched Send out trapping module, the output of negative edging trigger trapping module is simultaneously connected with high-speed interface control module, high-speed interface control module Data output connects first in first out buffer module；The enable of LVDS receiver is controlled by high-speed interface control module, the LVDS of startup The Low Voltage Differential Signal LVDS received is converted to single ended digital system level by receptor；Positive edge triggers trapping module and uses warp Oversampling clock adjustment unit processes the positive edge of clock signal and captures transferring single-ended input data to；Negative edging trigger capture mould Block uses and processes the negative side of clock signal along capturing transferring single-ended input data to through oversampling clock adjustment unit；High-speed interface Control module is according to the data effective form arranged and effectively captures edge, by assembled for input data, and is sequentially written in first in first out Buffer module；

Described clock adjustment unit input clock is provided by high-speed interface input block, and the clock after clock adjustment unit adjusts carries Supply high-speed interface input block, the clock after clock adjustment unit divides is supplied to control unit, frequency measurement arithmetic element and height Speed interface output cell；

Described frequency measurement arithmetic element processes the output data of the first in first out buffer module being derived from high-speed interface input block, and frequency measurement is transported The operation result calculating unit exports to high speed interface output cell；Frequency measurement arithmetic element includes: by window function wave filter, window function Road device, frequency measurement arithmetical unit, arithmetic and control unit, ROM, outlet selector；Window function bypass apparatus is simultaneously connected with frequency measurement arithmetic element Input, window function wave filter, arithmetic and control unit, frequency measurement arithmetical unit, frequency measurement connects outlet selector, frequency measurement computing arithmetical unit Device, outlet selector and ROM are all by arithmetic and control unit control；Whether window function bypass apparatus selects to enter the data of frequency measurement arithmetical unit Needing the process through window function wave filter, frequency measurement arithmetical unit is by fast fourier transform FFT module and discrete Fourier transform DFT Module composition；The input data of frequency measurement arithmetical unit are derived from window function bypass apparatus, calculate the factor by arithmetic and control unit after ROM reads, Write frequency measurement arithmetical unit；Outlet selector is operated by arithmetic and control unit, according to the setting of control unit, selects satisfactory survey Frequently result arithmetical unit output.

Further, described control unit arranges the clock effective means of high-speed interface input block, effective including positive edge, negative Edge is effective；Control unit arranges the data effective form of high-speed interface input block；It is single that control unit arranges high-speed interface input Unit's capture data are by the export ratio in first in first out buffer module；Control unit arranges the significance bit of high-speed interface input block Number；Control unit controls frequency measurement arithmetic element and loads the number of significant digit of frequency measurement operational factor from self ROM；Control unit is arranged The delayed control mode of clock adjustment unit, control mode be divided into arranged by pin and depositor arrange；When control unit is arranged The quantity to clock delay of clock adjustment unit；Control unit arranges the divider ratios of clock adjustment unit output clock；Window function Bypass apparatus MUX3 is under the control of arithmetic and control unit (Control3), it is possible to input signal is filtered by selectivity by window function Device or be directly output in frequency measurement arithmetical unit without window function wave filter, external equipment is realized window function by control unit The coefficient configuration of depositor；Control unit arranges the working method of arithmetic and control unit in frequency measurement arithmetic element, passes through arithmetic and control unit Data through window function bypass apparatus being read out mode select, reading manner divides reading continuously and frame data to read；Control single Unit arranges the working method of outlet selector in frequency measurement arithmetic element；Control unit arranges the number of significant digit of high-speed interface output unit.

Further, in described high-speed interface input block, method assembled for input data is by high-speed interface control module: when It is effective that monolateral edge is set, further according to the effective edge edge arranged, selects the trapping module data on corresponding sides edge；It is effective that bilateral edge is set Time, overlapping selection positive and negative edge trapping module data.

Further, described clock adjustment unit includes: two delay phase-locked loops worked alone, locking decision module, two-stages Clock multichannel module, frequency dividing control device, programmable integer modulus frequency divider；The clock source of the delay phase-locked loop input that two work alone The single-ended clock signal of LVDS receiver conversion in high-speed interface input block, the locking signal of two delay phase-locked loops simultaneously with Locking decision module connects, and the output of phaselocked loop is connected with two-stage clock multichannel module successively, and second level clock multichannel module exports One be connected with programmable integer modulus frequency divider, another is directly entered high-speed interface input block, and frequency dividing control device controls to compile The output of journey integer frequency divider；Each delay phase-locked loop adapts to different working bands respectively；Described locking decision module is mainly sentenced The precedence of disconnected two delay phase-locked loops locking, controls the first order output of two-stage clock multichannel module simultaneously, and output first locks Delay phase-locked loop clock；The second level of two-stage clock multichannel module is controlled output by control unit；Chosen locks through delay The clock that phase ring postpones enters fractional number frequency frequency divider after crossing two-stage clock multichannel module, by programmable integer modulus frequency divider by controlling The frequency dividing ratio output that unit is arranged, the clock of output enters frequency measurement arithmetic element, high-speed interface output unit, control unit.

Further, the operation result of described frequency measurement arithmetic element has four kinds of way of outputs, is that directly output, maximum are defeated respectively Go out, minima exports, beyond threshold value output.

Further, the computing mode of described frequency measurement arithmetic element frequency measurement provides and includes using 16 fixed-point number FFT, FFT 1024 points of counting, 512 points, 256 points, 128 points, 64 are selective；And use 16 fixed-point number DFT transform, DFT Counting 8 points, 16 points, 32 selective.

Further, described window function wave filter provide two kinds of typical window function wave filter selective, be respectively cosine window function, Window index function, window function filter order N is fixed as 16 rank, and window function coefficient is configured by control unit.

Further, described high-speed interface output unit includes being sequentially connected with: output register, output buffer, LVDS send out Send device；The data of the output of frequency measurement arithmetic element are after control unit selects, and the output being stored in high-speed interface output unit is deposited Device, unification exports LVDS emitter by output buffer, it is achieved the conversion between single-ended signal to LVDS signal；Output Reference clock made by output clock after depositor uses clock adjustment unit frequency dividing；Clock adjustment unit is divided by output buffer Output clock after Pin and output register, through postponing control, adjust output data and clock phase relation, and parallel cache exports.

Further, described control unit includes: three line SPI interface, two line I2C interfaces, interface control module and deposit Device heap, three line SPI interface and two line I2C interfaces connect interface control module, then are connected with register file；Register file is by circuit Unit control register array composition, be divided into according to said units: interface configuration register heap, clock configuration register Heap, computing arranges register file, Interface status register file；High-speed interface can be latched by Interface status register file to input The value of first in first out buffer module in unit.

The invention have the advantage that there is configuration mode flexibly, analysis quick for note number can be taken into account and to continuous long signal Quick high accuracy is analyzed；The high-speed interface that this circuit possesses, can directly be connected with prime high-speed ADC (analog-digital converter) circuit, Without other change-over circuits；The clock adjustment unit that this circuit possesses, reduces the high-speed interface bit error rate；External equipment can be passed through Read the data of high-speed interface captured in real time, and then judge that high-speed interface work is the most normal.

Accompanying drawing explanation

Fig. 1 whole circuit Organization Chart.

Fig. 2 high-speed interface input block structural representation.

Fig. 3 high-speed interface output unit structural representation.

Fig. 4 clock adjustment unit circuit structure diagram.

Fig. 5 frequency measurement arithmetic element circuit structure chart.

Fig. 6 control unit structural representation.

Fig. 7 controls interface data/command frame structural representation.

Detailed description of the invention

Circuit framework figure such as Fig. 1 of the present invention, including high-speed interface input block, clock adjustment unit, frequency measurement arithmetic element, High-speed interface output unit, control unit.Described high-speed interface input block connect respectively control unit, clock adjustment unit and Frequency measurement arithmetic element；Described high-speed interface output unit connects control unit, clock adjustment unit and frequency measurement arithmetic element respectively； Described control unit scheduling controlling high-speed interface input block, clock adjustment unit simultaneously, frequency measurement arithmetic element, high-speed interface are defeated Go out the respective work of unit.

(default mode is sampling to the DDR/SDR data of the high-speed interface input block capture high speed LVDS interface of this circuit DDR data)；Clock adjustment unit can support that hardware/software mode realizes the adjustment to input clock Phase delay；Frequency measurement computing The data of cell processing high-speed interface elements capture, support that 5 class FFT modes are arranged, and 3 classes DFT are arranged；Control unit provides External device access interface, command/data resolves, and external equipment arranges present invention work by controlling scheduling unit, reads this The duty of bright circuit.By reading Interface status register file, it is judged that whether the clock delay of setting meets necessary sampling Requirement.

As in figure 2 it is shown, described high-speed interface input block specifically includes that LVDS receiver (LVDS_RX), positive edge Trigger trapping module (Capture_P), negative edging trigger trapping module (Capture_N), high-speed interface control module (Control1), First in first out buffer module (FIFO)；The output of described LVDS receiver is simultaneously connected with positive edge and triggers trapping module, negative side edge Triggering trapping module, positive edge triggers trapping module, the output of negative edging trigger trapping module is simultaneously connected with high-speed interface and controls mould Block, the data output of high-speed interface control module connects first in first out buffer module.The difference that LVDS receiver will receive LVDS signal is converted to single ended digital system level；The data form that high-speed interface control module is arranged according to control unit DDR/SDR, effective edge edge, the data of selection trapping module, the follow-up FIFO of assembled write (illustrate, when being set to SDR, Negative side, along effectively, selects Capture_N assembly write FIFO；It is set to DDR, owing to DDR is that bilateral edge is effective, therefore Overlapping Capture_P and Capture_N of selection write assembly writes FIFO)；The principal character of this unit includes:

(1) signal of telecommunication received is LVDS (Low Voltage Differential Signal), it is possible to the LVDS of difference is changed into single-ended signal；

(2) in high-speed interface data/address bus quantity be 8,10,12,14,16 optional (i.e. effectively word length 8,10,12, 14,16 are optional, arrange input data when being 8 word lengths, from a high position to low level, and the only LVDS input difference of most-significant byte To effectively)；

(3) high speed input interface receives differential bit synchronised clock；

(4) mode of the data captured is DDR (Double Data Rate, in the clock cycle, only two data are effective) form, SDR (single data speed, clock cycle only one of which data are effective) form is optional；

(5) data received carry out buffering that (buffering ratio is relevant to the frequency dividing ratio of clock adjustment unit, works as clock by FIFO When the frequency dividing ratio of adjustment unit is 1:2, needing with 1:2 ratio buffered data, the most each internal clock cycle, by control module control System reads the data of 2 word lengths), it is achieved the transmission of frequency senser different clock frequencies outer with high-speed interface input block, reduces and surveys Frequently the power consumption of unit.

As it is shown on figure 3, high-speed interface output unit specifically includes that LVDS transmitter (LVDS_TX), output register, defeated Go out buffer.The data of frequency senser output are deposited through one-level, the time sequence difference between equilibrium criterion, unified slow by output Rush device and export LVDS sender interface, it is achieved the conversion between single-ended signal to LVDS signal.This unit principal character bag Include:

(1) signal of telecommunication exported is difference LVDS, and the LVDS output interface quantity opened is by control unit control, the highest by 16 To LVDS difference output interface；

(2) output data export to output buffer after depositor is deposited again；

(3) source synchronous clock of LVDS_TX simultaneously output register and register data.

As shown in Figure 4, described clock adjustment unit includes: two DLL worked alone (delay phase-locked loop), lockings are sentenced Certainly (Lock dect), two-stage clock MUX (MUX1 and MUX2), programmable integer modulus frequency divider (Divide), point Frequently controller (Control2).Two DLL worked alone (DLL1 and DLL2), it is defeated that the clock of input is derived from high-speed interface Entering the input clock of the LVDS that unit receives, each DLL adapts to different working bands respectively, and each DLL is simultaneously Export 8 equal decile input phases and postpone signal.Locking decision mainly judges the order of two DLL lockings, high from working band , to the movement that working band is low, this locking decision controls clock MUX (MUX1) output of the first order simultaneously, 8 clocks of the DLL that output first locks；Second clock Port Multiplier selects according to the delay quantity arranged to meet the clock letter required Number output；Frequency dividing control device realizes the operation to integral frequency divisioil number device, and what main judgement frequency divider needs were carried out is frequency division by odd integers, Even frequency division, does not divides, and adjusts the output of frequency divider simultaneously.The principal character of this unit includes:

(1) possesses regulation output clock phase ability, it is possible to according to setting, one cycle of clock of input is divided into 8 phase places Or 4 phase places, output clock can be controlled (defeated for postponing unit with 1/8 input clock cycle or 1/4 input clock cycle Entering the clock cycle is T, and output delay resolution is the T/8 clock cycle, i.e. output delay time T/8, T/4,3T/8, T/2, 5T/8,3T/4,7T/8 are optional；When 4 grades divide the cycle, the T/4 integral multiple output of second level multichannel controls effectively, other Multi-channel control is invalid；When 8 grades divide the cycle, whole controls of second level multichannel are arranged effectively)；

(2) this clock adjustment unit can bypass, and i.e. input clock is without any DLL, is directly inputted into clock Port Multiplier；

(3) through delay control clock enter integer frequency divider, frequency dividing control device according in control unit arrange frequency dividing ratio, (frequency dividing ratio is 1 to 32 integers, and if frequency dividing ratio is that 1 selection does not divide output, frequency dividing ratio is 2 in the output of control integer frequency divider Select 2 frequency dividing outputs).

As it is shown in figure 5, described frequency measurement arithmetic element includes: window function wave filter, window function bypass apparatus (MUX3), frequency measurement Arithmetical unit, outlet selector (MUX4), ROM, arithmetic and control unit (Control3).

Window function wave filter provides two kinds of typical window function wave filter selective: cosine window function, window index function；Filter order Number N is fixed as 16 rank, and its coefficient is configured according to the setting in control unit by arithmetic and control unit.

Window function bypass apparatus is simultaneously connected with input and the output of window function wave filter, can be straight by the data filtered without window function Connect and pass to frequency measurement arithmetical unit.

Frequency measurement arithmetical unit is by FFT, 512 FFT, 256 FFT, 128 FFT, 64 FFT of 1024, above-mentioned Structure be made up of its subset (FFT of i.e. 1024 is made up of 512 FFT, and 512 FFT are made up of 256 FFT, And so on)；32 DFT, 16 DFT, 8 DFT are independent DFT operating structure.Its basic workflow Being that first arithmetic and control unit effectively inputs figure place according to arrange, the operating structure of selection reads the calculating of storage in ROM The factor, and the factor is write the correspondence position in frequency measurement arithmetical unit；Then arithmetic and control unit is according to the data reading mode arranged, The data being derived from window function bypass apparatus are loaded into frequency measurement arithmetical unit；Loading starts computing after completing；Computing terminate after according to setting Output requirement, start outlet selector, select satisfactory data to export.The principal character of this unit includes:

(1) the computing mode of its frequency measurement includes using fixed-point number FFT, 1024 points, 512 points, 256 points, 128 points, 64 points Optional；

(2) the computing mode of its frequency measurement includes using fixed-point number DFT, and 8 points, 16 points, 32 optional；

(3) the twiddle factor coefficient of computing is solidificated in ROM, and according to the frequency measurement mode selected, corresponding depositor can obtain Control unit is by the normalization coefficient obtained in the ROM in sheet, beyond the computing of arrange value in a control unit more than 1 The factor will be truncated (when input is 8, it is 8 that the operational factor of reading is truncated)；

(4) operational precision of frequency measurement, 8,10,12,14,16 can be arranged；

(5) window function wave filter provides two kinds of typical window function wave filter selective, is cosine window function respectively, window index function, Filter order N is fixed as 16 rank, and its coefficient is configured by control unit；

(6) the maximum output that the operation result of frequency measurement arithmetical unit is arranged by outlet selector according to control unit, minima exports, The mode of super thresholding output, selects the most satisfactory output.

As shown in Figure 6, described control unit includes: three line SPI interface (SPI), two lines I2C interface (I2C), interface Control module, register file.

Three line SPI interface include that three line SPI input (SPI_I) and three line SPI export (SPI_O), it is achieved the input of SPI mouth Output access, the signal of three line SPI includes that input chip selects signal (ISEN), input clock signal (ISCK), input data/ Command signal (ISD), output chip selection signal (OSEN), export clock signal, export data/commands signal (OSD), its Being mainly characterized by the case of clock is effective, when input chip selection signal is effective, input data/commands interface external equipment is defeated The instruction/data entered；When needs output information, exporting interface clock signal carry-out bit synchronised clock, output chip selection signal maintains Effective status, output data/commands signal with output clock for bit synchronization reference clock, synchronism output data/commands.

Three line I2C realize I2C interface I/O reference, and this interfaces is in I2C from equipment state, and its principal character includes Chip selection signal (CS), input/output signal (I/O).When chip selection signal is effective, first input/output interface works in reception shape State, receives the instruction/data instruction of transmission, decides whether to enter output state according to the control of rear class interface control module.

The Frame that three line SPI interface/two line I2C interface are arrived by interface control module, its frame format is: frame head, instruction, Address, data, effect position (CRC16 uses 16 cyclic redundancy effects), as shown in Figure 7；When receiving complete frame After information, first check that the effect information of last transmission is the most correct according to frame format, fed back by corresponding transmission interface as made mistakes Error message；As correct, frame information is decomposed into address, data, instruction, according to the result decomposed, appropriate address is deposited Device carries out read/write operation, and by corresponding interface, implementation status is fed back to external equipment.

Register file includes that interface configuration register heap, clock configuration register heap, computing arrange register file.Interface configuration is posted Storage heap provides the setting (8/10/12/14/16 BITBUS network selects) of the quantity of docking port bus, DDR/SDR (double data number Rate/haploidy number selects according to digit rate), sampling window (positive edge/negative side edge).Interface status register file, according to the instruction received, Latch FIFO in High-speed Interface Card, be may determine that by the data of this part whether the clock delay of setting possesses correct sampling Window.Clock configuration register heap provides the control to cycle isodisperse, postpones to control depositor, and pin controls Phase delay to be made Can, internal integers crossover frequency is arranged.Computing configuration register heap provides and selects operating structure, and window function is arranged, defeated Go out result judgement.

The principal character of described control unit includes:

(1) possess three line SPI interface, two line I2C interfaces；

(2) by above two interface, in accessing sheet, control depositor, carry out relevant setting；

(3) possess high-speed interface status register heap, latch the internal number of high speed input interface FIFO according to the order controlling interface According to.

The principle of the present invention:

Time-base signal is endless, and the feature of frequency in the time window t mouth that to be one of them limited of the position focused particularly on, Time-base signal for an endless is first divided into many little time intervals, in order to determines and exists in corresponding time interval Frequency.In order to study the signal local characteristics at time Γ, need to strengthen the signal at time Γ, and be compressed in other times Signal, this i.e. can be taken out, by windowing, the signal being concerned about by realizing with signal multiplication at the window function h (Γ) of Γ with center Coming, now signal becomes:

s_t(_Γ)=s (_Γ)h(_Γ-t), note: when Γ=t, s_t(_Γ)=s (_Γ)；Other time, s_t(_Γ)=0

The signal of sampling is the function of two times, set time section reference point t the most of interest and execution time Γ.Window function is certainly The signal having determined to take out is substantially unchanged around time t, and the signal leaving interested time t is greatly reduced.

Discrete Fourier transform (DFT) (DFT), by signal is mapped to orthogonal complex exponential space, obtains the frequency spectrum of signal, if signal is X (n), its calculating formula is as follows:

$X\left(k\right)=\underset{n=0}{\overset{N-1}{\Σ}}x\left(n\right)\exp (-j2\mathrm{\π}kn/N),0\≤k\≤N-1$

Its spectrum is

$P\left(k\right)=\sqrt{{X_r}^2\left(k\right)+{X_i}^2\left(k\right)},k=0,1,2,......N$

The center frequency points i.e. measured is positioned at above-mentioned spectrum maximum point；

Fast fourier transform (FFT) is a kind of algorithm of discrete Fourier transform (DFT) (FFT), can reduce discrete Fourier and become The arithmetic element usage quantity changed, the DFT operand of a N point is N², the FFT operand of a N point is Nlog₂N, When calculating 32 and above DFT, FFT can significantly reduce the hardware spending of computing；But need first during FFT computing Complete the extraction (the most first completing all operational datas to prepare) that computing is counted, can be with computing and data acquisition streamline during DFT computing Arranging (i.e. while gathering data, computing), therefore the frequency in low resolution calculates (bigness scale) employing DFT technology On advantage.

Claims (9)

1. possess the Fast Frequency Estimation circuit of high-speed interface, its feature, including: high-speed interface input block, clock adjustment unit, frequency measurement arithmetic element, high-speed interface output unit, control unit；Described high-speed interface input block connects control unit, clock adjustment unit and frequency measurement arithmetic element respectively, and described high-speed interface output unit connects control unit, clock adjustment unit and frequency measurement arithmetic element respectively；Described control unit arranges high-speed interface input block, clock adjustment unit, frequency measurement arithmetic element, the duty of high-speed interface output unit；

Described high-speed interface input block, by control unit control, receives data and bit synchronization clock simultaneously, and the data received enter frequency measurement arithmetic element, and the bit synchronization clock received enters clock adjustment unit；Described high-speed interface input block includes: LVDS receiver, positive edge trigger trapping module, negative edging trigger trapping module, high-speed interface control module, first in first out buffer module；The output of described LVDS receiver is simultaneously connected with positive edge and triggers trapping module, negative edging trigger trapping module, positive edge triggers trapping module, the output of negative edging trigger trapping module is simultaneously connected with high-speed interface control module, and the data output of high-speed interface control module connects first in first out buffer module；The enable of LVDS receiver is controlled by high-speed interface control module, and the Low Voltage Differential Signal LVDS received is converted to single ended digital system level by the LVDS receiver of startup；Positive edge triggers trapping module and uses the positive edge through oversampling clock adjustment unit process clock signal to capture transferring single-ended input data to；Negative edging trigger trapping module uses and processes the negative side of clock signal along capturing transferring single-ended input data to through oversampling clock adjustment unit；High-speed interface control module is according to the data effective form arranged and effectively captures edge, by assembled for input data, and is sequentially written in first in first out buffer module；

Described clock adjustment unit input clock is provided by high-speed interface input block, clock after clock adjustment unit adjusts is supplied to high-speed interface input block, and the clock after clock adjustment unit divides is supplied to control unit, frequency measurement arithmetic element and high-speed interface output unit；

Described frequency measurement arithmetic element processes the output data of the first in first out buffer module being derived from high-speed interface input block, and the operation result of frequency measurement arithmetic element exports to high speed interface output cell；Frequency measurement arithmetic element includes: window function wave filter, window function bypass apparatus, frequency measurement arithmetical unit, arithmetic and control unit, ROM, outlet selector；Window function bypass apparatus is simultaneously connected with the input of frequency measurement arithmetic element, window function wave filter, arithmetic and control unit, frequency measurement arithmetical unit, and frequency measurement connects outlet selector arithmetical unit, and frequency measurement arithmetical unit, outlet selector and ROM are all by arithmetic and control unit control；Window function bypass apparatus selects the data entering frequency measurement arithmetical unit to be made up of fast fourier transform FFT module and discrete Fourier transform DFT block arithmetical unit the need of the process through window function wave filter, frequency measurement；The input data of frequency measurement arithmetical unit are derived from window function bypass apparatus, calculate the factor by arithmetic and control unit after ROM reads, write frequency measurement arithmetical unit；Outlet selector is operated by arithmetic and control unit, according to the setting of control unit, selects satisfactory frequency measurement result arithmetical unit to export.

Possessing the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, described control unit arranges the clock effective means of high-speed interface input block, effective including positive edge, and negative side is along effectively；Control unit arranges the data effective form of high-speed interface input block；Control unit arranges high-speed interface input block capture data by the export ratio in first in first out buffer module；Control unit arranges the number of significant digit of high-speed interface input block；Control unit controls frequency measurement arithmetic element and loads the number of significant digit of frequency measurement operational factor from self ROM；Control unit arranges the delayed control mode of clock adjustment unit, control mode be divided into arranged by pin and depositor arrange；Control unit arranges the quantity to clock delay of clock adjustment unit；Control unit arranges the divider ratios of clock adjustment unit output clock；Window function bypass apparatus (MUX3) is under the control of arithmetic and control unit (Control3), can input signal be directly output in frequency measurement arithmetical unit by window function wave filter or without window function wave filter by selectivity, external equipment realizes the coefficient to window function depositor by control unit and configures；Control unit arranges the working method of arithmetic and control unit in frequency measurement arithmetic element, by arithmetic and control unit, the data through window function bypass apparatus is read out mode and selects, and reading manner divides reading continuously and frame data to read；Control unit arranges the working method of outlet selector in frequency measurement arithmetic element；Control unit arranges the number of significant digit of high-speed interface output unit.

Possesses the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, in described high-speed interface input block, method assembled for input data is by high-speed interface control module: when arranging, monolateral edge is effective, further according to the effective edge edge arranged, select the trapping module data on corresponding sides edge；Arrange bilateral edge effective time, overlapping select positive and negative edge trapping module data.

Possesses the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, described clock adjustment unit includes: two delay phase-locked loops worked alone, locking decision module, two-stage clock multichannel module, frequency dividing control devices, programmable integer modulus frequency divider；The clock of the delay phase-locked loop input that two work alone is derived from the single-ended clock signal of LVDS receiver conversion in high-speed interface input block, the locking signal of two delay phase-locked loops is connected with locking decision module simultaneously, the output of phaselocked loop is connected with two-stage clock multichannel module successively, one of second level clock multichannel module output is connected with programmable integer modulus frequency divider, another is directly entered high-speed interface input block, and frequency dividing control device controls the output of programmable integer modulus frequency divider；Each delay phase-locked loop adapts to different working bands respectively；Described locking decision module mainly judges the precedence of two delay phase-locked loop lockings, controls the first order output of two-stage clock multichannel module, the delay phase-locked loop clock that output first locks simultaneously；The second level of two-stage clock multichannel module is controlled output by control unit；The chosen clock through delay phase-locked loop delay enters fractional number frequency frequency divider after crossing two-stage clock multichannel module, the frequency dividing ratio output arranged by control unit by programmable integer modulus frequency divider, the clock of output enters frequency measurement arithmetic element, high-speed interface output unit, control unit.

Possessing the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, the operation result of described frequency measurement arithmetic element has four kinds of way of outputs, is directly output, maximum output, minima output respectively, exports beyond threshold value.

Possessing the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, the computing mode of described frequency measurement arithmetic element frequency measurement provides and includes using 16 fixed-point number FFT, 1024 points of counting of FFT, 512 points, and 256 points, 128 points, 64 selective；And using 16 fixed-point number DFT transform, DFT counts 8 points, and 16 points, 32 are selective.

Possesses the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, described window function wave filter provides two kinds of typical window function wave filter selective, it is cosine window function, window index function respectively, window function filter order N is fixed as 16 rank, and window function coefficient is configured by control unit.

Possessing the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, described high-speed interface output unit includes being sequentially connected with: output register, output buffer, LVDS transmitter；The data of the output of frequency measurement arithmetic element, after control unit selects, are stored in the output register of high-speed interface output unit, and unification exports LVDS emitter by output buffer, it is achieved the conversion between single-ended signal to LVDS signal；Reference clock made by output clock after output register uses clock adjustment unit frequency dividing；Output clock after clock adjustment unit is divided by output buffer controls through delay with output register, adjusts output data and clock phase relation, parallel cache output.

Possesses the Fast Frequency Estimation circuit of high-speed interface the most as claimed in claim 1, it is characterized in that, described control unit includes: three line SPI interface, two line I2C interfaces, interface control module and register file, and three line SPI interface and two line I2C interfaces connect interface control module, then are connected with register file；Register file is made up of the control register array of the unit of circuit, is divided into according to said units: interface configuration register heap, clock configuration register heap, and computing arranges register file, Interface status register file；The value of first in first out buffer module in high-speed interface input block can be latched by Interface status register file.