CN103986462A - Fast frequency measuring circuit with high-speed interface - Google Patents
Fast frequency measuring circuit with high-speed interface Download PDFInfo
- Publication number
- CN103986462A CN103986462A CN201410239560.2A CN201410239560A CN103986462A CN 103986462 A CN103986462 A CN 103986462A CN 201410239560 A CN201410239560 A CN 201410239560A CN 103986462 A CN103986462 A CN 103986462A
- Authority
- CN
- China
- Prior art keywords
- speed interface
- unit
- output
- clock
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a fast frequency measuring circuit with a high-speed interface. The frequency measuring circuit comprises a high-speed interface input unit, a clock adjusting unit, a frequency measuring operation unit, a high-speed interface output unit and a control unit. The fast frequency measuring circuit is provided with a high-speed difference LVDS input and output interface which can adjust the delay time of a clock on a high-speed interface bus according to external settings. The frequency measuring operation unit provides eight frequency measuring algorithm settings which can be selected, an SPI interface/I2C interface is used for achieving relevant configuration of the circuit. The fast frequency measuring circuit can meet the requirement for ultrahigh-speed frequency measuring with the high throughput rate, a flexible configuration manner is achieved, and fast analysis of short signals and fast and high-precision analysis of long consecutive signals can be compatible; the circuit is provided with the high-speed interface which can be directly connected with a preceding state high-speed ADC circuit; the circuit is provided with the clock adjusting unit, and therefore the error rate of the high-speed interface is reduced; data which are captured in real time by the high-speed interface can be read through a peripheral device, and therefore whether the high-speed interface works normally or not can be judged.
Description
Technical field
The present invention relates to a kind of communication and signal processing integrated circuit, specifically a kind of Fast Frequency Estimation circuit that possesses high-speed interface.
Background technology
Various, utilize wireless signal to communicate and detection field, often need to obtain and receive signal spectrum signal characteristic.The method that analysis receives signal spectrum feature is a lot, and along with the development of digital technology and software engineering, all-digital receiver device increases gradually in association area application.Basic digital receiver is that the digital signal receiving is stored, and the software analysis signal characteristic that passes budgets.Yet along with the electromagnetic environment going from bad to worse and the increasing of demand of signal being processed to real-time capacity, information processing rate is brought into schedule faster.Hardware computing conversion speed contrasts traditional software and carries out, and saves 3-5 order of magnitude operation time; But special-purpose hardware compute mode is because flexibility is poor, and computing cost is high.
Therefore design a kind of possess high-speed interface and the configurable Fast Frequency Estimation circuit of software can solve flexibility and computing ageing between contradiction.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, proposed a kind of Fast Frequency Estimation circuit that possesses high-speed interface, its real-time is high, can adapt to the ultrahigh speed frequency measurement requirement under high throughput rate.
According to technical scheme provided by the invention, described in possess high-speed interface Fast Frequency Estimation circuit comprise: high-speed interface input unit, clock adjustment unit, frequency measurement arithmetic element, high-speed interface output unit, control unit; Described high-speed interface input unit is connection control unit, clock adjustment unit and frequency measurement arithmetic element respectively, and described high-speed interface output unit is connection control unit, clock adjustment unit and frequency measurement arithmetic element respectively; Described control unit arranges high-speed interface input unit, clock adjustment unit, the operating state of frequency measurement arithmetic element, high-speed interface output unit;
Described high-speed interface input unit is controlled by control unit, receives data and bit synchronization clock simultaneously, and the data that receive enter frequency measurement arithmetic element, and the bit synchronization clock receiving enters clock adjustment unit; Described high-speed interface input unit comprises: LVDS receiver, positive edge trigger trapping module, negative edging trigger trapping module, high-speed interface control module, first in first out buffer module; The output of described LVDS receiver connects positive edge simultaneously and triggers trapping module, negative edging trigger trapping module, the output that positive edge triggers trapping module, negative edging trigger trapping module connects high-speed interface control module simultaneously, and the data output of high-speed interface control module connects first in first out buffer module; The enabling of LVDS receiver controlled by high-speed interface control module, and the LVDS receiver of startup is converted to single-ended digital system level by the Low Voltage Differential Signal LVDS receiving; Positive edge triggers trapping module employing and catches transferring single-ended input data to through the positive edge of oversampling clock adjustment unit processing clock signal; Negative edging trigger trapping module adopts catches transferring single-ended input data to through the marginal edge of oversampling clock adjustment unit processing clock signal; High-speed interface control module is according to the data effective form arranging and effectively catch edge, will input data assembled, and order writes first in first out buffer module;
Described clock adjustment unit input clock is provided by high-speed interface input unit, clock after the adjustment of clock adjustment unit offers high-speed interface input unit, and the clock after clock adjustment unit frequency division offers control unit, frequency measurement arithmetic element and high-speed interface output unit;
Described frequency measurement arithmetic element is processed the output data of the first in first out buffer module that is derived from high-speed interface input unit, and the operation result of frequency measurement arithmetic element exports high-speed interface output unit to; Frequency measurement arithmetic element comprises: window function filter, window function bypass apparatus, frequency measurement arithmetic unit, arithmetic and control unit, ROM, outlet selector; Window function bypass apparatus connects input, window function filter, arithmetic and control unit, the frequency measurement arithmetic unit of frequency measurement arithmetic element simultaneously, and frequency measurement arithmetic unit connects outlet selector, and frequency measurement arithmetic unit, outlet selector and ROM are controlled by arithmetic and control unit all; Window function bypass apparatus selects the data that enter frequency measurement arithmetic unit whether to need the processing through window function filter, and frequency measurement arithmetic unit is by fast fourier transform FFT module and discrete Fourier transform DFT module composition; The input data source of frequency measurement arithmetic unit is from window function bypass apparatus, and calculated factor from ROM reads, writes frequency measurement arithmetic unit by arithmetic and control unit; Outlet selector is operated by arithmetic and control unit, according to the setting of control unit, selects satisfactory frequency measurement arithmetic unit result output.
Further, described control unit arranges the clock effective means of high-speed interface input unit, comprises that positive edge is effective, and marginal edge is effective; Control unit arranges the data effective form of high-speed interface input unit; Control unit arranges high-speed interface input unit capture-data by the export ratio in first in first out buffer module; Control unit arranges the number of significant digit of high-speed interface input unit; Control unit is controlled frequency measurement arithmetic element and from self ROM, is loaded the number of significant digit of frequency measurement operational factor; Control unit arranges the delayed control mode of clock adjustment unit, and control mode is divided into by pin and arranges and register arranges; Control unit arranges the quantity to clock delay of clock adjustment unit; Control unit arranges the divider ratios of clock adjustment unit output clock; Control unit, according to selecting window function, is selected corresponding window function outgoing route, and external equipment is realized the coefficient of window function register is configured by control unit; Control unit arranges the working method of arithmetic and control unit in frequency measurement arithmetic element, by arithmetic and control unit, the data through window function bypass apparatus is carried out to reading manner selection, and reading manner divides and reads continuously and frame data read; Control unit arranges the working method of outlet selector in frequency measurement arithmetic element; Control unit arranges the number of significant digit of high-speed interface output unit.
Further, in described high-speed interface input unit, high-speed interface control module by the assembled method of input data is: when arranging, monolateral edge is effective, then according to the effective edge edge arranging, selects the trapping module data on corresponding sides edge; Bilateral edge is set when effective, the positive and negative edge of overlapping selection trapping module data.
Further, described clock adjustment unit comprises: two delay phase-locked loops that work alone, locking decision module, two-stage clock multichannel module, frequency dividing control device, programmable integer modulus frequency divider; The single-ended clock signal of clock source LVDS receiver conversion in high-speed interface input unit of two delay phase-locked loop inputs that work alone, the locking signal of two delay phase-locked loops is connected with locking decision module simultaneously, the output of phase-locked loop is connected with two-stage clock multichannel module successively, one of second level clock multichannel module output is connected with programmable integer modulus frequency divider, another directly enters high-speed interface input unit, and frequency dividing control device is controlled the output of programmable integer modulus frequency divider; Each delay phase-locked loop adapts to respectively different working bands; Described locking decision module mainly judges the precedence of two delay phase-locked loop lockings, controls the first order output of two-stage clock multichannel module simultaneously, and output is the delay phase-locked loop clock of locking first; Output is controlled by control unit in the second level of two-stage clock multichannel module; After crossing two-stage clock multichannel module, the chosen clock postponing through delay phase-locked loop enters fractional number frequency frequency divider, by programmable integer modulus frequency divider, by the frequency dividing ratio of control unit setting, exported, the clock of output enters frequency measurement arithmetic element, high-speed interface output unit, control unit.
Further, the operation result of described frequency measurement arithmetic element has four kinds of way of outputs, is respectively direct output, maximum output, minimum value output, exceeds threshold value output.
Further, the compute mode of described frequency measurement arithmetic element frequency measurement provides and comprises 16 fixed-point number FFT conversion of employing, 1024 points of counting of FFT, and 512 points, 256 points, 128 points, 64 are selective; And adopt 16 fixed-point number DFT conversion, DFT 8 points of counting, and 16 points, 32 are selective.
Further, described window function filter provides two kinds of typical window function filters selective, is respectively cosine window function, window index function, and window function filter order N is fixed as 16 rank, and window function coefficient is configured by control unit.
Further, described high-speed interface output unit comprises connection successively: output register, output buffer, LVDS transmitter; The data of the output of frequency measurement arithmetic element, after control unit is selected, deposit the output register of high-speed interface output unit in, and unification outputs to LVDS reflector by output buffer, realizes single-ended signal to the conversion between LVDS signal; Output register adopts is that output clock after clock adjustment unit frequency division is made reference clock; Output buffer is controlled the output clock after clock adjustment unit frequency division and output register through postponing, adjust output data and clock phase relation, parallel cache output.
Further, described control unit comprises: three line SPI interfaces, two line I2C interfaces, interface control module and register file, and three line SPI interfaces and two line I2C interface connecting interface control modules, then be connected with register file; Register file is comprised of the control register array of the unit of circuit, according to affiliated unit, is divided into: interface configuration register file, and clock configuration register heap, computing arranges register file, Interface status register file; By Interface status register file, can latch the value of first in first out buffer module in high-speed interface input unit.
Advantage of the present invention is: have configuration mode flexibly, can take into account for short signal rapid analysis and the quick high accuracy analysis to continuous long signal; The high-speed interface that this circuit possesses, can directly be connected with prime high-speed ADC (analog to digital converter) circuit, without other change-over circuits; The clock adjustment unit that this circuit possesses, reduces the high-speed interface error rate; Can read the data that high-speed interface is caught in real time by external equipment, and then judge that whether high-speed interface work is normal.
Accompanying drawing explanation:
Fig. 1 whole circuit Organization Chart.
Fig. 2 high-speed interface input unit structural representation.
Fig. 3 high-speed interface output unit structural representation.
Fig. 4 clock adjustment unit circuit structure diagram.
Fig. 5 frequency measurement arithmetic element circuit structure chart.
Fig. 6 control unit structural representation.
Fig. 7 control interface data/commands frame structure schematic diagram.
Embodiment
Circuit framework figure of the present invention, as Fig. 1, comprises high-speed interface input unit, clock adjustment unit, frequency measurement arithmetic element, high-speed interface output unit, control unit.Described high-speed interface input unit is connection control unit, clock adjustment unit and frequency measurement arithmetic element respectively; Described high-speed interface output unit is connection control unit, clock adjustment unit and frequency measurement arithmetic element respectively; Described control unit is scheduling controlling high-speed interface input unit, clock adjustment unit simultaneously, frequency measurement arithmetic element, the work separately of high-speed interface output unit.
The high-speed interface input unit of this circuit is caught the DDR/SDR data (default mode is sampling DDR data) of high speed LVDS interface; Clock adjustment unit can be realized the adjustment to input clock phase delay by support hardware/software mode; Frequency measurement arithmetic element is processed the data of high-speed interface elements capture, and the 5 class FFT modes of support arrange, and 3 class DFT arrange; Control unit provides external device access interface, and command/data is resolved, and external equipment arranges the present invention by Control and Schedule unit and works, and reads the operating state of circuit of the present invention.By fetch interface status register, pile, whether the clock delay that judgement arranges meets necessary sampling request.
As shown in Figure 2, described high-speed interface input unit mainly comprises: LVDS receiver (LVDS_RX), positive edge trigger trapping module (Capture_P), negative edging trigger trapping module (Capture_N), high-speed interface control module (Control1), first in first out buffer module (FIFO); The output of described LVDS receiver connects positive edge simultaneously and triggers trapping module, negative edging trigger trapping module, the output that positive edge triggers trapping module, negative edging trigger trapping module connects high-speed interface control module simultaneously, and the data output of high-speed interface control module connects first in first out buffer module.LVDS receiver is converted to single-ended digital system level by the difference LVDS signal receiving; The data format DDR/SDR that high-speed interface control module arranges according to control unit, effective edge edge, selects the data of trapping module, assembledly writes follow-up FIFO (for example, when being set to SDR, marginal edge is effective, selects the assembled FIFO that writes of Capture_N; Be set to DDR, because DDR is that bilateral edge is effective, therefore overlapping selection Capture_P and Capture_N write the assembled FIFO of writing); The principal character of this unit comprises:
(1) signal of telecommunication receiving is LVDS (Low Voltage Differential Signal), can change the LVDS of difference into single-ended signal;
(2) in high-speed interface, data/address bus quantity is 8,10,12,14,16 optional (be effective word length 8,10,12,14,16 optional, input data is set while being 8 word lengths, and from a high position to low level, the LVDS input difference that only has most-significant byte is to effectively);
(3) high speed input interface receives difference bit synchronization clock;
(4) mode of the data of catching is DDR (Double Data Rate, only have in the clock cycle two data effective) form, and SDR (single data speed, clock cycle only has the data effective) form is optional;
(5) data that receive cushion by FIFO that (buffering ratio is relevant to the frequency dividing ratio of clock adjustment unit, when the frequency dividing ratio of clock adjustment unit is 1: 2, need to be with 1: 2 ratio buffered data, it is each sheet internal clock cycle, by control module, controlled the data that read 2 word lengths), realize the transmission of the outer different clock frequencies of frequency senser and high-speed interface input unit, reduce the power consumption of frequency senser.
As shown in Figure 3, high-speed interface output unit mainly comprises: LVDS transmitter (LVDS_TX), output register, output state.The data of frequency senser output are deposited through one-level, the time sequence difference between equilibrium criterion, and unification outputs to LVDS sender interface by output buffer, realizes single-ended signal to the conversion between LVDS signal.This unit principal character comprises:
(1) signal of telecommunication of output is difference LVDS, and the LVDS output interface quantity of opening is controlled by control unit, the highest 16 pairs of LVDS difference output interfaces;
(2) output data export on output buffer after register is deposited again;
(3) source synchronous clock and the register data of LVDS_TX while output register.
As shown in Figure 4, described clock adjustment unit comprises: two DLL that work alone (delay phase-locked loop), locking decision (Lock dect), two-stage clock MUX (MUX1 and MUX2), programmable integer modulus frequency divider (Divide), frequency dividing control device (Control2).Two DLL that work alone (DLL1 and DLL2), the input clock of the LVDS that the clock source of input receives from high-speed interface input unit, each DLL adapts to respectively different working bands, and each DLL exports 8 equal decile input phase inhibit signals simultaneously.Locking decision mainly judges the order of two DLL lockings, high from working band, and to the low movement of working band, this locking decision is controlled clock MUX (MUX1) output of the first order simultaneously, and output is 8 clocks of the DLL of locking first; Second clock Port Multiplier is selected the clock signal output meeting the demands according to the delay quantity arranging; Frequency dividing control device is realized the operation that integral frequency divisioil is counted to device, and what mainly adjudicate that frequency divider need to carry out is frequency division by odd integers, even frequency division, and frequency division is not adjusted the output of frequency divider simultaneously.The principal character of this unit comprises:
(1) possesses regulation output clock phase ability, can be according to setting, the clock one-period of input is divided into 8 phase places or 4 phase places, to output clock, can take 1/8 input clock cycle or 1/4 input clock cycle and control as postponing unit that (input clock cycle is T, output delay resolution is the T/8 clock cycle, and output delay time T/8, T/4,3T/8, T/2,5T/8,3T/4,7T/8 are optional; When 4 grades are divided the cycle, the output of the T/4 integral multiple of second level multichannel is controlled effectively, and it is invalid that other multichannel is controlled; When 8 grades are divided the cycle, whole controls of second level multichannel arrange effectively);
(2) this clock adjustment unit can bypass, and input clock, without any DLL, is directly inputted into clock Port Multiplier;
(3) through the clock that postpones to control, enter integer frequency divider, frequency dividing control device is according to the frequency dividing ratio arranging in control unit, control the output (frequency dividing ratio is 1 to 32 integer, and if frequency dividing ratio is 1 to select not frequency division output, frequency dividing ratio is 2 selection 2 frequency divisions outputs) of integer frequency divider.
As shown in Figure 5, described frequency measurement arithmetic element comprises: window function filter, window function bypass apparatus (MUX3), frequency measurement arithmetic unit, outlet selector (MUX4), ROM, arithmetic and control unit (Control3).
Window function filter provides two kinds of typical window function filters selective: cosine window function, window index function; Filter order N is fixed as 16 rank, and its coefficient is configured according to the setting in control unit by arithmetic and control unit.
Window function bypass apparatus connects input and the output of window function filter simultaneously, the data of not process window function filtering can be directly passed to frequency measurement arithmetic unit.
Frequency measurement arithmetic unit is by the FFT of 1024,512 FFT, and 256 FFT, 128 FFT, 64 FFT, above-mentioned structure forms (the FFT of 1024 consists of 512 FFT, and 512 FFT consist of 256 FFT, so analogize) by its subset; 32 DFT, 16 DFT, 8 DFT are DFT operating structure independently.Its basic workflow is, first arithmetic and control unit is according to the effective input figure place arranging, and the operating structure of selection, reads the calculated factor of storing in ROM, and the factor is write to the correspondence position in frequency measurement arithmetic unit; Then arithmetic and control unit, according to the data reading manner arranging, is loaded into frequency measurement arithmetic unit by the data that are derived from window function bypass apparatus; Startup computing after loading completes; Computing finishes rear according to the output requirement arranging, and starts outlet selector, selects satisfactory data output.The principal character of this unit comprises:
(1) compute mode of its frequency measurement comprises employing fixed-point number FFT, 1024 points, and 512 points, 256 points, 128 points, 64 are optional;
(2) compute mode of its frequency measurement comprises employing fixed-point number DFT, 8 points, and 16 points, 32 are optional;
(3) the twiddle factor coefficient that computing is used is solidificated in ROM, according to the frequency measurement mode of selecting, the normalization coefficient that the controlled unit of corresponding register meeting obtains in the ROM in sheet, exceed more than 1 operational factor of settings in control unit and will be truncated (when being input as 8, it is 8 that the operational factor reading is truncated);
(4) operational precision of frequency measurement, 8,10,12,14,16 can arrange;
(5) it is selective that window function filter provides two kinds of typical window function filters, is respectively cosine window function, window index function, and filter order N is fixed as 16 rank, and its coefficient is configured by control unit;
(6) the maximum output that outlet selector arranges the operation result of frequency measurement arithmetic unit according to control unit, minimum value output, the mode of super thresholding output, selects wherein satisfactory output.
As shown in Figure 6, described control unit comprises: three line SPI interfaces (SPI), two line I2C interfaces (I2C), interface control module, register file.
Three line SPI interfaces comprise three line SPI inputs (SPI_I) and three line SPI outputs (SPI_O), realize the I/O reference of SPI mouth, the signal of three line SPI comprises input chip selection signal (ISEN), input clock signal (ISCK), input data/commands signal (ISD), output chip selection signal (OSEN), clock signal, output data/commands signal (OSD), its principal character is in the effective situation of clock, when input chip selection signal is effective, input data/commands interface receives the instruction/data of external equipment input; When needs output information, clock signal interface carry-out bit synchronised clock, output chip selection signal maintains effective status, and output data/commands signal be take output clock as bit synchronization reference clock, synchronously exports data/commands.
Three line I2C realize the I/O reference of I2C interface, and this interfaces is in I2C from equipment state, and its principal character comprises chip selection signal (CS), input/output signal (I/O).When chip selection signal is effective, first input/output interface works in accepting state, receives the instruction/data instruction of transmission, according to the control of rear class interface control module, determines whether to enter output state.
The Frame that interface control module receives three line SPI interface/two line I2C interfaces, its frame format is: frame head, instruction, address, data, effect position (CRC16 adopts 16 cyclic redundancy effects), as shown in Figure 7; After receiving complete frame information, first whether correct according to the effect information of the last transmission of frame format inspection, as make mistakes by corresponding transmission interface feedback error message; As correctly frame information being decomposed into address, data, instruction, according to the result of decomposing, carries out read/write operation to the register of appropriate address, and implementation status is fed back to external equipment by corresponding interface.
Register file comprises that interface configuration register file, clock configuration register heap, computing arrange register file.Interface configuration register file provides the setting (8/10/12/14/16 bus selection) of the quantity of docking port bus, DDR/SDR (double data rate/haploidy number is selected according to digit rate), sampling window (positive edge/marginal edge).Interface status register file, according to the instruction receiving, latchs FIFO in High-speed Interface Card, and the data by this part can judge whether the clock delay of setting possesses correct sampling window.Clock configuration register heap provides the control to cycle isodisperse, postpones control register, and pin control phase postpones to enable, inner integral frequency divisioil set of frequency.Computing configuration register heap provides to be selected operating structure, window function setting, Output rusults judgement.
The principal character of described control unit comprises:
(1) possess three line SPI interfaces, two line I2C interfaces;
(2) by above-mentioned two kinds of interfaces, control register in access sheet, the setting of being correlated with;
(3) possess high-speed interface status register heap, according to the order of control interface, latch high speed input interface FIFO internal data.
Principle of the present invention:
Time-base signal is endless, and the feature that the concrete position of paying close attention to is frequency in one of them limited time window t mouth, first time-base signal for an endless is divided into many little time intervals, to determine the frequency existing within the corresponding time interval.In order to study signal at the local characteristics of time Γ, need to strengthen the signal at time Γ, and be compressed in the signal of other times, this can be by realizing with signal multiplication at the window function h of Γ (Γ) with center, by windowing, the signal of being concerned about is taken out, now signal becomes:
St (Γ)=s (Γ) h (Γ-t), note: when Γ=t, st (Γ)=s (Γ); Other time, st (Γ)=0
The signal of sampling is the function of two times, the set time section reference point t and the time of implementation Γ that are concerned about.Window function has determined that the signal taking out is around time t constant substantially, and the signal that leaves be concerned about time t is greatly reduced.
Discrete Fourier transform (DFT) (DFT), by the complex exponential space to quadrature by signal map, obtains the frequency spectrum of signal, and establishing signal is x (n), and its calculating formula is as follows:
Its spectrum value is
The center frequency points of measuring is positioned at above-mentioned spectrum value maximum point;
Fast fourier transform (FFT) is a kind of algorithm of discrete Fourier transform (DFT) (FFT), can reduce the arithmetic element usage quantity of discrete Fourier transform (DFT), the DFT operand that N is ordered is N2, the FFT operand that N is ordered is Nlog2N, when 32 of calculating and above DFT, FFT can significantly reduce the hardware spending of computing; But during FFT computing, need to first complete the extraction (first completing all operational datas prepares) that computing is counted, can computing during DFT computing and data acquisition line configurations (image data on one side, computing on one side), therefore at frequency measuring and calculating (bigness scale) the employing DFT of low resolution, there is technical advantage.
Claims (9)
1. the Fast Frequency Estimation circuit that possesses high-speed interface, its feature, comprising: high-speed interface input unit, clock adjustment unit, frequency measurement arithmetic element, high-speed interface output unit, control unit; Described high-speed interface input unit is connection control unit, clock adjustment unit and frequency measurement arithmetic element respectively, and described high-speed interface output unit is connection control unit, clock adjustment unit and frequency measurement arithmetic element respectively; Described control unit arranges high-speed interface input unit, clock adjustment unit, the operating state of frequency measurement arithmetic element, high-speed interface output unit;
Described high-speed interface input unit is controlled by control unit, receives data and bit synchronization clock simultaneously, and the data that receive enter frequency measurement arithmetic element, and the bit synchronization clock receiving enters clock adjustment unit; Described high-speed interface input unit comprises: LVDS receiver, positive edge trigger trapping module, negative edging trigger trapping module, high-speed interface control module, first in first out buffer module; The output of described LVDS receiver connects positive edge simultaneously and triggers trapping module, negative edging trigger trapping module, the output that positive edge triggers trapping module, negative edging trigger trapping module connects high-speed interface control module simultaneously, and the data output of high-speed interface control module connects first in first out buffer module; The enabling of LVDS receiver controlled by high-speed interface control module, and the LVDS receiver of startup is converted to single-ended digital system level by the Low Voltage Differential Signal LVDS receiving; Positive edge triggers trapping module employing and catches transferring single-ended input data to through the positive edge of oversampling clock adjustment unit processing clock signal; Negative edging trigger trapping module adopts catches transferring single-ended input data to through the marginal edge of oversampling clock adjustment unit processing clock signal; High-speed interface control module is according to the data effective form arranging and effectively catch edge, will input data assembled, and order writes first in first out buffer module;
Described clock adjustment unit input clock is provided by high-speed interface input unit, clock after the adjustment of clock adjustment unit offers high-speed interface input unit, and the clock after clock adjustment unit frequency division offers control unit, frequency measurement arithmetic element and high-speed interface output unit;
Described frequency measurement arithmetic element is processed the output data of the first in first out buffer module that is derived from high-speed interface input unit, and the operation result of frequency measurement arithmetic element exports high-speed interface output unit to; Frequency measurement arithmetic element comprises: window function filter, window function bypass apparatus, frequency measurement arithmetic unit, arithmetic and control unit, ROM, outlet selector; Window function bypass apparatus connects input, window function filter, arithmetic and control unit, the frequency measurement arithmetic unit of frequency measurement arithmetic element simultaneously, and frequency measurement arithmetic unit connects outlet selector, and frequency measurement arithmetic unit, outlet selector and ROM are controlled by arithmetic and control unit all; Window function bypass apparatus selects the data that enter frequency measurement arithmetic unit whether to need the processing through window function filter, and frequency measurement arithmetic unit is by fast fourier transform FFT module and discrete Fourier transform DFT module composition; The input data source of frequency measurement arithmetic unit is from window function bypass apparatus, and calculated factor from ROM reads, writes frequency measurement arithmetic unit by arithmetic and control unit; Outlet selector is operated by arithmetic and control unit, according to the setting of control unit, selects satisfactory frequency measurement arithmetic unit result output.
2. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, is characterized in that, described control unit arranges the clock effective means of high-speed interface input unit, comprises that positive edge is effective, and marginal edge is effective; Control unit arranges the data effective form of high-speed interface input unit; Control unit arranges high-speed interface input unit capture-data by the export ratio in first in first out buffer module; Control unit arranges the number of significant digit of high-speed interface input unit; Control unit is controlled frequency measurement arithmetic element and from self ROM, is loaded the number of significant digit of frequency measurement operational factor; Control unit arranges the delayed control mode of clock adjustment unit, and control mode is divided into by pin and arranges and register arranges; Control unit arranges the quantity to clock delay of clock adjustment unit; Control unit arranges the divider ratios of clock adjustment unit output clock; Control unit, according to selecting window function, is selected corresponding window function outgoing route, and external equipment is realized the coefficient of window function register is configured by control unit; Control unit arranges the working method of arithmetic and control unit in frequency measurement arithmetic element, by arithmetic and control unit, the data through window function bypass apparatus is carried out to reading manner selection, and reading manner divides and reads continuously and frame data read; Control unit arranges the working method of outlet selector in frequency measurement arithmetic element; Control unit arranges the number of significant digit of high-speed interface output unit.
3. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, it is characterized in that, in described high-speed interface input unit, high-speed interface control module by the assembled method of input data is: when arranging, monolateral edge is effective, according to the effective edge edge arranging, select the trapping module data on corresponding sides edge again; Bilateral edge is set when effective, the positive and negative edge of overlapping selection trapping module data.
4. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, it is characterized in that, described clock adjustment unit comprises: two delay phase-locked loops that work alone, locking decision module, two-stage clock multichannel module, frequency dividing control device, programmable integer modulus frequency divider; The single-ended clock signal of clock source LVDS receiver conversion in high-speed interface input unit of two delay phase-locked loop inputs that work alone, the locking signal of two delay phase-locked loops is connected with locking decision module simultaneously, the output of phase-locked loop is connected with two-stage clock multichannel module successively, one of second level clock multichannel module output is connected with programmable integer modulus frequency divider, another directly enters high-speed interface input unit, and frequency dividing control device is controlled the output of programmable integer modulus frequency divider; Each delay phase-locked loop adapts to respectively different working bands; Described locking decision module mainly judges the precedence of two delay phase-locked loop lockings, controls the first order output of two-stage clock multichannel module simultaneously, and output is the delay phase-locked loop clock of locking first; Output is controlled by control unit in the second level of two-stage clock multichannel module; After crossing two-stage clock multichannel module, the chosen clock postponing through delay phase-locked loop enters fractional number frequency frequency divider, by programmable integer modulus frequency divider, by the frequency dividing ratio of control unit setting, exported, the clock of output enters frequency measurement arithmetic element, high-speed interface output unit, control unit.
5. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, is characterized in that, the operation result of described frequency measurement arithmetic element has four kinds of way of outputs, is respectively direct output, maximum output, minimum value output, exceeds threshold value output.
6. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, is characterized in that, the compute mode of described frequency measurement arithmetic element frequency measurement provides and comprises 16 fixed-point number FFT conversion of employing, 1024 points of counting of FFT, and 512 points, 256 points, 128 points, 64 are selective; And adopt 16 fixed-point number DFT conversion, DFT 8 points of counting, and 16 points, 32 are selective.
7. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, it is characterized in that, described window function filter provides two kinds of typical window function filters selective, respectively cosine window function, window index function, window function filter order N is fixed as 16 rank, and window function coefficient is configured by control unit.
8. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, is characterized in that, described high-speed interface output unit comprises successively and to connect: output register, output buffer, LVDS transmitter; The data of the output of frequency measurement arithmetic element, after control unit is selected, deposit the output register of high-speed interface output unit in, and unification outputs to LVDS reflector by output buffer, realizes single-ended signal to the conversion between LVDS signal; Output register adopts is that output clock after clock adjustment unit frequency division is made reference clock; Output buffer is controlled the output clock after clock adjustment unit frequency division and output register through postponing, adjust output data and clock phase relation, parallel cache output.
9. the Fast Frequency Estimation circuit that possesses as claimed in claim 1 high-speed interface, it is characterized in that, described control unit comprises: three line SPI interfaces, two line I2C interfaces, interface control module and register file, three line SPI interfaces and two line I2C interface connecting interface control modules, then be connected with register file; Register file is comprised of the control register array of the unit of circuit, according to affiliated unit, is divided into: interface configuration register file, and clock configuration register heap, computing arranges register file, Interface status register file; By Interface status register file, can latch the value of first in first out buffer module in high-speed interface input unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410239560.2A CN103986462B (en) | 2014-05-30 | 2014-05-30 | Possesses the Fast Frequency Estimation circuit of high-speed interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410239560.2A CN103986462B (en) | 2014-05-30 | 2014-05-30 | Possesses the Fast Frequency Estimation circuit of high-speed interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103986462A true CN103986462A (en) | 2014-08-13 |
| CN103986462B CN103986462B (en) | 2017-01-04 |
Family
ID=51278302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410239560.2A Active CN103986462B (en) | 2014-05-30 | 2014-05-30 | Possesses the Fast Frequency Estimation circuit of high-speed interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103986462B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615571A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第五十八研究所 | Programmable high-speed differential interface |
| CN107734375A (en) * | 2017-09-22 | 2018-02-23 | 北京嗨动视觉科技有限公司 | Video source synchronous clock generation method and device |
| CN111510117A (en) * | 2020-04-09 | 2020-08-07 | 上海艾为电子技术股份有限公司 | Clock phase control circuit, clock phase control method, power amplification device and audio equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6834093B1 (en) * | 2004-03-19 | 2004-12-21 | National Semiconductor Corporation | Frequency comparator circuit |
| CN201464557U (en) * | 2009-03-16 | 2010-05-12 | 邵啸 | Intermediate frequency spectrum monitoring device |
| CN101871968B (en) * | 2009-04-24 | 2011-12-07 | 郑州威科姆科技股份有限公司 | Reliable time scale pulse measurement method and measurement device thereof |
| CN102030018B (en) * | 2009-09-28 | 2013-01-16 | 西门子信号有限公司 | Attached peripheral data acquisition and distribution device for axis counting system |
-
2014
- 2014-05-30 CN CN201410239560.2A patent/CN103986462B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615571A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第五十八研究所 | Programmable high-speed differential interface |
| CN104615571B (en) * | 2015-01-30 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | programmable high-speed differential interface |
| CN107734375A (en) * | 2017-09-22 | 2018-02-23 | 北京嗨动视觉科技有限公司 | Video source synchronous clock generation method and device |
| CN111510117A (en) * | 2020-04-09 | 2020-08-07 | 上海艾为电子技术股份有限公司 | Clock phase control circuit, clock phase control method, power amplification device and audio equipment |
| CN111510117B (en) * | 2020-04-09 | 2023-06-27 | 上海艾为电子技术股份有限公司 | Clock phase control circuit, clock phase control method, power amplifying device and audio equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103986462B (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7817767B2 (en) | Processor-controlled clock-data recovery | |
| Chun-Zhi et al. | A universal asynchronous receiver transmitter design | |
| CN103986462A (en) | Fast frequency measuring circuit with high-speed interface | |
| CN107872221B (en) | Full-phase digital delay phase-locked loop device and working method | |
| CN103258561A (en) | Data output timing control circuit for semiconductor apparatus | |
| US8423314B2 (en) | Deterministic reconfiguration of measurement modules using double buffered DMA | |
| EP2565782A2 (en) | Slave mode transmit with zero delay for audio interface | |
| CN102723952B (en) | A kind of analog-digital conversion data transmission method, transmitter and modulus conversion chip | |
| CN105677593A (en) | Self-adaption adjustment method and device for write operation timing path of chip storage | |
| US20080065866A1 (en) | Apparatus and method for regulating bursty data in a signal processing pipeline | |
| CN104170252B (en) | Self-correcting multirate filter | |
| CN206060731U (en) | Multichannel digital signal processing platform | |
| CN108573710A (en) | A kind of method and device of real-time removal recording echo | |
| CN203617974U (en) | Configurable coefficient filter and electronic device based on FPGA | |
| CN112838860A (en) | Data output method, device and system | |
| CN104391817B (en) | The electronic system synchronous with ancillary equipment | |
| CN104050121A (en) | Double-receiving double-emitting programmable ARINC 429 communication interface chip | |
| US20210328577A1 (en) | Audio rate conversion system and electronic apparatus | |
| CN109240981A (en) | Synchronous collection method, equipment and the computer readable storage medium of multi-channel data | |
| CN106301644A (en) | A kind of method and apparatus of voice synchronous | |
| CN111446960A (en) | Clock output circuit | |
| CN102045078B (en) | FPGA (Field Programmable Gate Array) based software receiver system and implementation method | |
| CN105335232A (en) | Time sequence multiplexing-based FPGA resource optimization scheme | |
| US7249274B1 (en) | System and method for scalable clock gearing mechanism | |
| US20140053027A1 (en) | Multiple clock domain debug capability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |