CN103795979A - Method and device for synchronizing distributed image stitching - Google Patents
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Abstract
The invention provides a method and device for synchronizing distributed image stitching. The method and device for synchronizing distributed image stitching are applied to a video decoder in a distributed stitching control system. The method comprises the steps that the video decoder decodes video frames output by a stitching controller, and stores decoded video data in a video memory; when display output is interrupted, the theoretical display output time of the nth frame is worked out according to the formula Xn=(Tn-T1)+t1+d; whether the current preset time for displaying the nth frame is longer than or equal to Xn is judged; if yes, the nth frame data are output and are displayed by a sub-display screen corresponding to the decoder; if not, whether the nth frame is displayed or not is judged again in a next display interruption generation period. By the adoption of the method and device for synchronizing distributed image stitching, the time during which images on all output screens are not synchronous can be shortened, and the effect of displaying a stitched image is improved.
Description
Technical field
The present invention relates to field of video monitoring, relate in particular to a kind of distributed image and splice synchronous method and apparatus.
Background technology
The demand of large-screen being watched in order to meet user, large screen splicing technology is more and more applied to field of video monitoring.So-called large screen splicing technology, is by a secondary complete image is divided into many parts, shows and guarantee image various piece simultaneous display on different display devices.At present, each producer realizes large screen splicing by matrix device mostly, belong to the splicing equipment of integrated form, its common solution as depicted in figs. 1 and 2, Fig. 1 is simple matrix device, and not network enabled stream input, if will carry out the tiled display of network flow, front end must connect a Video Decoder for network flow is decoded, and outputting video signal is to matrix device; Fig. 2 is integrated decoder module, simultaneously network enabled stream and vision signal input.
For above-mentioned two kinds of solutions, poor expandability, what between different display modules, transmit is original image after decoding, data volume is large, and owing to adopting integrated form Splicing model, each split screen Image Sharing bandwidth is transmitted, the time that transmitting procedure may cause image to arrive display module produces certain difference, therefore in the time that tiled display is exported, can cause each display module display splicing picture time, produce asynchronous.
Summary of the invention
Based on the problems referred to above, the present invention proposes a kind of distributed image and splices synchronous method, be applied on the Video Decoder in a kind of distributed splicing control system, described distributed splicing control system comprises splicing controller, some Video Decoders and some sub-display screens, wherein said some Video Decoders are all connected in described splicing controller, each Video Decoder connects one or more sub-display screens, and described method comprises:
Steps A, the frame of video that described splicing controller is exported are decoded, and decoded video data are stored in video memory; In the time showing that output is interrupted producing, the theory that calculates n frame according to formula Xn=(Tn-T1)+t1+d shows output time; Wherein Xn represents that the theory of the n frame calculating shows output time; T1 represents to arrive with the first frame after other Video Decoder is synchronizeed the system time of video memory; Described T1 and Tn represent respectively the timestamp carrying in first frame and n frame; Described d represents the described display buffer time, and this time is to show the output integral multiple in interruption generation cycle; Described n is greater than 1 integer; Wherein this decoder produces and shows that time and other decoder that output is interrupted produce the time synchronized that shows that output is interrupted;
Step B, judge that current preparation shows whether the time of n frame is more than or equal to described Xn; If so, exporting these n frame data is shown by sub-display screen corresponding to this decoder; Otherwise, show that until next output re-executes step B while interrupting generation.
Preferably, described Video Decoder receives the multicast message that comprises the order of resetting being sent by described splicing controller, and resets and show pio chip according to the replacement order in this multicast message, shows synchronizeing of output break period and other decoder to realize.
Preferably, described Video Decoder is received after the first frame query messages time of advent sending from described splicing controller, calculating receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory, and this time difference is noticed to described splicing controller, so that time that time difference that described splicing controller can be noticed according to this time difference and other Video Decoders arrives video memory to the first frame of this Video Decoder is carried out and the synchronizeing of other Video Decoder.
Preferably, described splicing controller carried out being specially with synchronizeing of other Video Decoder according to the time that the time difference of this time difference and the notice of other Video Decoders arrives video memory to the first frame of this Video Decoder: splicing controller is take the time difference maximum in the time difference of described notice as benchmark, send the instruction of being adjusted forward to m millisecond the time of the first frame arrival video memory of record to this Video Decoder, wherein m=a-b, a is described maximum time difference, b is that this Video Decoder receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory.
Preferably, in the time that the difference between described time difference and the time difference of described maximum that arbitrary Video Decoder in each Video Decoder calculates exceeds the described display buffer time, splicing controller sends and comprises the message that empties buffering area order to described Video Decoder, described Video Decoder is received after this message, empty the data of screen buffer according to the order that empties buffering area in this message, return to execution step A.
The present invention also proposes a kind of distributed image splicing synchronizer, on the Video Decoder of this application of installation in a kind of distributed splicing control system, described distributed splicing control system also comprises splicing controller, some sub-display screens and other Video Decoder, wherein said each Video Decoder is all connected in described splicing controller, each Video Decoder connects one or more sub-display screens, and this device comprises:
Decoding computing module, for the frame of video of described splicing controller output is decoded, and decoded video data is stored in video memory, and in the time showing that output is interrupted producing, the theory that calculates n frame according to formula Xn=(Tn-T1)+t1+d shows output time; Wherein Xn represents that the theory of the n frame calculating shows output time; T1 represents to arrive with the first frame after other Video Decoder is synchronizeed the system time of video memory; Described T1 and Tn represent respectively the timestamp carrying in first frame and n frame; Described d represents the described display buffer time, and this time is to show the output integral multiple in interruption generation cycle; Described n is greater than 1 integer; Described decoder produces and shows that time and other decoder that output is interrupted produce the time synchronized that shows that output is interrupted;
Output control module, for judging that current preparation shows whether the time of n frame is more than or equal to described Xn; If so, exporting these n frame data is shown by sub-display screen corresponding to this decoder; Otherwise, show until next output rejudges whether export this n frame while interrupting generation.
Preferably, described decoding computing module is further used for: receive the multicast message that comprises the order of resetting being sent by described splicing controller, and reset and show pio chip according to replacement order in this multicast message, show synchronizeing of output break period and other decoder to realize.
Preferably, described decoding computing module is further used for: when receiving after the query messages of first frame time of advent of sending from described splicing controller, calculating receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory, and this time difference is noticed to described splicing controller, so that time that time difference that described splicing controller can be noticed according to this time difference and other Video Decoders arrives video memory to the first frame of this Video Decoder is carried out and the synchronizeing of other Video Decoder.
Preferably, described splicing controller carried out being specially with synchronizeing of other Video Decoder according to the time that the time difference of this time difference and the notice of other Video Decoders arrives video memory to the first frame of this Video Decoder: splicing controller is take the time difference maximum in the time difference of described notice as benchmark, send the instruction of being adjusted forward to m millisecond the time of the first frame arrival video memory of record to this Video Decoder, wherein m=a-b, a is described maximum time difference, b is that this Video Decoder receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory.
Preferably, in the time that the difference between described time difference and the time difference of described maximum that arbitrary Video Decoder in each Video Decoder calculates exceeds the described display buffer time, splicing controller sends and comprises the message that empties buffering area order to described Video Decoder, described output control module is further used for: receive after this message, empty the data of screen buffer according to the order that empties buffering area in this message.
The present invention program, by proposing a kind of distributed decoding tiled display scheme, according to the demonstration opportunity of the every two field picture of the strict control of the timestamp in code stream, thereby reduces each nonsynchronous time of cutout screen picture, promotes stitching image display effect.
Accompanying drawing explanation
Fig. 1 is large screen splicing solution schematic diagram in a kind of prior art;
Fig. 2 is large screen splicing solution schematic diagram in another kind of prior art;
Fig. 3 is the tiled display schematic flow sheet of a kind of distributed splicing control system that proposes of the present invention;
Fig. 4 is that in one embodiment of the present invention, a kind of distributed image splices synchronous method flow diagram;
Fig. 5 is the schematic diagram of selected first frame time of advent in one embodiment of the present invention;
Fig. 6 carries out the first frame synchronous schematic diagram time of advent to the display prot of each sub-display screen in one embodiment of the present invention;
Fig. 7 shows according to timestamp the flow chart of controlling in one embodiment of the present invention;
Fig. 8 is the logic device of a kind of distributed image splicing synchronizer in one embodiment of the present invention.
Embodiment
For the technical problem proposing in background technology, the present invention program proposes a kind of distributed splicing control system, refer to Fig. 3, different from the integrated form Splicing model of available technology adopting is, this distributed splicing control system comprises a splicing control appliance, some Video Decoders and some sub-display screens, wherein said some Video Decoders are all connected in described splicing controller, and each Video Decoder connects one or more sub-display screens.In specific implementation process,, according to splicing business code stream is copied and is distributed on multiple Video Decoders by splicing control appliance, after each Video Decoder is decoded to code stream, according to splicing business, wherein a part of picture of an output image.Certainly,, if Video Decoder is supported multipath decoding output, this Video Decoder can be responsible for exporting multiple parts of picture, as the Video Decoder 1 in Fig. 4.Easy for describing, the frame of the Video Decoder output relating to herein all refers to the part picture of corresponding this frame that needs output of this Video Decoder.Such as the description of the 1st frame that in Fig. 3, decoder 2 is exported is actual refers to the part 2 picture of the 1st frame that decoder 2 exports.
For this distributed splicing control system, the splicing of image is synchronously the problem that cannot avoid.The present invention proposes a kind of synchronous method and apparatus of Image Mosaics that is applicable to this distributed splicing control system.Describe in detail below in conjunction with specific embodiment.
Refer to Fig. 4, the method is carried out following steps:
S401, the frame of video that described splicing controller is exported are decoded, and decoded video data are stored in video memory; In the time showing that output is interrupted producing, the theory that calculates n frame according to formula Xn=(Tn-T1)+t1+d shows output time;
Wherein, Xn represents that the theory of the n frame calculating shows output time; T1 represents to arrive with the first frame after other Video Decoder is synchronizeed the system time of video memory; Described T1 and Tn represent respectively the timestamp carrying in first frame and n frame; Described d represents the described display buffer time, and this time is to show the output integral multiple in interruption generation cycle; Described n is greater than 1 integer; Wherein this decoder produces and shows that time and other decoder that output is interrupted produce the time synchronized that shows that output is interrupted;
S402, judge that current preparation shows whether the time of n frame is more than or equal to described Xn; If so, exporting these n frame data is shown by sub-display screen corresponding to this decoder; Otherwise, show that until next output re-executes step S402 while interrupting generation.
Showing output stage, after every demonstration one two field picture of demonstration pio chip of each Video Decoder, all can produce one and show that output interruption is for arranging next frame image.But, in the system of this distributed splicing, because producing, the demonstration pio chip of each Video Decoder shows that the opportunity of output interruption is inconsistent, can cause the asynchronous of image demonstration.
Therefore, in the present embodiment, the time that need to interrupt the demonstration pio chip generation demonstration of each Video Decoder in advance carries out synchronously.The time that the demonstration output that the demonstration pio chip of each Video Decoder is produced is interrupted is carried out synchronous process, is specifically carried out by splicing controller.In actual utilization, splicing controller can be by control each Video Decoder demonstration pio chip of resetting simultaneously, guarantees that each Video Decoder produces to show that the time that output is interrupted is synchronization.In the preferred mode of one, because splicing controller and each Video Decoder are positioned at same local area network (LAN) in actual applications, therefore splicing controller can send a multicast message that comprises the order of resetting, when each Video Decoder in this network is received after this multicast message, reset to showing pio chip according to the replacement order in this multicast message, export the synchronous of break period to realize demonstration.Because splicing controller and each Video Decoder are positioned at same local area network (LAN), therefore the real-time of multicast message can farthest guarantee that all demonstration pio chips all receive this multicast message simultaneously, produces and shows that the opportunity that output interrupts is consistent thereby realize each decoder.
In the present embodiment, each Video Decoder is received after the frame of video of splicing controller output, be to calculate and control the demonstration of n frame and output time by periodically calling formula Xn=(Tn-T1)+t1+d, wherein the cycle of calling of this formula is that Video Decoder produces the cycle that shows that output is interrupted.In this formula, Tn and T1 are the timestamp carrying in video data.Because timestamp and parameter d are fixed value, therefore in the present embodiment, Xn-t1 is actual is with a fixed value relatively.If the time t1 of the first frame arrival video memory of each Video Decoder record is identical, according to this formula, the theory of the n frame calculating so shows that output time is inevitable identical.Thereby, in order to guarantee that the video memory of each Video Decoder receives that the time t1 of first frame is identical, also need the time t1 that described first frame is arrived to the video memory of each Video Decoder to carry out synchronously.
The time that splicing controller is arrived to video memory to the first frame recording in each Video Decoder referring to accompanying drawing and in conjunction with concrete instance carries out synchronous process and is further described:
In the present embodiment, the first frame of described record arrive time of video memory of each Video Decoder concrete headed by frame arrive after video memory, the next one of record shows that output interrupts the system time producing.Refer to 6, because the time that shows output interruption generation has carried out synchronously in advance, and each Video Decoder video memory receives that the time of first frame may there are differences, therefore identical in order to guarantee that as far as possible the first frame of each Video Decoder record arrives time of video memory, can record when after the actual arrival of first frame video memory, the next system time that shows that output interrupts producing arrives the time of video memory as this head frame.Such as the VO0 in Fig. 5 and VO1, although the real time that first frame arrives is not identical, if but selected first frame arrive the next one recording after video memory show output interrupt time of producing as this head frame the time to video memory, the time t1 that final VO0 and VO1 record is all identical.
But many times, the time difference of first frame arrival different video decoder may be greater than a demonstration and export interrupt cycle, so said method can not be dealt with problems completely.The embodiment of the present invention based on the above method, further operates in such a way.
Carry out when synchronous at the time t1 that the first frame of each Video Decoder record is arrived to video memory, splicing controller can be inquired about and determine that first frame in each Video Decoder arrives the Video Decoder of video memory the earliest by send a multicast message to each decoder, and using the time of first this Video Decoder frame arrival video memory as fiducial value, the time that the first frames of other each Video Decoders is arrived to video memorys with this proofreaies and correct.
But, because the system time of each decoder may be different, the system time of the first frame arrival video memory of each Video Decoder record may be different, therefore in the present embodiment, splicing controller is that the first frame of receiving time of query messages and record by inquiring about each Video Decoder arrives the time difference between the system time of video memory, determines that first frame in each Video Decoder arrives the Video Decoder of video memory the earliest.For example, splicing controller can send a multicast message as query messages to each decoder unification, each decoder is received after this query messages, calculate and receive that the first frame of the system time of this query messages and record arrived after the time difference of time of video memory, this time difference is returned to splicing controller as Query Result.In order to guarantee the reliable of Query Result, splicing controller can be by repeatedly inquiring about to guarantee Query Result.Due to the real-time of multicast message, each decoder receives that the time of query messages can think identical, therefore when splicing controller was received after the described time difference that each Video Decoder returns, the described time difference that can calculate according to different video decoder, judge the Video Decoder that first frame in each Video Decoder arrives video memory the earliest, frame arrives the Video Decoder of video memory the earliest headed by the Video Decoder of the described time difference maximum calculating.
When having confirmed that first frame arrives after the Video Decoder of video memory the earliest, the time difference that splicing controller calculates take this Video Decoder is fiducial value, and the time that the first frame of other Video Decoder records is arrived to video memory proofreaies and correct.Be specially: send the instruction of being adjusted forward to m millisecond the time of the first frame arrival video memory of record to other each Video Decoders, wherein m=a-b, a is the maximum described time difference calculating in described each Video Decoder, and b is that each Video Decoder receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory.For example: refer to Fig. 3 and Fig. 6, to inquire about three times as example, after splicing controller is inquired about by three times, the described time difference of returning by each Video Decoder is finally confirmed the time difference maximum that Video Decoder 1 calculates, it is the Video Decoder that frame arrives video memory the earliest headed by Video Decoder 1, so the first frame that as fiducial value, Video Decoder 2 recorded of the time difference of returning using Video Decoder 1 arrives the time of video memory and proofreaies and correct.Splicing controller is by the further calculated difference of described time difference that Video Decoder 1 and Video Decoder 2 are returned, the first frame that discovery Video Decoder 2 records than Video Decoder 1 arrives time in late two generation cycles that show that output is interrupted of video memory, therefore splicing controller sends to Video Decoder 2 time that first frame arrives video memory and adjusts forward the instruction in 2 cycles, Video Decoder 2 is received after this instruction, the first frame of record is deducted to the time in two demonstration output interruption generation cycles the time of advent, thereby the described first frame that assurance Video Decoder 1 and Video Decoder 2 record arrives the time consistency of video memory.
Wherein, in the present embodiment, when splicing controller is found the described time difference that in each Video Decoder, arbitrary Video Decoder calculates, and the difference between the described time difference that the Video Decoder that described first frame arrives video memory the earliest calculates, while exceeding the display buffer time of each Video Decoder, unification is sent one to each Video Decoder and is comprised the message that empties buffering area order; Each Video Decoder is received after this message, empties after the data of screen buffer separately, re-executes above each step.In the present embodiment, the display buffer time of each Video Decoder is all identical, and simultaneously for the convenient first frame time to each Video Decoder record is adjusted, this display buffer time is the integral multiple that the generation cycle is interrupted in each decoder demonstration output.
By the description to more than the present embodiment, if first frame arrive each Video Decoder video memory time, t1 was identical time, the theory of each Video Decoder n frame that each Video Decoder calculates according to formula Xn=(Tn-T1)+t1+d shows that output time is inevitable identical.Therefore for a Video Decoder, at the demonstration output stage of video, can show that output time shows n frame and exports control according to the theory of the n frame calculating.Such as in the time that Video Decoder prepares n frame show and export, can prepare to show by comparing current system time and the described Xn of n frame, be further confirmed whether to show this n frame.Refer to Fig. 7, system time when tn represents current system preparation demonstration n frame in Fig. 7.Video Decoder obtains n frame data from decoding rear video buffering area, and in the time that system is prepared to show n frame, Video Decoder, by the Xn that compares tn and calculated by above-mentioned formula, determines whether to show this n frame; If described tn is more than or equal to Xn, this frame is exported to corresponding sub-display screen and show; If showing output interrupts every 16.7ms (when 60fps output) and produces once, therefore tn is increasing with the gradient of 16.7ms, in the time of the above condition of first fit, this frame being exported to corresponding sub-display screen shows, now tn is more than or equal to Xn, be less than Xn+16.7ms, within therefore can being controlled to a demonstration output interruption generation cycle nonsynchronous time of frame of video.In addition, if described tn is less than Xn, do not process this frame, treat next to show that output judges whether to show this frame interrupt cycle again.
Certainly, in the present embodiment, splicing controller can periodically use said method synchronous to each Video Decoder being shown to output is interrupted, and the time that described first frame arrives the video memory of each Video Decoder is carried out synchronously, concrete implementation step is identical with the above description of the present embodiment, does not repeat them here.
Describe above by the present embodiment, can learn in the present invention program, splicing controller can be periodically produces to each Video Decoder the time that the first frame that shows opportunity that output is interrupted and output arrives the video memory of each Video Decoder to carry out synchronously, thereby has at utmost avoided because each Video Decoder produces the time errors that opportunity, difference caused that show that output is interrupted.In the present invention, splicing controller reality has only utilized each Video Decoder to receive that the system time of query messages and the first frame of record arrive the time of video memory, the time that the first frame of each Video Decoder is arrived to video memory has carried out synchronously, do not need the system time of different video decoder to carry out synchronously, therefore synchronous effect is more effective.
Please refer to Fig. 8, the present invention also proposes a kind of distributed image splicing synchronizer 80, on the Video Decoder of this application of installation in a kind of distributed splicing control system, described distributed splicing control system also comprises splicing controller, some sub-display screens and other Video Decoder, wherein said each Video Decoder is all connected in described splicing controller, each Video Decoder connects one or more sub-display screens, and this device comprises:
Wherein, Xn represents that the theory of the n frame calculating shows output time; T1 represents to arrive with the first frame after other Video Decoder is synchronizeed the system time of video memory; Described T1 and Tn represent respectively the timestamp carrying in first frame and n frame; Described d represents the described display buffer time, and this time is to show the output integral multiple in interruption generation cycle; Described n is greater than 1 integer; Described decoder produces and shows that time and other decoder that output is interrupted produce the time synchronized that shows that output is interrupted;
In the present embodiment, described decoding computing module is further used for: receive the multicast message that comprises the order of resetting being sent by described splicing controller, and reset and show pio chip according to replacement order in this multicast message, show synchronizeing of output break period and other decoder to realize.
In the present embodiment, described decoding computing module is further used for: when receiving after the query messages of first frame time of advent of sending from described splicing controller, calculating receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory, and this time difference is noticed to described splicing controller, so that time that time difference that described splicing controller can be noticed according to this time difference and other Video Decoders arrives video memory to the first frame of this Video Decoder is carried out and the synchronizeing of other Video Decoder.
In the present embodiment, described splicing controller carried out being specially with synchronizeing of other Video Decoder according to the time that the time difference of this time difference and the notice of other Video Decoders arrives video memory to the first frame of this Video Decoder: splicing controller is take the time difference maximum in the time difference of described notice as benchmark, send the instruction of being adjusted forward to m millisecond the time of the first frame arrival video memory of record to this Video Decoder, wherein m=a-b, a is described maximum time difference, b is that this Video Decoder receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory.
In the present embodiment, in the time that the difference between described time difference and the time difference of described maximum that arbitrary Video Decoder in each Video Decoder calculates exceeds the described display buffer time, splicing controller sends and comprises the message that empties buffering area order to described Video Decoder, described output control module is further used for: receive after this message, empty the data of screen buffer according to the order that empties buffering area in this message.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (10)
1. a distributed image splices synchronous method, be applied on the Video Decoder in a kind of distributed splicing control system, it is characterized in that, described distributed splicing control system comprises splicing controller, some Video Decoders and some sub-display screens, wherein said some Video Decoders are all connected in described splicing controller, each Video Decoder connects one or more sub-display screens, and described method comprises:
Steps A, the frame of video that described splicing controller is exported are decoded, and decoded video data are stored in video memory; In the time showing that output is interrupted producing, the theory that calculates n frame according to formula Xn=(Tn-T1)+t1+d shows output time; Wherein Xn represents that the theory of the n frame calculating shows output time; T1 represents to arrive with the first frame after other Video Decoder is synchronizeed the system time of video memory; Described T1 and Tn represent respectively the timestamp carrying in first frame and n frame; Described d represents the described display buffer time, and this time is to show the output integral multiple in interruption generation cycle; Described n is greater than 1 integer; Wherein this decoder produces and shows that time and other decoder that output is interrupted produce the time synchronized that shows that output is interrupted;
Step B, judge that current preparation shows whether the time of n frame is more than or equal to described Xn; If so, exporting these n frame data is shown by sub-display screen corresponding to this decoder; Otherwise, show that until next output re-executes step B while interrupting generation.
2. the method for claim 1, it is characterized in that, described Video Decoder receives the multicast message that comprises the order of resetting being sent by described splicing controller, and reset and show pio chip according to replacement order in this multicast message, show synchronizeing of output break period and other decoder to realize.
3. method as claimed in claim 2, it is characterized in that, described Video Decoder is received after the first frame query messages time of advent sending from described splicing controller, calculating receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory, and this time difference is noticed to described splicing controller, so that time that time difference that described splicing controller can be noticed according to this time difference and other Video Decoders arrives video memory to the first frame of this Video Decoder is carried out and the synchronizeing of other Video Decoder.
4. method as claimed in claim 3, it is characterized in that, described splicing controller carried out being specially with synchronizeing of other Video Decoder according to the time that the time difference of this time difference and the notice of other Video Decoders arrives video memory to the first frame of this Video Decoder: splicing controller is take the time difference maximum in the time difference of described notice as benchmark, send the instruction of being adjusted forward to m millisecond the time of the first frame arrival video memory of record to this Video Decoder, wherein m=a-b, a is described maximum time difference, b is that this Video Decoder receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory.
5. method as claimed in claim 4, it is characterized in that, in the time that the difference between described time difference and the time difference of described maximum that arbitrary Video Decoder in each Video Decoder calculates exceeds the described display buffer time, splicing controller sends and comprises the message that empties buffering area order to described Video Decoder, described Video Decoder is received after this message, empty the data of screen buffer according to the order that empties buffering area in this message, return to execution step A.
6. a distributed image splicing synchronizer, on the Video Decoder of this application of installation in a kind of distributed splicing control system, it is characterized in that, described distributed splicing control system also comprises splicing controller, some sub-display screens and other Video Decoder, wherein said each Video Decoder is all connected in described splicing controller, each Video Decoder connects one or more sub-display screens, and this device comprises:
Decoding computing module, for the frame of video of described splicing controller output is decoded, and decoded video data is stored in video memory, and in the time showing that output is interrupted producing, the theory that calculates n frame according to formula Xn=(Tn-T1)+t1+d shows output time; Wherein Xn represents that the theory of the n frame calculating shows output time; T1 represents to arrive with the first frame after other Video Decoder is synchronizeed the system time of video memory; Described T1 and Tn represent respectively the timestamp carrying in first frame and n frame; Described d represents the described display buffer time, and this time is to show the output integral multiple in interruption generation cycle; Described n is greater than 1 integer; Described decoder produces and shows that time and other decoder that output is interrupted produce the time synchronized that shows that output is interrupted;
Output control module, for judging that current preparation shows whether the time of n frame is more than or equal to described Xn; If so, exporting these n frame data is shown by sub-display screen corresponding to this decoder; Otherwise, show until next output rejudges whether export this n frame while interrupting generation.
7. Video Decoder as claimed in claim 6, it is characterized in that, described decoding computing module is further used for: receive the multicast message that comprises the order of resetting being sent by described splicing controller, and reset and show pio chip according to replacement order in this multicast message, show synchronizeing of output break period and other decoder to realize.
8. Video Decoder as claimed in claim 7, it is characterized in that, described decoding computing module is further used for: when receiving after the query messages of first frame time of advent of sending from described splicing controller, calculating receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory, and this time difference is noticed to described splicing controller, so that time that time difference that described splicing controller can be noticed according to this time difference and other Video Decoders arrives video memory to the first frame of this Video Decoder is carried out and the synchronizeing of other Video Decoder.
9. Video Decoder as claimed in claim 8, it is characterized in that, described splicing controller carried out being specially with synchronizeing of other Video Decoder according to the time that the time difference of this time difference and the notice of other Video Decoders arrives video memory to the first frame of this Video Decoder: splicing controller is take the time difference maximum in the time difference of described notice as benchmark, send the instruction of being adjusted forward to m millisecond the time of the first frame arrival video memory of record to this Video Decoder, wherein m=a-b, a is described maximum time difference, b is that this Video Decoder receives that the system time of described query messages and the first frame of record arrive the time difference of the system time of video memory.
10. Video Decoder as claimed in claim 9, it is characterized in that, in the time that the difference between described time difference and the time difference of described maximum that arbitrary Video Decoder in each Video Decoder calculates exceeds the described display buffer time, splicing controller sends and comprises the message that empties buffering area order to described Video Decoder, described output control module is further used for: receive after this message, empty the data of screen buffer according to the order that empties buffering area in this message.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6636269B1 (en) * | 1999-08-18 | 2003-10-21 | Webtv Networks, Inc. | Video timing system and method |
| CN101000755A (en) * | 2006-12-21 | 2007-07-18 | 康佳集团股份有限公司 | Multi-screen display splicing controller |
| CN101256762A (en) * | 2008-03-21 | 2008-09-03 | 广东威创视讯科技股份有限公司 | Multiple-screen splitting and jointing method and device |
| CN101295235A (en) * | 2008-06-04 | 2008-10-29 | 广东威创视讯科技股份有限公司 | Distributed digital processing system and method |
| CN101807389A (en) * | 2010-03-19 | 2010-08-18 | 上海博康智能网络科技有限公司 | Large screen splicing method and system |
| CN102510494A (en) * | 2011-10-09 | 2012-06-20 | 杭州华三通信技术有限公司 | Method and device for synchronizing I frame |
| CN102752642A (en) * | 2012-06-18 | 2012-10-24 | 李洋 | Method and system for synchronously broadcasting multi-terminal video based on IP (internet protocol) network |
| CN103402140A (en) * | 2013-08-01 | 2013-11-20 | 深圳英飞拓科技股份有限公司 | Distributed IP (Internet Protocol) video decoder synchronous stitching and on-wall method and system |
-
2014
- 2014-01-23 CN CN201410031868.8A patent/CN103795979B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6636269B1 (en) * | 1999-08-18 | 2003-10-21 | Webtv Networks, Inc. | Video timing system and method |
| CN101000755A (en) * | 2006-12-21 | 2007-07-18 | 康佳集团股份有限公司 | Multi-screen display splicing controller |
| CN101256762A (en) * | 2008-03-21 | 2008-09-03 | 广东威创视讯科技股份有限公司 | Multiple-screen splitting and jointing method and device |
| CN101295235A (en) * | 2008-06-04 | 2008-10-29 | 广东威创视讯科技股份有限公司 | Distributed digital processing system and method |
| CN101807389A (en) * | 2010-03-19 | 2010-08-18 | 上海博康智能网络科技有限公司 | Large screen splicing method and system |
| CN102510494A (en) * | 2011-10-09 | 2012-06-20 | 杭州华三通信技术有限公司 | Method and device for synchronizing I frame |
| CN102752642A (en) * | 2012-06-18 | 2012-10-24 | 李洋 | Method and system for synchronously broadcasting multi-terminal video based on IP (internet protocol) network |
| CN103402140A (en) * | 2013-08-01 | 2013-11-20 | 深圳英飞拓科技股份有限公司 | Distributed IP (Internet Protocol) video decoder synchronous stitching and on-wall method and system |
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|---|---|---|---|---|
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| CN113287323B (en) * | 2019-01-08 | 2023-08-18 | 高通股份有限公司 | Method, client device and computer readable medium for retrieving media data |
| CN110809041A (en) * | 2019-10-30 | 2020-02-18 | 北京百度网讯科技有限公司 | Data synchronization method and device, electronic equipment and storage medium |
| CN110809041B (en) * | 2019-10-30 | 2023-06-27 | 北京百度网讯科技有限公司 | Data synchronization method and device, electronic equipment and storage medium |
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