CN107731830B - A kind of polysilicon plug forming method improving depth consistency - Google Patents
A kind of polysilicon plug forming method improving depth consistency Download PDFInfo
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- CN107731830B CN107731830B CN201710755338.1A CN201710755338A CN107731830B CN 107731830 B CN107731830 B CN 107731830B CN 201710755338 A CN201710755338 A CN 201710755338A CN 107731830 B CN107731830 B CN 107731830B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The present invention provides a kind of polysilicon plug forming method for improving depth consistency, the method carries out plug oxide filling in channel hole and does not use back carving technology, but deposition forms the polysilicon of plug after carrying out planarization process；In the ion implanting for carrying out the doping of p type to the polysilicon for forming plug；And the ion implanting of the N type doping (N+) of high concentration is carried out at the top of channel hole using photo etched mask；To form the polysilicon plug that top has PN junction structure.By the above method, so that the mode for forming PN junction substitutes the consistency that the method that existing time is carved plug oxide and deposit polycrystalline silicon improves polysilicon plug depth；So that the raising of polysilicon plug depth consistency, so that cut-in voltage (Vt) consistency of top selection gate (TSG) is more preferable, to improve the performance of 3D nand flash memory.
Description
Technical field
The present invention relates to improve polysilicon plug in field of semiconductor manufacture more particularly to a kind of 3D NAND flash memory structure
The method of depth consistency.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and most ask being produced into for lower unit storage unit
This, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memory and 3D NAND
(3D and non-) flash memory.
Currently, as shown in figs. la-ld, including the following steps: in the polysilicon plug preparation process of 3D NAND structure
S1: referring to Fig. 1 a, using the method for atomic layer deposition (Atomic Layer Deposition, abbreviation ALD) in ditch
Deposition oxide 1-1 in road hole (Channel Hole)；
S2: referring to Fig. 1 b, returns and carves (Recess Etch Back) oxide 1-1, wherein returning quarter includes being carved using dry method
The step of erosion and wet etching；
S3: Fig. 1 c, the deposition of polysilicon plug 1-2 are referred to；
S4: referring to Fig. 1 d, planarizes surface using chemical mechanical grinding (CMP).
However in above-mentioned technique, have the following deficiencies:
Using dry etching return carve oxide 1-1 when, due in each channel hole return carve depth it is uneven, cause
The depth that subsequent polysilicon plug deposits in each channel is uneven, i.e., deposit depth is inconsistent；And polysilicon plug is heavy
Product depth will affect the cut-in voltage (Vt) of top selection gate (TSG)；The deposit depth of polysilicon plug in multiple channel holes
The inconsistent cut-in voltage that will lead to top selection gate (TSG) is unevenly distributed.
With specific reference to shown in Fig. 2, wherein the height of top selection gate (TSG) to oxide top is defined as H3 (BL-
B), the height and at the top of oxide top to polysilicon plug is defined as H2 (BL-T), the unlatching electricity of top selection gate (TSG)
Press (Vt) higher for the susceptibility of H2/H3, the inconsistent of ratio leads to selection gate (TSG) cut-in voltage at the top of each section
It is inconsistent, as shown in Figure 3.
This inconsistent performance that will affect 3D nand flash memory entirety, therefore, how to effectively control the filling of oxide and
The depth consistency of etching and polysilicon plug is endeavoured always the direction of research by those skilled in the art.
Summary of the invention
It is deep by improving the purpose of the present invention is to provide a kind of polysilicon plug forming method for improving depth consistency
It spends consistency and keeps the consistency of the cut-in voltage of top selection gate more preferable, to improve the performance of 3D nand flash memory.
To achieve the goals above, the invention proposes it is a kind of improve depth consistency polysilicon plug forming method,
The following steps are included:
The substrate stacked structure for having channel hole is provided；
The filling of plug oxide is carried out in channel hole, and plug oxide skin(coating) is also formed on stacked structure；
Planarization process is carried out, removes the plug oxide skin(coating) above stacked structure, and terminate at stacked structure top layer
Medium of oxides layer；
Deposition forms the polysilicon of plug；
The ion implanting of p type doping is carried out to the polysilicon for forming plug；
Photoresist is coated, and forms photoengraving pattern；The photoengraving pattern be upper surface step structure (Stair Step,
SS) formed on contact zone by the top of channel hole and the photoetching band with a photoetching critical size；
The ion implanting of the N type doping (N+) of high concentration is carried out in the photoetching banded zone；
The extra photoresist in removal top.
Further, the oxide, which is filled with, fills (ALD) using atomic layer deposition method.
Further, the planarization process is using chemical mechanical grinding processing (CMP).
Further, the plug oxide is ethyl orthosilicate (TEOS).
Further, the polysilicon for forming plug that deposits is using low-pressure chemical vapor deposition (LPCVD).
Further, the photoetching critical size is 40nm bigger than the critical size of existing polysilicon plug；And Aligning degree
(OVL) it is less than 15nm.
Compared with prior art, the beneficial effects are mainly reflected as follows:
First, since there is no use go back to the step of carving plug oxide, polysilicon plug bottom to top selection gate
(TSG) height is exactly the thickness after plug oxide deposition film, and therefore, depth consistency is more preferable in each channel hole.
Second, and polysilicon plug itself is using the thickness of the polysilicon film of low-pressure chemical vapor deposition, therefore, each ditch
The depth consistency of polysilicon plug is more preferable in road hole.
Third forms p type polysilicon matrix by the way of the injection of p type Doped ions, for controlling top selection
The cut-in voltage (Vt) of grid (TSG), consistency is more preferable.
4th, photoetching band is formed on channel hole top using photo etched mask, and carry out the ion note of N type doping (N+)
Enter, so that the mode for forming PN junction, which substitutes the method that existing time is carved plug oxide and deposit polycrystalline silicon, improves polysilicon plug
The consistency of depth.
5th, due to the raising of polysilicon plug depth consistency, thus the cut-in voltage of top selection gate (TSG)
(Vt) consistency is more preferable, to improve the performance of 3D nand flash memory.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 a-d, for the polysilicon plug preparation technology flow chart of 3D NAND structure in the prior art；
Fig. 2, for the inconsistent microphoto of the polysilicon plug depth of 3D NAND structure in the prior art；
Fig. 3 inconsistent leads to top selection gate for the polysilicon plug depth of 3D NAND structure in the prior art
(TSG) the inconsistent test curve of cut-in voltage；
Fig. 4 a-g is the polysilicon plug preparation technology flow chart of 3D NAND structure in embodiment of the present invention.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 4 a-f is please referred to, in the present embodiment, the invention proposes a kind of polysilicon plugs for improving depth consistency
Forming method, comprising the following steps:
S100: Fig. 4 a is referred to, the substrate stacked structure 400 with channel hole is provided；Top selection gate (TSG) arrives in figure
The height of top layer's silicon nitride is H1；
S200: referring to Fig. 4 a, and plug oxide 401 is carried out in channel hole and is filled, and is also formed on stacked structure
Plug oxide skin(coating)；The oxide, which is filled with, fills (ALD) using atomic layer deposition method；The plug oxide is positive silicic acid
Ethyl ester (TEOS)；
S300: referring to Fig. 4 b, carries out planarization process, removes the plug oxide skin(coating) above stacked structure, and terminate at
The medium of oxides layer of stacked structure top layer；The planarization process is using chemical mechanical grinding processing (CMP)；
S400: referring to Fig. 4 c, and deposition forms the polysilicon 402 of plug；The deposition forms the polysilicon of plug to use
Low-pressure chemical vapor deposition (LPCVD)
S500: referring to Fig. 4 d, and the ion implanting of p type doping is carried out to the polysilicon 402 for forming plug；
S600: referring to Fig. 4 e and Fig. 4 f, and wherein Fig. 4 e is top view；Photoresist is coated, and forms photoengraving pattern；The light
Needle drawing case is to be formed on the contact zone upper surface step structure (Stair Step, SS) by the top of channel hole and with a light
Carve the photoetching band of critical size；403 be the polysilicon after the injection of p class Doped ions in figure；404 is at the top of channel hole, 405 are
Virtual channel hole (Dummy CH), 406 be the photoetching band for intending being formed after exposure photo-etching glue；407 be photoresist exposure mask；Described
Photoetching banded zone carries out the ion implanting of the N type doping (N+) of high concentration；
S700: referring to Fig. 4 g, and the extra photoresist in removal top forms top P class Doped ions injection region 403 and N class
The polysilicon plug with PN junction structure of Doped ions injection region 408.
To sum up, since there is no use go back to the step of carving plug oxide, polysilicon plug bottom to top selection gate
(TSG) height is exactly the thickness after plug oxide deposition film, and polysilicon plug itself is using low pressure chemical phase
The thickness of the polysilicon film of deposition forms p type polysilicon matrix by the way of the injection of p type Doped ions；Using photoetching
Exposure mask forms photoetching band on channel hole top, and carries out the ion implanting of N type doping (N+), to form the mode of PN junction
Substitute the consistency that the method that existing time is carved plug oxide and deposit polycrystalline silicon improves polysilicon plug depth；So that polycrystalline
The raising of silicon plug depth consistency, so that cut-in voltage (Vt) consistency of top selection gate (TSG) is more preferable, to improve
The performance of 3D nand flash memory.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (6)
1. a kind of polysilicon plug forming method for improving depth consistency, which comprises the following steps:
The substrate stacked structure for having channel hole is provided；
The filling of plug oxide is carried out in channel hole, and plug oxide skin(coating) is also formed on stacked structure；
Planarization process is carried out, removes the plug oxide skin(coating) above stacked structure, and terminate at the oxygen of stacked structure top layer
Compound dielectric layer；
Deposition forms the polysilicon of plug；
The ion implanting of p type doping is carried out to the polysilicon for forming plug；
Photoresist is coated, and forms photoengraving pattern；The photoengraving pattern is to connect in upper surface step structure (Stair Step, SS)
Formed in touching area by the top of channel hole and the photoetching band with a photoetching critical size；
The ion implanting of the N type doping (N+) of high concentration is carried out in the photoetching banded zone；
The extra photoresist in removal top.
2. improving the polysilicon plug forming method of depth consistency as described in claim 1, which is characterized in that the oxidation
Object, which is filled with, fills (ALD) using atomic layer deposition method.
3. improving the polysilicon plug forming method of depth consistency as described in claim 1, which is characterized in that described flat
Change processing using chemical mechanical grinding processing (CMP).
4. improving the polysilicon plug forming method of depth consistency as claimed in claim 1 or 2, which is characterized in that described
Plug oxide is ethyl orthosilicate (TEOS).
5. improving the polysilicon plug forming method of depth consistency as described in claim 1, which is characterized in that the deposition
The polysilicon for forming plug is using low-pressure chemical vapor deposition (LPCVD).
6. improving the polysilicon plug forming method of depth consistency as described in claim 1, which is characterized in that the photoetching
Critical size is 40nm bigger than the critical size of existing polysilicon plug；And Aligning degree (OVL) is less than 15nm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710755338.1A CN107731830B (en) | 2017-08-29 | 2017-08-29 | A kind of polysilicon plug forming method improving depth consistency |
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| CN201710755338.1A CN107731830B (en) | 2017-08-29 | 2017-08-29 | A kind of polysilicon plug forming method improving depth consistency |
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| US10566388B2 (en) * | 2018-05-27 | 2020-02-18 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical memory |
| CN110233152B (en) * | 2019-07-19 | 2020-06-12 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory and three-dimensional memory |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711149A (en) * | 2015-11-12 | 2017-05-24 | 旺宏电子股份有限公司 | Vertical channel structure |
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| KR100398037B1 (en) * | 2000-12-05 | 2003-09-19 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory |
| US20050287793A1 (en) * | 2004-06-29 | 2005-12-29 | Micron Technology, Inc. | Diffusion barrier process for routing polysilicon contacts to a metallization layer |
| US7465650B2 (en) * | 2005-04-14 | 2008-12-16 | Micron Technology, Inc. | Methods of forming polysilicon-comprising plugs and methods of forming FLASH memory circuitry |
| US8395206B2 (en) * | 2008-10-09 | 2013-03-12 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN106128996A (en) * | 2016-06-24 | 2016-11-16 | 武汉新芯集成电路制造有限公司 | A kind of forming method of seamless polysilicon plug |
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| CN106711149A (en) * | 2015-11-12 | 2017-05-24 | 旺宏电子股份有限公司 | Vertical channel structure |
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