CN107729269A - A kind of NANDFlash to FPGA internal blocks RAM caching method - Google Patents
A kind of NANDFlash to FPGA internal blocks RAM caching method Download PDFInfo
- Publication number
- CN107729269A CN107729269A CN201710900372.3A CN201710900372A CN107729269A CN 107729269 A CN107729269 A CN 107729269A CN 201710900372 A CN201710900372 A CN 201710900372A CN 107729269 A CN107729269 A CN 107729269A
- Authority
- CN
- China
- Prior art keywords
- data
- bram
- nandflash
- fpga
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a kind of NANDFlash to FPGA internal blocks RAM caching method, during MCU read-writes NANDFlash, using logical operation powerful FPGA and convenient Sequential Circuit Design ability, frequency-dividing clock avoids the clock for reading NANDFlash and write-in BRAM clock conflict.By way of data buffer storage, 28 data of reading are spliced into write-in BRAM 16 data, under DMA write instruction, by the data write-in BRAM of latch.Cumulative with the ensure that write-in data continuity in automatic address, when quickly reading BRAM data, under MCU control instruction, sends the data in BRAM to slave computer.By the use of FPGA as middle bridge, hardware circuit is simplified, reduces cost, solves the problems, such as that MCU reads NANDFlash data committed memories, so as to alleviate MCU load.
Description
Technical field
The invention belongs to field of electron design automation, and in particular to a kind of MCU control, from NANDFlash to FPGA in
The DMA cache implementing methods of the multiple block RAMs in portion.
Background technology
Medical dynamic electro-cardiac monitor, automobile travel recorder and portable intelligent instrument for being worn with oneself in life etc.
Small volume, the data collecting system that low in energy consumption, memory capacity is big, data can preserve for a long time are needed, it is general to use
NANDFlash data storages.NANDFlash uses serial structure, and capacity is high, price is low, and hardware interface and software programming are simple.
But because NANDFlash does not have single address and data/address bus, NANDFlash carrys out serial access number using the I/O mouths of complexity
Be used for transmitting control, address and data message according to, 8 I/O pins, NANDFlash data write be based on page programs,
In the presence of take CPU, dependent on flash translation layer (FTL) the defects of, thus limit the performance of control system, it is difficult to higher to frequency
Data are gathered in real time.The FPGA of Xilinx companies SP3 series provides 16 dual-ports BRAM, each BRAM and includes 18Kb
Rapid static RAM, wherein 16Kb are used for data storage for position, and 2Kb is used for even-odd check or extra " adding " data bit in addition.BRAM
The data storage of a variety of bit wide forms is supported, it reads and writes the maximum reachable 300MHz of clock, can easily meet data in FPGA
Cache.
The content of the invention
The defects of in order to overcome above-mentioned prior art to exist and deficiency, the invention provides a kind of based on FPGA's
NANDFlash mitigates CPU burdens to the DMA data cache implementing method of block RAM.The I/O that FPGA has up to up to a hundred draws
Pin, substantial amounts of peripheral hardware can be connected, while FPGA and cans easily carry out the design of sequence circuit.Intermediate axle is made using FPGA
Beam, both solved the pin occupation problem that MCU accesses NANDFlash, and facilitated the storage of data, at the same by FPGA inside
Two-port RAM, NANDFlash data fast cache is realized, system architecture and placement-and-routing is simplified, reduces cost.
To reach above-mentioned purpose, a kind of DMA numbers based on FPGA NANDFlash to multiple block RAMs of the present invention
According to cache implementing method, mainly include the following steps that：
1) middle bridge is made using FPGA in hardware design, there is the characteristics of individual I/O pins up to a hundred with reference to FPGA, by MCU
It is distributed in around FPGA, data exchange is carried out with bus mode and FPGA.FPGA is connected by I/O port with NANDFlash, is reduced
The occupancy of MCU pins, extend MCU RAM.
2) MCU read-writes NANDFlash control is realized on software, the design of sequence circuit is carried out primarily directed to FPGA.
By MCU and high four bit address and address latch signal of FPGA address buses, Read-write Catrol is needed by combining gating
Device.
3) to realize that the DMA data of NANDFlash to multiple block RAMs caches, mainly including following components.Write-in
BRAM controllers：NANDflash data, latch data, write-in data are read, address is added up.Read BRAM controllers：Read data, lock
Deposit data, address are added up.
4) to realize above-mentioned reading and writing BRAM controllers, frequency-dividing clock is established inside FPGA.In different clocks under,
Reading and writing BRAM controllers are operated.
5) to realize above-mentioned frequency-dividing clock, system clock four is divided and carries out phase modulation, four is obtained and is in respectively not
Frequency-dividing clock Clk_4S [0], Clk_4S [1], Clk_4S [2] and Clk_4S [3] in same-phase.
6) it is total by MCU and FPGA address bus and data to realize the function of the write-in BRAM controllers of above-mentioned steps 3
Line, the NANDFlash addresses of target are written in address latch, the trigger controller under MCU instruction, DMA is continuously read
Set is instructed, starts four frequency-dividing clocks, starts that continuously NANDflash data high-speeds are cached in BRAM.
7) for realize it is above-mentioned NANDflash data are continuously cached in BRAM, utilize the frequency-dividing clock of step 5.
Under frequency-dividing clock Clk_4S [0] driving, NANDflash data are read, under Clk_4S [1] clock, are saved the data in
In data buffer, under frequency-dividing clock Clk_4S [2], the data in latch are written in BRAM.Then in frequency dividing
Clock Clk_4S [3] adds 1 automatically along lower counter, and address accumulator adds 1 automatically.Then dock cycles, realize that continuous clock caches,
When data counter reaches number of targets, data buffer storage stops.
8) to realize above-mentioned reading BRAM controllers, by MCU and FPGA address bus and data/address bus, by target
BRAM addresses are written in address latch, the trigger controller under MCU instruction, the continuous reading instruction set of DMA, start four points
Frequency clock, start continuous high speed and read BRAM data.
9) it is to realize that above-mentioned continuous high speed reads BRAM data, the frequency-dividing clock of step 5, in frequency-dividing clock Clk_4S
[0] under driving, BRAM data are read, are cached under the driving of Clk_4S [1] in data latches, in Clk_4S [3]
Under clock, BRAM adds up address.
The invention has the advantages that：
DMA data cache implementing method of the present invention based on FPGA NANDFlash to multiple block RAMs, MCU are read
During writing NANDFlash, using logical operation powerful FPGA and convenient Sequential Circuit Design ability, cleverly design
Frequency-dividing clock, avoid the clock for reading NANDFlash and write-in BRAM clock conflict.By way of data buffer storage,
28 data of reading are spliced into write-in BRAM 16 data, under DMA write instruction, the data of latch are write into BRAM
In.Cumulative with the ensure that write-in data continuity in automatic address, when quickly reading BRAM data, in MCU control instruction
Under, send the data in BRAM to slave computer.By the use of FPGA as middle bridge, hardware circuit is not only simplify, is dropped
Low cost, also solve the problems, such as that MCU reads NANDFlash data committed memories, so as to alleviate MCU load.
Brief description of the drawings
Fig. 1 is the system architecture schematic diagram of the present invention.
Fig. 2 is that the simulation experiment result figure that NANDFlash writes BRAM is read in the embodiment of the present invention one.
Fig. 3 is the simulation experiment result figure that BRAM is read in the embodiment of the present invention one.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings：
The implementation method of more MCU read-writes NANDFlash of the present invention based on FPGA, is mainly included the following steps that：
To reach above-mentioned purpose, a kind of DMA numbers based on FPGA NANDFlash to multiple block RAMs of the present invention
According to cache implementing method, mainly include the following steps that：
1) middle bridge is made using FPGA in hardware design, MCU is distributed in around FPGA, entered with bus mode and FPGA
Row data exchange, FPGA are connected by I/O pin with NANDFlash.
2) MCU read-writes NANDFlash control is realized on software, the design of sequence circuit is carried out primarily directed to FPGA.
Using the powerful logical relations of FPGA itself, the modular unit that can be called is write in FPGA.It is more due to be carried out in FPGA
The control of kind function, difference in functionality module will rely on different read/write address realize, therefore be addressed first in FPGA
Design, chip selection signal CS is designed by high four bit address and address latch signal ALE of MCU and FPGA address buses
[16] (2^4=16 chip selection signal), CS [16] are mainly responsible for the MCU module that gating needs to read and write；Utilize MCU low five ground
Location and address latch signal ALE design address signal MCUportL [32] (2^5=32 address signal), MCUportL [32]
It is main to be responsible for more detailed Read-write Catrol in each MCU module of gating.
3) operation for writing BRAM is divided into three parts：NANDflash data, latch data, write-in data are read, address is added up.
4) DMA reads NANDFlash clock and DMA writes data into BRAM clock and do not clashed to make, to being
System clock has carried out clock four and has divided clk_12M_4S, and the division function of clock four will be in the enable signal DMAflag of dma controller
Start after set, main MCU is configured with the control sequential of NANDFlash read operations before DMAflag set, and there is provided DMA readings
The initial address of the NANDFlash address sections taken.
5) dma controller reads data in clk_12M_4S [0] rising edge clocks from NANDFlash, due to NANDFlash
Data bit be 8, the dual port data position of six BRAM blocks of use is 16, thus dma controller need will successively
28 data read are spliced into write-in BRAM 16 data, and by setting ByteL signals, the signal is in clk_12M_4S
[1] inversion operation is carried out under the trailing edge of clock signal, it is low that DMA, which reads NANDFlash read signal nRD in ByteL signals,
In the data deposit register nD_L_Buf read during level, data and lock that nRD is read when ByteL signals are changed into high level
The data that nD_L_Buf be present together form the data for needing to write BRAM；
6) finally, dma controller write-in BRAM write signal clock D_WR takes clk_ when ByteL signals are high level
Triggered during 12M_4S [1] clock signal set, the data for being latched in nDtoDRam are write into BRAM.When write signal resets, write
BRAM address will be added up, and ensure the continuity of write-in BRAM data, when the data amount check of write-in reaches the number of setting
When, illustrate to write data completion, now write BRAM complement mark DMAdone set, write marking signal DMAflag resets, illustrate DMA
Controller reads NANDFlash and writes BRAM and terminate.NRD, ByteL and D_WR signal mutually stagger under sub-frequency clock signal, protect
The correctness of continuous read-write data is demonstrate,proved.
7) operation for entirely reading BRAM is divided into three parts：Reading data, latch data, address are added up.
8) after reading BRAM enabler flags Rd_Bram_En set, the division function of clock four will start, by four frequency-dividing clocks
Clk12M_4S [0] be defined as read BRAM clocks Rd_Bram_clk, clk12M_4S [1] be defined as latch read data clock
Lock_Bram_clk, clk12M_4S [2] are defined as the cumulative clock Addr_Cnt_Clk in Bram addresses, avoid reading wrong with this
By mistake.
9) before dma controller reads NANDFlash data write-in BRAM for the first time, initialization has been carried out to reading BRAM and set
Put, it is main to include resetting BRAM port selection switch Sel_Bram_Flag, ensure to write A ports during low level, read B
Port, while the address initialization that BRAM will be read, make the address corresponding with the address for writing BRAM, ensure that reading is correct.
10) read data for the first time and enable Rd_Bram_Start_En to be started by main MCU, hereafter read every time data it is enabled by
Triggered after speed control signal set, after reading three data every time, stored count mark Addr_Cnt_Flag set, then
The enabled reset of data will be read, shows that reading BRAM terminates.
Embodiment one
With reference to specific embodiment, the present invention is described in detail.Following examples will be helpful to the technology of this area
Personnel further understand the present invention, but the invention is not limited in any way.It should be noted that the different technologies to this area
For personnel, in the case where not departing from the concept thereof of the present invention, various modifications and improvements can be made.This is all in the present invention
In protection domain.
In the present embodiment,, will so that robot task space tracking plans pose data transfer as an example with reference to figure 1 and Fig. 2
The position sequence in each joint of robot of generation is stored in NANDFlash, and the position sequence of each axle is read by MCU,
Because joint requires high to real-time property, by the data buffer storage in NANDFlash in BRAM, to meet joint drive control
The requirement of real-time.First, the position sequence in each joint is generated offline, is written to by MCU in NANDFlash.Instructed in MCU
Under signal, the desired value of starting is written in FPGA register, DMA signal position set in the case where writing BRAM controllers, is read
Go out the data stored in NANDFlash, write in BRAM.MCU reads cache module Block by FPGA internal bus
Data in RAM, and position control module is sent to, the track following in joint is realized using PD control.
Fig. 2 has illustrated the function of the dma controller, make dma controller from 8 data that NANDFlash to be read according to
Secondary is 0x06~0x0D (binary representation is 0b00000110~0b00001101), through Xilinx ISim software emulations
16 data that BRAM is written after experiment are that (binary representation is by 0x0706,0x0908,0x0B0A
0b0000011100000110,0b0000100100001000,0b0000101100001010), what is set here only writes three
Data, so the 3rd data write complete mark DMAdone set after writing, dma controller write operation is completed.
Claims (7)
- A kind of 1. NANDFlash to FPGA internal blocks RAM caching method, it is characterised in that：1) middle bridge is made using FPGA in hardware design, there is the characteristics of individual I/O pins up to a hundred with reference to FPGA, MCU is distributed Around FPGA, data exchange is carried out with bus mode and FPGA；2) MCU read-writes NANDFlash control is realized on software, the design of sequence circuit is carried out primarily directed to FPGA.Pass through MCU and high four bit address and address latch signal of FPGA address buses, the read-write controller needed is gated by combining；3) to realize that the DMA data of NANDFlash to multiple block RAMs caches, mainly including following components.Write BRAM controls Device processed：NANDflash data, latch data, write-in data are read, address is added up.Read BRAM controllers：Read data, latch data, Add up address.
- A kind of 2. NANDFlash to FPGA internal blocks RAM according to claim 1 caching method, it is characterised in that Reading and writing BRAM controllers establish frequency-dividing clock inside FPGA, and in different clocks under, reading and writing BRAM controllers are carried out Operation.
- A kind of 3. NANDFlash to FPGA internal blocks RAM according to claim 2 caching method, it is characterised in that institute The frequency-dividing clock stated, system clock four is divided and carries out phase modulation, obtains four frequency-dividing clocks being in respectively in out of phase Clk_4S [0], Clk_4S [1], Clk_4S [2] and Clk_4S [3].
- 4. a kind of NANDFlash to FPGA internal blocks RAM according to claim 2 caching method, it is characterised in that read BRAM controllers, by MCU and FPGA address bus and data/address bus, the NANDFlash addresses of target are written to address lock In storage, the trigger controller under MCU instruction, the continuous reading instruction set of DMA, start four frequency-dividing clocks, continuously will start NANDflash data high-speeds are cached in BRAM.
- A kind of 5. NANDFlash to FPGA internal blocks RAM according to claim 3 caching method, it is characterised in that institute That states is continuously cached to NANDflash data in BRAM, under the driving of frequency-dividing clock Clk_4S [0], reads NANDflash Data, under Clk_4S [1] clock, save the data in data buffer, under frequency-dividing clock Clk_4S [2], will lock Data in storage are written in BRAM, then add 1 automatically along lower counter in frequency-dividing clock Clk_4S [3], address accumulator Automatic to add 1, then dock cycles, realize that continuous clock caches, and when data counter reaches number of targets, data buffer storage stops.
- 6. a kind of NANDFlash to FPGA internal blocks RAM according to claim 1 caching method, it is characterised in that read BRAM controllers are taken, by MCU and FPGA address bus and data/address bus, the BRAM addresses of target are written to address latch In, the trigger controller under MCU instruction, the continuous reading instruction set of DMA, start four frequency-dividing clocks, start continuous high speed and read BRAM data.
- A kind of 7. NANDFlash to FPGA internal blocks RAM according to claim 6 caching method, it is characterised in that institute The continuous high speed stated reads BRAM data, under the driving of frequency-dividing clock Clk_4S [0], BRAM data is read, in Clk_4S [1] it is cached under driving in data latches, under Clk_4S [3] clock, BRAM adds up address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710900372.3A CN107729269A (en) | 2017-09-28 | 2017-09-28 | A kind of NANDFlash to FPGA internal blocks RAM caching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710900372.3A CN107729269A (en) | 2017-09-28 | 2017-09-28 | A kind of NANDFlash to FPGA internal blocks RAM caching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107729269A true CN107729269A (en) | 2018-02-23 |
Family
ID=61208650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710900372.3A Pending CN107729269A (en) | 2017-09-28 | 2017-09-28 | A kind of NANDFlash to FPGA internal blocks RAM caching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107729269A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111488297A (en) * | 2020-04-02 | 2020-08-04 | 杭州迪普科技股份有限公司 | Method, device, electronic equipment and readable medium for accessing register |
| CN112765054A (en) * | 2019-11-01 | 2021-05-07 | 中国科学院声学研究所 | High-speed data acquisition system and method based on FPGA |
| CN117277998A (en) * | 2023-11-23 | 2023-12-22 | 西安智多晶微电子有限公司 | Frequency division signal adjusting circuit applied to FPGA |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103885909A (en) * | 2014-03-26 | 2014-06-25 | 国电南瑞科技股份有限公司 | SSD controller based on native PCIe interface and control method thereof |
| CN104021086A (en) * | 2014-05-26 | 2014-09-03 | 西安交通大学 | Implementation method for reading and writing 16-bit memory cell RAM through eight-bit single-chip microcomputer |
| CN105138470A (en) * | 2015-08-31 | 2015-12-09 | 浪潮集团有限公司 | Multi-channel nand flash controller |
| CN105955919A (en) * | 2016-04-27 | 2016-09-21 | 西安交通大学 | Implementation method of reading-writing NANDFlash by multiple MCUs based on FPGA (Field Programmable Gate Array) |
-
2017
- 2017-09-28 CN CN201710900372.3A patent/CN107729269A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103885909A (en) * | 2014-03-26 | 2014-06-25 | 国电南瑞科技股份有限公司 | SSD controller based on native PCIe interface and control method thereof |
| CN104021086A (en) * | 2014-05-26 | 2014-09-03 | 西安交通大学 | Implementation method for reading and writing 16-bit memory cell RAM through eight-bit single-chip microcomputer |
| CN105138470A (en) * | 2015-08-31 | 2015-12-09 | 浪潮集团有限公司 | Multi-channel nand flash controller |
| CN105955919A (en) * | 2016-04-27 | 2016-09-21 | 西安交通大学 | Implementation method of reading-writing NANDFlash by multiple MCUs based on FPGA (Field Programmable Gate Array) |
Non-Patent Citations (1)
| Title |
|---|
| 彭卓文等: "《基于FPGA控制的高速大容量NAND FLASH存储模块设计》", 《电子设计工程》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112765054A (en) * | 2019-11-01 | 2021-05-07 | 中国科学院声学研究所 | High-speed data acquisition system and method based on FPGA |
| CN111488297A (en) * | 2020-04-02 | 2020-08-04 | 杭州迪普科技股份有限公司 | Method, device, electronic equipment and readable medium for accessing register |
| CN117277998A (en) * | 2023-11-23 | 2023-12-22 | 西安智多晶微电子有限公司 | Frequency division signal adjusting circuit applied to FPGA |
| CN117277998B (en) * | 2023-11-23 | 2024-03-19 | 西安智多晶微电子有限公司 | Frequency division signal adjusting circuit applied to FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4158227A (en) | Paged memory mapping with elimination of recurrent decoding | |
| CN102087606B (en) | FPGA configuration file update device | |
| CN105786411B (en) | Method of operating a non-volatile memory device | |
| US20140181365A1 (en) | Techniques to Configure a Solid State Drive to Operate in a Storage Mode or a Memory Mode | |
| CN108958638A (en) | Ultrahigh speed SAR data recorder and data record method | |
| CN101354906B (en) | Flash memory controller for solid hard disk | |
| CN107729269A (en) | A kind of NANDFlash to FPGA internal blocks RAM caching method | |
| CN102999453B (en) | For the general non-volatile memory control device that System on Chip/SoC is integrated | |
| CN105027213A (en) | Programmable address mapping and memory access operations | |
| US20220206780A1 (en) | Online upgrading method and system for multi-core embedded system | |
| US10452598B2 (en) | Apparatuses and methods for an operating system cache in a solid state device | |
| CN102541510B (en) | Instruction cache system and its instruction acquiring method | |
| CN106802870A (en) | A kind of efficient embedded system chip Nor Flash controllers and control method | |
| CN205608814U (en) | Augmented reality system based on zynq software and hardware concurrent processing | |
| CN101944011B (en) | The device of working procedure, chip and method | |
| CN104615386A (en) | Off-core cache device | |
| CN115080471A (en) | Nand flash interface controller based on FPGA and read-write method | |
| CN100499557C (en) | Addressing control device and addressing method using same | |
| TW201437812A (en) | Methods for accessing memory and controlling access of memory, memory device and memory controller | |
| CN102789424B (en) | External extended DDR2 (Double Data Rate 2) read-write method on basis of FPGA (Field Programmable Gate Array) and external extended DDR2 particle storage on basis of FPGA | |
| WO1995025307A1 (en) | Methods and apparatus for increased efficiency bus transactions | |
| CN102200952A (en) | Extensible hierarchical embedded CPU memory system | |
| CN111221754A (en) | Storage device with read-write collision prevention function | |
| CN101876952B (en) | System and method for realizing software-hardware interaction between transmission layer and application layer of host | |
| CN102646071A (en) | Device and method for executing cache write hit operation in single cycle |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180223 |