CN102200952A - Extensible hierarchical embedded CPU memory system - Google Patents
Extensible hierarchical embedded CPU memory system Download PDFInfo
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Abstract
The invention relates to an extensible hierarchical embedded CPU memory system. The system comprises an embedded CPU memory, a system bus main-equipment interface, a system bus slave-equipment interface and a memory resource access arbitrator, wherein the memory resource access arbitrator is connected with a processor through an internal bus; the memory resource access arbitrator is connected with the system bus main-equipment interface simultaneously through an instruction bus and a data bus; the memory resource access arbitrator is also connected with the system bus slave-equipment interface; and through distinguishing an access address on the instruction bus and the data bus, the memory resource access arbitrator sends an access request onto an instruction on-chip memory, a data on-chip memory, an instruction off-chip memory interface, a data off-chip memory interface or the system bus main-equipment interface. In the invention, the embedded CPU memory system can be configured flexibly for meeting multiple application requirements, and the performance of the embedded CPU is improved.
Description
Technical field
The present invention relates to the flush bonding processor field, especially a kind of embedded type CPU accumulator system.
Background technology
The reservoir system is that the core of Computer Architecture one of is formed, and particularly for embedded type CPU, the storage loading procedure of instruction and data has become one of bottleneck of embedded type CPU performance boost.Nearly 30 years data show, are example with the DRAM of 64KB, and the performance of storer aspect time delay increases to average annual 7%, and the average annual growth of memory performance is about 41%.Promote memory performance and obviously be difficult to satisfy the performance of processors requirement from reducing storer time delay angle merely.Therefore, current international mainstream technology has all adopted the memory hierarchy design.
Typical accumulator system comprises following four levels: internally cached (the Cache) → primary memory of register (Register) → sheet (Memory) → supplementary storage (Disk).Memory device speed is fast more more closely with the CPU coupling, but every bit storage cost is high more, and capacity is more little; Slow more with the memory device speed that the CPU distance is far away more, but every bit storage cost is low more, and capacity is big more.The purpose of accumulator system stratification promptly is to make up the storage system that an access speed approaches the fastest level storer with lower cost.
Existing embedded type CPU accumulator system generally comprises the memory resource of two levels, i.e. sheet internally cached (Cache) and system bus host device interface.The defective of this technology is, sheet is internally cached except storage data (Data), also must store to be used to judge the internally cached zone bit that hits of sheet (Tag), so its area and cost is bigger; And instruction or data access that at every turn can be high slow, all need to open simultaneously all data roads and sign road, cause power consumption higher, access time delay is also bigger simultaneously.So internally cached embedded system that is not suitable for super low-power consumption, Ultra Low Cost of sheet.
In addition, also have some embedded type CPU accumulator systems to use tight coupling storer (TCM) in the sheet, but the defective of existing TCM technology is that the base address and the scope of tight coupling storer are fixed in the sheet, can not be according to system's needs flexible configuration.
Summary of the invention
Existing embedded type CPU accumulator system area is big in order to overcome, cost and power consumption height, can not flexible configuration, the defective of the application of incompatibility super low-power consumption, Ultra Low Cost the invention provides and realize under a kind of low cost that flexible configuration, power consumption are lower, promotes the extendible stratification embedded type CPU accumulator system of the performance of embedded type CPU.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of extendible stratification embedded type CPU accumulator system, comprise embedded type CPU storer, system bus host device interface and system bus slave unit interface, described embedded type CPU storer comprises instruction on-chip memory, instruction chip external memory, data slice internal storage and data slice external storage; Described system bus host device interface is connected with system bus with system bus slave unit interface;
Described instruction bus is connected with described instruction on-chip memory, instruction chip external memory interface, described instruction chip external memory interface is connected with described instruction chip external memory, the outer slave unit interface of described instruction chip external memory and instruction sheet connects, and the outer slave unit interface of described instruction sheet is connected with described system bus;
Described data bus is connected with described data slice internal storage, data slice external memory interface, described data slice external memory interface is connected with described data slice external storage, described data slice external storage is connected with the outer slave unit interface of data slice, and the outer slave unit interface of described data slice is connected with described system bus;
Described embedded type CPU accumulator system also comprises memory resource access arbitration device, described memory resource access arbitration device is connected with processor by internal bus, described memory resource access arbitration device is connected with the system bus host device interface with data bus by instruction bus simultaneously, and described memory resource access arbitration device also is connected with described system bus slave unit interface;
Described memory resource access arbitration device sends to request of access on instruction on-chip memory, data slice internal storage, instruction chip external memory interface, data slice external memory interface or the system bus host device interface by the reference address on instruction bus and the data bus is differentiated.
Further, in the described embedded type CPU accumulator system, be divided into three level memory resources successively from high to low with access privileges, wherein, ground floor external memory resource is instruction on-chip memory and data slice internal storage, second layer external memory resource is instruction chip external memory and data slice external storage, and the tri-layer memory resource is the system bus host device interface.Certainly, also can select other layered mode.
Further again, described ground floor external memory resource, second layer external memory resource are configurable resource, and the tri-layer memory resource is not configurable VS .NET Prerequisites resource.
Described instruction on-chip memory all is connected with described system bus slave unit interface with the data slice internal storage, be provided with instruction on-chip memory base address and range registers in the system bus slave unit interface, data slice internal storage base address and range registers, these two registers are dynamically configurable, memory resource access arbitration device and instruction on-chip memory base address and range registers, data slice internal storage base address links to each other with range registers, memory resource access arbitration device judges according to the base address and the scope of instruction on-chip memory base address and range registers whether bus request drops on the instruction on-chip memory, and judges according to the base address and the scope of data slice internal storage base address and range registers whether bus request drops on the data slice internal storage.
The outer slave unit interface of described instruction chip external memory interface and instruction sheet links to each other, compare mask and instruction chip external memory enable bit by instruction chip external memory interface to memory resource access arbitration device input instruction chip external memory base address, address, memory resource access arbitration device judges according to instruction chip external memory interface input information whether bus request drops on the instruction chip external memory interface, and instruction chip external memory base address, address compare mask and instruction chip external memory enable bit is produced by user flexibility;
Described data slice external memory interface links to each other with the outer slave unit interface of data slice, compare mask and data slice external storage enable bit by the data slice external memory interface to memory resource access arbitration device input data slice external storage base address, address, memory resource access arbitration device judges according to data slice external memory interface input information whether bus request drops on the data slice external memory interface, and data slice external storage base address, address compare mask and data slice external storage enable bit is produced by user flexibility.
In the described memory resource access arbitration device, do not fall into the request of access of data slice internal storage, instruction on-chip memory, data slice external memory interface and instruction chip external memory interface for those, its visit is all by the visit of system bus host device interface realization to system bus.
Technical conceive of the present invention is: in the embedded type CPU accumulator system, introduce memory resource access arbitration device and judge request of access, the different access request is accurately sent on the respective memory resource; Introduction system bus slave interface, design instruction on-chip memory base address and range registers are used to realize to instruct the flexible configuration of on-chip memory base address and scope, and design data on-chip memory base address and range registers are used to realize the flexible configuration of data slice internal storage base address and scope; Introduce instruction chip external memory interface, realize the flexible expansion of instruction chip external memory; Introduce the data slice external memory interface, realize the flexible expansion of data slice external storage.
Beneficial effect of the present invention mainly shows: the low-cost performance that realizes that down accumulator system flexible configuration, power consumption are lower, promotes embedded type CPU.
Description of drawings
Fig. 1 is the stratification embedded type CPU accumulator system schematic representation of apparatus of the easy expansion that proposes of the present invention.
Fig. 2 is the bus network schematic representation of apparatus of memory resource access arbitration device.
Fig. 3 is the address comparator device of memory resource access arbitration device and the synoptic diagram of arbitration mechanism.
Fig. 4 is the synoptic diagram of the implement device of on-chip memory plot dynamic adjustable and capacity dynamic adjustable.
Fig. 5 is the synoptic diagram of the corresponding relation of on-chip memory capacity, on-chip memory plot and address mask in the specific embodiment.
Fig. 6 is a kind of synoptic diagram that is used for the User Defined storage arrangement of supporting pieces external storage base address dynamic adjustable.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 6, a kind of extendible stratification embedded type CPU accumulator system, comprise embedded type CPU storer, system bus host device interface and system bus slave unit interface, described embedded type CPU storer comprises instruction on-chip memory, instruction chip external memory, data slice internal storage and data slice external storage; Described system bus host device interface is connected with system bus with system bus slave unit interface;
Described instruction bus is connected with described instruction on-chip memory, instruction chip external memory interface, described instruction chip external memory interface is connected with described instruction chip external memory, the outer slave unit interface of described instruction chip external memory and instruction sheet connects, and the outer slave unit interface of described instruction sheet is connected with described system bus;
Described data bus is connected with described data slice internal storage, data slice external memory interface, described data slice external memory interface is connected with described data slice external storage, described data slice external storage is connected with the outer slave unit interface of data slice, and the outer slave unit interface of described data slice is connected with described system bus;
Described embedded type CPU accumulator system also comprises memory resource access arbitration device, described memory resource access arbitration device is connected with processor by internal bus, described memory resource access arbitration device is connected with the system bus host device interface with data bus by instruction bus simultaneously, and described memory resource access arbitration device also is connected with described system bus slave unit interface;
Described memory resource access arbitration device sends to request of access on instruction on-chip memory, data slice internal storage, instruction chip external memory interface, data slice external memory interface or the system bus host device interface by the reference address on instruction bus and the data bus is differentiated.
In the described embedded type CPU accumulator system, be divided into three level memory resources successively from high to low with access privileges, wherein, ground floor external memory resource is instruction on-chip memory and data slice internal storage, second layer external memory resource is instruction chip external memory and data slice external storage, and the tri-layer memory resource is the system bus host device interface.Certainly, also can select other layered mode.
Described ground floor external memory resource, second layer external memory resource are configurable resource, and the tri-layer memory resource is not configurable VS .NET Prerequisites resource.
Described instruction on-chip memory all is connected with described system bus slave unit interface with the data slice internal storage, be provided with instruction on-chip memory base address and range registers in the system bus slave unit interface, data slice internal storage base address and range registers, these two registers are dynamically configurable, memory resource access arbitration device and instruction on-chip memory base address and range registers, data slice internal storage base address links to each other with range registers, memory resource access arbitration device judges according to the base address and the scope of instruction on-chip memory base address and range registers whether bus request drops on the instruction on-chip memory, and judges according to the base address and the scope of data slice internal storage base address and range registers whether bus request drops on the data slice internal storage.
The outer slave unit interface of described instruction chip external memory interface and instruction sheet links to each other, compare mask and instruction chip external memory enable bit by instruction chip external memory interface to memory resource access arbitration device input instruction chip external memory base address, address, memory resource access arbitration device judges according to instruction chip external memory interface input information whether bus request drops on the instruction chip external memory interface, and instruction chip external memory base address, address compare mask and instruction chip external memory enable bit is produced by user flexibility;
Described data slice external memory interface links to each other with the outer slave unit interface of data slice, compare mask and data slice external storage enable bit by the data slice external memory interface to memory resource access arbitration device input data slice external storage base address, address, memory resource access arbitration device judges according to data slice external memory interface input information whether bus request drops on the data slice external memory interface, and data slice external storage base address, address compare mask and data slice external storage enable bit is produced by user flexibility.
In the described memory resource access arbitration device, do not fall into the request of access of data slice internal storage, instruction on-chip memory, data slice external memory interface and instruction chip external memory interface for those, its visit is all by the visit of system bus host device interface realization to system bus.
Fig. 1 shows a specific embodiment of the extendible stratification embedded type CPU accumulator system device of the present invention's proposition.This embedded type CPU accumulator system 117 comprises following composition:
The independently instruction bus 13 of the connection total system shown in Fig. 1 and data bus 14.That transmits instruction on the instruction bus 13 gets finger request, address, instruction length information, order code and region of memory protection relevant information.Request, address, read-write sign, the data of writing out and the length information thereof of Data transmission visit on the data bus 14, data of reading in and significance bit sign thereof, and region of memory protection relevant information.
The memory resource access arbitration device 12 of the whole accumulator system device control of the conduct shown in Fig. 1 core.Moderator 12 carries out two-way communication by internal bus 1 (118) and internal bus 2 (119) with processor core.Moderator is accepted request of access and the reference address on internal bus 1 and the internal bus 2, by the address relatively, sends request of access to the corresponding memory resource.Internal bus 1 and internal bus 2 are communication interfaces of processor core and accumulator system, and its realization can have various protocols.Wherein a kind of organizational principle according to Harvard structure, instruction bus and data bus are separated, and then internal bus 1 may be instantiated as instruction bus, and internal bus 2 may be instantiated as data bus.
The on- chip memory 15,16 and the system bus slave unit interface 17 thereof of this accumulator system equipment that is positioned at first level shown in Fig. 1.On- chip memory 15,16 can be realized the monocycle visit of instruction and data.Similarly, in one embodiment, can be according to the organizational principle of Harvard structure, on-chip memory can be divided into instruction on-chip memory 15 and data slice internal storage 16, wherein instruct 15 of on-chip memories to be connected on the instruction bus 13,16 in data slice internal storage is connected on the data bus 14.System bus slave unit interface 17 is responsible for the read-write requests of receiving system DMA, writes or sense order and data to on-chip memory 15,16.System bus slave unit interface 17 is responsible for realizing the dynamic adjustable of on-chip memory base address simultaneously.
The chip external memory interface 18,19 of this accumulator system equipment that is positioned at second level shown in Fig. 1.The chip external memory interface provides a kind of selection of autonomous extended memory for the user.User-defined outer expansion storer 110,111 is positioned at the system clock territory, by the conversion between chip external memory interface 18,19 responsible processor clock territories and the system clock territory.The storer that the outer slave unit interface 112,113 of sheet is responsible for expansion outside sheet writes or sense order and data, realizes the dynamic adjustable of chip external memory base address simultaneously.Similarly, in one embodiment, also can chip external memory be divided into instruction chip external memory 110 and data slice external storage 111 according to the organizational principle of Harvard structure.
The system bus host device interface 114 that is positioned at this accumulator system equipment tri-layer shown in Fig. 1.After the moderator arbitration, if the request of instruction or data is not all hit on on-chip memory and chip external memory interface, then moderator is initiated request by system bus host device interface 114 to system bus with this request, reads and writes data from Installed System Memory.
The memory resource access privileges of three levels shown in Fig. 1 order successively from high to low, access speed is successively near slowly.The access privileges of on- chip memory 15,16 is higher than chip external memory interface 18,19, and the access privileges of chip external memory interface 18,19 is higher than system bus host device interface 114; The access speed of on- chip memory 15,16 is faster than chip external memory interface 18,19, and the access speed of chip external memory interface 18,19 is faster than system bus host device interface 114.
The memory devices resource of first, second level shown in Fig. 1 is a configurable resource, can carry out flexible configuration according to the actual demand of using; Tri-layer memory devices resource is the VS .NET Prerequisites resource, and is not configurable.The instruction chip external memory interface 18, the data slice external memory interface 19 that are positioned at instruction on-chip memory 15, the data slice internal storage 16 of first level and are positioned at second level are configurable resource, and the system bus host device interface that is positioned at tri-layer is the VS .NET Prerequisites resource.
Fig. 2 shows the bus network that the present invention proposes, and is used for connection processing device core and accumulator system.In processor core one side, processor core is connected on the bus network by n bar internal bus (21,22).In accumulator system one side,, select corresponding internal bus 1 (21) or internal bus 2 (22) to be connected on instruction bus (23) and the data bus (24) by the data selector of memory resource access arbitration device control.
As shown in Figure 2, in a kind of typical embodiment, the internal bus of processor is counted n=2, and promptly processor core is connected on the bus network by two internal buss, and wherein one is internal instruction bus, and another is an internal data bus.For the Harvard structure processor of strictness, bus network is with unique being connected on the accumulator system instruction bus (23) of internal instruction bus (21), with unique being connected on the accumulator system data bus (24) of internal data bus (22).Like this, get the instruction area that the finger process can only the access system internal memory, and the data field that the reading and writing data process can only the access system internal memory.
As shown in Figure 2, in the special embodiment of another kind, the flush bonding processor instruction set comprises the instruction of programmable counter (PC) relative addressing usually, is used for loading counting (for example loading one 32 data) on a large scale immediately.The essence of this class instruction is to leave counting immediately of need loading in instruction area on a large scale, by the mode of PC-relative addressing, reads corresponding data from the instruction area.This class processor architecture belongs to the Harvard structure of non-strictness, for the type processor, internal instruction bus (21) and internal data bus (22) all need be connected on the accumulator system instruction bus (23), and select corresponding access originator by a data selector switch.
Show the address comparator device and the arbitration mechanism of the memory resource access arbitration device of the present invention's proposition as Fig. 3.17 designs of system bus slave unit interface have instruction on-chip memory base address and range registers 32 and data slice internal storage base address and range registers 33.The on-chip memory volume controlled position of instruction on-chip memory base address and range registers 32, the address mask that is used to produce instruction access; The on-chip memory volume controlled position of data slice internal storage base address and range registers 33, the address mask that is used to produce data access.The current storage reference address carries out " step-by-step with " operation through one with door 34 and address mask, sends into address comparator 35 then and compares with the on-chip memory base address.If comparative result equates, and the on-chip memory enable bit is effective, represent that then current accessed hits on on-chip memory, moderator can send to this request of access on the on-chip memory with relevant visit information; If comparative result is unequal, then represent current accessed not in on-chip memory, moderator can send to this request of access and relevant visit information on other corresponding memory resources; If the on-chip memory enable bit is invalid, represent that then current on-chip memory is unavailable, moderator can send to this request of access on other corresponding memory resources.
Show the implement device of on-chip memory base address dynamic adjustable and capacity dynamic adjustable as Fig. 4.Processor is by system bus, and instruction on-chip memory base address on system bus slave unit interface 17 and range registers write instruction on-chip memory base address, instruction on-chip memory capacity and instruction on-chip memory enable bit; Data slice internal storage base address on system bus slave unit interface 17 and range registers write data slice internal storage base address, data slice internal storage capacity and data slice internal storage enable bit.
Implement device as shown in Figure 4, in a specific embodiment, on-chip memory base address 43, on-chip memory volume controlled position 44, on-chip memory enable bit 45 can be positioned on the not coordination of same on-chip memory base address and range registers,, write in the lump according to specific form by software by system bus slave unit interface.。In another embodiment, on-chip memory base address 43, on-chip memory volume controlled position 44, on-chip memory enable bit 45 be special register of correspondence separately, each register is read and write respectively by system bus slave unit interface by software.
Implement device as shown in Figure 4 can be realized the reorientation of on-chip memories by the on-chip memory base address section 43 that modification is positioned at on-chip memory base address on the system bus slave unit interface 17 and range registers; Can realize the dynamic-configuration of on-chip memory amount of capacity by the on-chip memory volume controlled position 44 that modification is positioned at on-chip memory base address on the system bus slave unit interface 17 and range registers.On-chip memory volume controlled position capacity corresponding size should be less than or equal to actual on-chip memory size.
Implement device as shown in Figure 4 uses the data selector 46 of on-chip memory volume controlled position 44 controls to produce address mask, and the part address comparison screen that is used for memory resource access arbitration device address comparator is covered.
Show the corresponding relation of on-chip memory capacity, on-chip memory base address and address mask in the specific embodiment as Fig. 5.In this specific embodiment, realized the dynamic adjustable of on-chip memory capacity 1KB, 2KB, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, then the width range of on-chip memory plot is that 22 bits are to 13 bits, accordingly, the address mask that need the to produce 9 bit widths part address comparison screen that is used for memory resource access arbitration device is covered.
Show a kind of User Defined memory expansion device that is used for supporting pieces external storage base address dynamic adjustable as Fig. 6.Chip external memory is positioned at the system clock territory, so chip external memory interface 61 comprises two clock zones in system clock territory and processor clock territory.Signal transmission between two clock zones needs special steering logic to guarantee the correct sampling of signal.
A kind of User Defined storage arrangement that is used for supporting pieces external storage base address dynamic adjustable as shown in Figure 6 comprises 5 logical paths:
● the control path from the processor clock territory to the system clock territory (62), transmit the chip external memory request of access.
● the data path from the processor clock territory to the system clock territory (63), transmit chip external memory reference address, reading and writing data information, data size information and store the target data of chip external memory into.
● the control path from the system clock territory to the processor clock zone (64), transmit the chip external memory transmission and finish signal.
● the data path from the system clock territory to the processor clock zone (65), the data that transmission is read in from chip external memory, the validity information and the access errors information of data.
● the chip external memory expansion path (66) from the system clock territory to the processor clock zone, transmit chip external memory plot, address mask and chip external memory enable bit signal.
Preceding four logical paths the 62,63,64, the 65th in the dynamic adjustable memory expansion device of a kind of chip external memory as shown in Figure 6 base address, the data access path of chip external memory, the 5th path 66 is chip external memory configuration paths.
Chip external memory configuration path 66 in a kind of memory expansion device as shown in Figure 6 is used to realize chip external memory base address dynamic adjustable and capacity dynamic adjustable, and it realizes that principle is identical with on-chip memory.Chip external memory base address, address comparison mask and chip external memory enable bit are produced by user flexibility, and the accumulator system device that the present invention proposes is not done any restriction to the producing method of chip external memory plot, address comparison mask and chip external memory enable bit.Address relatively mask is used for that address signal in moderator and current accessed request carries out entering the moderator address comparator after " step-by-step with " computing and the chip external memory base address compares.If the address comparator comparative result equates, and the chip external memory enable bit is effective, represent that then current accessed hits on chip external memory, moderator can send to this request of access on the chip external memory interface; If comparative result is unequal, then represent current accessed not on chip external memory, moderator can send to this request of access on other corresponding memory resources; If the chip external memory enable bit is invalid, represent that then current chip external memory is unavailable, moderator can send to this request of access on other corresponding memory resources.
Claims (6)
1. extendible stratification embedded type CPU accumulator system, it is characterized in that: comprise embedded type CPU storer, system bus host device interface and system bus slave unit interface, described embedded type CPU storer comprises instruction on-chip memory, instruction chip external memory, data slice internal storage and data slice external storage; Described system bus host device interface is connected with system bus with system bus slave unit interface;
Described instruction bus is connected with described instruction on-chip memory, instruction chip external memory interface, described instruction chip external memory interface is connected with described instruction chip external memory, the outer slave unit interface of described instruction chip external memory and instruction sheet connects, and the outer slave unit interface of described instruction sheet is connected with described system bus;
Described data bus is connected with described data slice internal storage, data slice external memory interface, described data slice external memory interface is connected with described data slice external storage, described data slice external storage is connected with the outer slave unit interface of data slice, and the outer slave unit interface of described data slice is connected with described system bus; It is characterized in that:
Described embedded type CPU accumulator system also comprises memory resource access arbitration device, described memory resource access arbitration device is connected with processor by internal bus, described memory resource access arbitration device is connected with the system bus host device interface with data bus by instruction bus simultaneously, and described memory resource access arbitration device also is connected with described system bus slave unit interface;
Described memory resource access arbitration device sends to request of access on instruction on-chip memory, data slice internal storage, instruction chip external memory interface, data slice external memory interface or the system bus host device interface by the reference address on instruction bus and the data bus is differentiated.
2. extendible stratification embedded type CPU accumulator system as claimed in claim 1, it is characterized in that: in the described embedded type CPU accumulator system, be divided into three level memory resources successively from high to low with access privileges, wherein, ground floor external memory resource is instruction on-chip memory and data slice internal storage, second layer external memory resource is instruction chip external memory and data slice external storage, and the tri-layer memory resource is the system bus host device interface.
3. extendible stratification embedded type CPU accumulator system as claimed in claim 2, it is characterized in that: described ground floor external memory resource, second layer external memory resource are configurable resource, and the tri-layer memory resource is not configurable VS .NET Prerequisites resource.
4. as the described extendible stratification embedded type CPU accumulator system of one of claim 1～3, it is characterized in that: described instruction on-chip memory all is connected with described system bus slave unit interface with the data slice internal storage, be provided with instruction on-chip memory base address and range registers in the system bus slave unit interface, data slice internal storage base address and range registers, these two registers are dynamically configurable, memory resource access arbitration device and instruction on-chip memory base address and range registers, data slice internal storage base address links to each other with range registers, memory resource access arbitration device judges according to the base address and the scope of instruction on-chip memory base address and range registers whether bus request drops on the instruction on-chip memory, and judges according to the base address and the scope of data slice internal storage base address and range registers whether bus request drops on the data slice internal storage.
5. as the described extendible stratification embedded type CPU accumulator system of one of claim 1～3, it is characterized in that: the outer slave unit interface of described instruction chip external memory interface and instruction sheet links to each other, by instructing the chip external memory interface to memory resource access arbitration device input instruction chip external memory base address, the address is mask and instruction chip external memory enable bit relatively, memory resource access arbitration device judges according to instruction chip external memory interface input information whether bus request drops on the instruction chip external memory interface instruction chip external memory base address, address relatively mask is produced by user flexibility with instruction chip external memory enable bit;
Described data slice external memory interface links to each other with the outer slave unit interface of data slice, compare mask and data slice external storage enable bit by the data slice external memory interface to memory resource access arbitration device input data slice external storage base address, address, memory resource access arbitration device judges according to data slice external memory interface input information whether bus request drops on the data slice external memory interface, and data slice external storage base address, address compare mask and data slice external storage enable bit is produced by user flexibility.
6. as the described extendible stratification embedded type CPU accumulator system of one of claim 1～3, it is characterized in that: in the described memory resource access arbitration device, do not fall into the request of access of data slice internal storage, instruction on-chip memory, data slice external memory interface and instruction chip external memory interface for those, its visit is all by the visit of system bus host device interface realization to system bus.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103180817A (en) * | 2012-07-02 | 2013-06-26 | 杭州华为数字技术有限公司 | Storage expansion apparatus and server |
| CN108062486A (en) * | 2017-12-15 | 2018-05-22 | 杭州中天微系统有限公司 | A kind of storage protection device for dereference storage control |
| CN108197503A (en) * | 2017-12-15 | 2018-06-22 | 杭州中天微系统有限公司 | A kind of device for increasing defencive function for dereference storage control |
| CN110210232A (en) * | 2019-06-06 | 2019-09-06 | 成都海光集成电路设计有限公司 | Date storage method and device |
| CN112134814A (en) * | 2020-08-24 | 2020-12-25 | 合肥学院 | Board-level internet structure and communication method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4737932A (en) * | 1984-06-05 | 1988-04-12 | Nec Corporation | Processor |
| CN101692212A (en) * | 2009-06-19 | 2010-04-07 | 北京中星微电子有限公司 | Method and system for accessing memory and bus arbitration device |
| CN101894281A (en) * | 2010-06-18 | 2010-11-24 | 山东大学 | Baseband signal processing SOC chip of multi-protocol UHF RFID reader |
-
2011
- 2011-03-28 CN CN2011100755347A patent/CN102200952A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4737932A (en) * | 1984-06-05 | 1988-04-12 | Nec Corporation | Processor |
| CN101692212A (en) * | 2009-06-19 | 2010-04-07 | 北京中星微电子有限公司 | Method and system for accessing memory and bus arbitration device |
| CN101894281A (en) * | 2010-06-18 | 2010-11-24 | 山东大学 | Baseband signal processing SOC chip of multi-protocol UHF RFID reader |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103180817A (en) * | 2012-07-02 | 2013-06-26 | 杭州华为数字技术有限公司 | Storage expansion apparatus and server |
| WO2014005261A1 (en) * | 2012-07-02 | 2014-01-09 | 杭州华为数字技术有限公司 | Storage expansion device and server |
| US9053252B2 (en) | 2012-07-02 | 2015-06-09 | Huawei Technologies Co., Ltd. | Storage expansion apparatus and server |
| CN103180817B (en) * | 2012-07-02 | 2015-09-30 | 杭州华为数字技术有限公司 | Memory expansion unit and server |
| CN108062486B (en) * | 2017-12-15 | 2020-09-15 | 杭州中天微系统有限公司 | Storage protection device for indirect access storage controller |
| CN108197503A (en) * | 2017-12-15 | 2018-06-22 | 杭州中天微系统有限公司 | A kind of device for increasing defencive function for dereference storage control |
| WO2019114477A1 (en) * | 2017-12-15 | 2019-06-20 | C-Sky Microsystems Co., Ltd. | Apparatus for adding protection function for indirect access memory controller |
| CN108062486A (en) * | 2017-12-15 | 2018-05-22 | 杭州中天微系统有限公司 | A kind of storage protection device for dereference storage control |
| CN108197503B (en) * | 2017-12-15 | 2020-09-15 | 杭州中天微系统有限公司 | Device for adding protection function to indirect access storage controller |
| US11216192B2 (en) | 2017-12-15 | 2022-01-04 | C-Sky Microsystems Co., Ltd. | Memory protective apparatus for indirect access memory controller |
| US11256830B2 (en) | 2017-12-15 | 2022-02-22 | C-Sky Microsystems Co., Ltd. | Apparatus for adding protection function for indirect access memory controller |
| US11726675B2 (en) | 2017-12-15 | 2023-08-15 | C-Sky Microsystems Co., Ltd. | Memory protective apparatus for indirect access memory controller |
| CN110210232A (en) * | 2019-06-06 | 2019-09-06 | 成都海光集成电路设计有限公司 | Date storage method and device |
| CN110210232B (en) * | 2019-06-06 | 2022-05-24 | 成都海光集成电路设计有限公司 | Data storage method and device |
| CN112134814A (en) * | 2020-08-24 | 2020-12-25 | 合肥学院 | Board-level internet structure and communication method |
| CN112134814B (en) * | 2020-08-24 | 2022-04-12 | 合肥学院 | Board-level internet structure and communication method |
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