CN110210232A - Date storage method and device - Google Patents
Date storage method and device Download PDFInfo
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- CN110210232A CN110210232A CN201910493296.8A CN201910493296A CN110210232A CN 110210232 A CN110210232 A CN 110210232A CN 201910493296 A CN201910493296 A CN 201910493296A CN 110210232 A CN110210232 A CN 110210232A
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- memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
- H04L63/1441—Countermeasures against malicious traffic
Abstract
The present invention provides a kind of date storage method and devices, can prevent the side-channel attack based on shared buffer memory.The method, comprising: obtain the data of memory to be stored, and judge in the memory with the presence or absence of preset first memory；And if there are first memories in the memory, the data of first memory described in the memory are stored into the corresponding privately owned caching of the first memory described in the memory, and by the storage of the data of the memory in the memory in addition to first memory into the corresponding privately owned caching of the memory in addition to first memory and shared buffer memory.
Description
Technical field
The present invention relates to computer security technical fields, in particular to a kind of date storage method and device.
Background technique
In recent years, side Channel Technology gradually from device external be deep into the CPU of computer-internal, cache,
The sensitive information (such as key) that inch prediction unit etc. is wherein contained.Caching attack is a kind of novel side Multiple Channel Analysis
Technology, it can it is cross-platform, across CPU, break through security boundary target device is attacked, existing security protection is caused greatly
Threat.In addition, having due to can use the shared implementation attack of caching for the side-channel attack of caching and being not easy to find
And the characteristics of extremely difficult defence.
In view of this, how to provide a kind of method for preventing the side-channel attack based on shared buffer memory, become urgently to be resolved
The technical issues of.
Summary of the invention
In view of this, can prevent the purpose of the present invention is to provide a kind of date storage method and device based on shared slow
The side-channel attack deposited.
In a first aspect, the embodiment of the invention provides a kind of date storage methods, comprising:
The data of memory to be stored are obtained, and are judged in the memory with the presence or absence of preset first memory；And
If there are first memories in the memory, the data of the first memory described in the memory are stored to described
In the corresponding privately owned caching of first memory described in memory, and by the data of the memory in the memory in addition to first memory
It stores in the corresponding privately owned caching of the memory in addition to first memory and shared buffer memory, wherein first memory
Without using shared buffer memory, the data sensitive to the side-channel attack based on shared buffer memory are stored in first memory.
Second aspect, the embodiment of the invention also provides a kind of data storage devices, comprising:
First judging unit for obtaining the data of memory to be stored, and judges in the memory with the presence or absence of default
The first memory；And
First writing unit, if determining in the memory for first judging unit there are first memory,
The data of first memory described in the memory are stored into the corresponding privately owned caching of the first memory described in the memory, and
The data storage of memory in the memory in addition to first memory is corresponding to the memory in addition to first memory
Privately owned caching and shared buffer memory in, wherein first memory does not use shared buffer memory, is stored in first memory pair
The data of side-channel attack sensitivity based on shared buffer memory.
This method and hardware are at least able to achieve following effect: the data of memory to be stored are obtained, if judging to know described
There are preset first memories in memory, then store the data of the first memory described in the memory to described in the memory
In the corresponding privately owned caching of first memory, and the data of the memory in the memory in addition to first memory are stored to described
In the corresponding privately owned caching of memory and shared buffer memory in addition to first memory, and since first memory is without using shared
It caches, is stored with the data sensitive to the side-channel attack based on shared buffer memory in first memory, this allows for this programme
When needing storing to the sensitive internal storage data of the side-channel attack based on shared buffer memory into caching, can store privately owned slow
In depositing, without storing into shared buffer memory, thus the side-channel attack based on shared buffer memory can be prevented, and this programme is not
The caching number that each code can be used is reduced, thus can guarantee the performance of the program for internal storage access sensitivity.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the application specific embodiment or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the application, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of one embodiment of date storage method of the present invention；
Fig. 2 is the part flow diagram of mono- embodiment of S10 in Fig. 1；
Fig. 3 is the schematic diagram that method shown in a typical computer chip application drawing 1 carries out internal storage access；
Fig. 4 is the structural schematic diagram of one embodiment of data storage device of the present invention；
Fig. 5 is the structural schematic diagram of another embodiment of data storage device of the present invention.
Specific embodiment
It is clearly and completely described below in conjunction with technical solution of the attached drawing to the application, it is clear that described implementation
Example is some embodiments of the present application, instead of all the embodiments.
The component of the embodiment of the present application for usually describing and showing in attached drawing here can be with a variety of different configurations
To arrange and design.Therefore, the detailed description of the embodiments herein provided in the accompanying drawings is not intended to limit below and is wanted
The scope of the present application of protection is sought, but is merely representative of the selected embodiment of the application.
Based on the embodiment in the application, those of ordinary skill in the art are obtained without making creative work
The every other embodiment obtained, shall fall in the protection scope of this application.
Referring to Fig. 1, the present invention discloses a kind of date storage method, comprising:
S10, the data for obtaining memory to be stored, and judge in the memory with the presence or absence of preset first memory；With
And
If there are first memories in S11, the memory, the data storage of the first memory described in the memory is arrived
In the corresponding privately owned caching of first memory described in the memory, and by the memory in the memory in addition to first memory
Data are stored into the corresponding privately owned caching of the memory in addition to first memory and shared buffer memory, wherein described first
Memory does not use shared buffer memory, is stored with the data sensitive to the side-channel attack based on shared buffer memory in first memory.
In the present embodiment, the executing subject of S10 and S11 are hardware.Every time when by internal storage data storage into caching, all
It needs to judge in memory with the presence or absence of the first memory, if it is present needing the first internal storage data storage in memory to the
In the privately owned caching of one memory, without storing into shared buffer memory.
It should be noted that can will be distributed the sensitive data of the side-channel attack based on shared buffer memory by operating system
It stores in first memory, and due to not reducing the caching number that can be used, so as to pass through soft or hard combination pair
The relatively high program of safety requirements provides and a kind of feasible prevent caching side-channel attack while not having too big shadow to performance
Loud scheme.
Date storage method provided in an embodiment of the present invention obtains the data of memory to be stored, if judging to know described
There are preset first memories in memory, then store the data of the first memory described in the memory to described in the memory
In the corresponding privately owned caching of first memory, and the data of the memory in the memory in addition to first memory are stored to described
In the corresponding privately owned caching of memory and shared buffer memory in addition to first memory, and since first memory is without using shared
It caches, is stored with the data sensitive to the side-channel attack based on shared buffer memory in first memory, this allows for this programme
When needing storing to the sensitive internal storage data of the side-channel attack based on shared buffer memory into caching, can store privately owned slow
In depositing, without storing into shared buffer memory, thus the side-channel attack based on shared buffer memory can be prevented, and this programme is not
The caching number that each code can be used is reduced, thus can guarantee the performance of the program for internal storage access sensitivity.
Fig. 2 is the part flow diagram of mono- embodiment of S10 in Fig. 1, referring to Fig. 2, on the basis of preceding method embodiment
On, it whether there is preset first memory in the judgement memory, may include:
S20, the initial address and zone length for obtaining first memory respectively from the first register and the second register；
If S21, judgement, which are known, has the ground in [initial address, termination address] range in the address of the memory
Location, it is determined that there are first memories in the memory, wherein the termination address is the initial address and zone length
Sum.
On the basis of preceding method embodiment, it whether there is preset first memory in the judgement memory, it can
To include:
Obtain the initial address and Mask data of first memory respectively from third register and the 4th register；
If the result for existing in the address of the memory and being carried out with the Mask data by bit and operation is known in judgement
Equal to the address of the initial address, it is determined that there are first memories in the memory.
In the present embodiment, by the address of memory and the Mask data carry out by bit and the result of operation whether etc.
Determine whether memory is first memory in the initial address, the hardware logic of such mode is compared to previous embodiment
Whether in [initial address, termination address] range determine whether memory is first memory by the address of memory
Hardware logic it is relatively simple.
On the basis of preceding method embodiment, the method can also include:
The data of the corresponding privately owned caching of the memory are obtained, and judge whether deposit in the corresponding memory of the privately owned caching
In first memory；
If interior saving as first memory for corresponding there are first memory in the corresponding memory of the privately owned caching
The data of privately owned caching be directly stored in corresponding memory.
In the present embodiment, every time when storing the data of privately owned caching into memory, require to judge to be stored interior
Whether be first memory, if the memory to be stored is the first memory, it is straight that the data of privately owned caching are skipped shared buffer memory if depositing
Storage is connect into the memory to be stored.And with the presence or absence of in preset first in the corresponding memory of the judgement privately owned caching
It deposits, may include: the initial address and zone length for obtaining first memory respectively from the first register and the second register；
Exist in [initial address, termination address] range if judgement is known in the address of the corresponding memory of the privately owned caching
Address, it is determined that there are first memories in the corresponding memory of the privately owned caching, wherein the termination address is described rises
Beginning address and zone length and.It is described to judge to whether there is preset first memory in the corresponding memory of the privately owned caching,
Also may include: from third register and the 4th register obtain respectively the corresponding memory of the privately owned caching initial address and
Mask data；It is carried out with the Mask data by bit if judgement is known to exist in the address of the corresponding memory of the privately owned caching
Address of the result of position and operation equal to the initial address, it is determined that there are described the in the corresponding memory of the privately owned caching
One memory.
It is illustrated in figure 3 the schematic diagram that method shown in a typical computer chip application drawing 1 carries out internal storage access, Fig. 3
In processor with four cores be a group, this four cores independently possess L1 caching and L2 caching, share L3 caching.
Before needing to cache access data from L3 every time, the memory management unit of processor requires to judge whether institute is belonged to using memory
First memory will cache without using L3 if belonging to the first memory and directly access main memory.
On the basis of preceding method embodiment, the sensitive data of the described pair of side-channel attack based on shared buffer memory can be with
It include: the local variable and code of program.
On the basis of preceding method embodiment, first memory may include what preset memory allocation function was distributed
Memory.
Referring to Fig. 4, the present invention discloses a kind of data storage device, comprising:
First judging unit 40 for obtaining the data of memory to be stored, and judges in the memory with the presence or absence of pre-
If the first memory；And
First writing unit 41, if determining that there are in described first in the memory for first judging unit
It deposits, by the data storage of the first memory described in the memory to the corresponding privately owned caching of the first memory described in the memory
In, and the data of the memory in the memory in addition to first memory are stored to the memory in addition to first memory
In corresponding privately owned caching and shared buffer memory, wherein first memory does not use shared buffer memory, stores in first memory
There are the data sensitive to the side-channel attack based on shared buffer memory.
In the present embodiment, data storage device is really hardware.Every time when by internal storage data storage into caching, all need
Judge with the presence or absence of the first memory in memory, if it is present needing the first internal storage data storage in memory to first
In the privately owned caching of memory, without storing into shared buffer memory.
It should be noted that can will be distributed the sensitive data of the side-channel attack based on shared buffer memory by operating system
It stores in first memory, and due to not reducing the caching number that can be used, so as to pass through soft or hard combination pair
The relatively high program of safety requirements provides and a kind of feasible prevent caching side-channel attack while not having too big shadow to performance
Loud scheme.
Data storage device provided in an embodiment of the present invention obtains memory to be stored by means of the first judging unit 40
Data, if judgement is known in the memory there are preset first memory, by means of the first writing unit 41 by the memory
Described in the data of the first memory store into the corresponding privately owned caching of the first memory described in the memory, and by the memory
In memory in addition to first memory data storage to the corresponding privately owned caching of the memory in addition to first memory
In shared buffer memory, and since first memory does not use shared buffer memory, it is stored in first memory to based on shared
The data of the side-channel attack sensitivity of caching, this allow for this programme need will be quick to the side-channel attack based on shared buffer memory
It when the internal storage data of sense is stored into caching, can store in privately owned caching, without storing into shared buffer memory, thus can prevent
Only based on the side-channel attack of shared buffer memory, and this programme does not reduce the caching number that each code can be used, thus
It can guarantee the performance of the program for internal storage access sensitivity.
Fig. 5 is the structural schematic diagram of another embodiment of data storage device of the present invention, referring to Fig. 5, is implemented in aforementioned hardware
On the basis of example, can also include:
Second judgment unit 50 for obtaining the data of the corresponding privately owned caching of the memory, and judges described privately owned slow
It deposits in corresponding memory with the presence or absence of first memory；
Second writing unit 51, if determining to deposit in the corresponding memory of the privately owned caching for the second judgment unit
In first memory, the data of the corresponding interior privately owned caching for saving as first memory are directly stored in corresponding memory
In.
In the present embodiment, every time when storing the data of privately owned caching into memory, require to judge to be stored interior
Whether be first memory, if the memory to be stored is the first memory, it is straight that the data of privately owned caching are skipped shared buffer memory if depositing
Storage is connect into the memory to be stored.And with the presence or absence of in preset first in the corresponding memory of the judgement privately owned caching
It deposits, may include: the initial address and zone length for obtaining first memory respectively from the first register and the second register；
Exist in [initial address, termination address] range if judgement is known in the address of the corresponding memory of the privately owned caching
Address, it is determined that there are first memories in the corresponding memory of the privately owned caching, wherein the termination address is described rises
Beginning address and zone length and.It is described to judge to whether there is preset first memory in the corresponding memory of the privately owned caching,
Also may include: from third register and the 4th register obtain respectively the corresponding memory of the privately owned caching initial address and
Mask data；It is carried out with the Mask data by bit if judgement is known to exist in the address of the corresponding memory of the privately owned caching
Address of the result of position and operation equal to the initial address, it is determined that there are described the in the corresponding memory of the privately owned caching
One memory.
On the basis of aforementioned hardware embodiment, first judging unit specifically can be used for:
Obtain the initial address and zone length of first memory respectively from the first register and the second register；
If judgement, which is known, has the address in [initial address, termination address] range in the address of the memory,
Then determine that there are first memories in the memory, wherein the termination address is the initial address and zone length
With.
On the basis of aforementioned hardware embodiment, first judging unit specifically can be used for:
Obtain the initial address and Mask data of first memory respectively from third register and the 4th register；
If the result for existing in the address of the memory and being carried out with the Mask data by bit and operation is known in judgement
Equal to the address of the initial address, it is determined that there are first memories in the memory.
In the present embodiment, by the address of memory and the Mask data carry out by bit and the result of operation whether etc.
Determine whether memory is first memory in the initial address, the hardware logic of such mode is compared to previous embodiment
Whether in [initial address, termination address] range determine whether memory is first memory by the address of memory
Hardware logic it is relatively simple.
On the basis of aforementioned hardware embodiment, the sensitive data of the described pair of side-channel attack based on shared buffer memory can be with
It include: the local variable and code of program.
On the basis of aforementioned hardware embodiment, first memory may include what preset memory allocation function was distributed
Memory.
Finally, it should be noted that the above various embodiments is only to illustrate the technical solution of the application, rather than its limitations；To the greatest extent
Pipe is described in detail the application referring to foregoing embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, each embodiment technology of the application that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (12)
1. a kind of date storage method characterized by comprising
The data of memory to be stored are obtained, and are judged in the memory with the presence or absence of preset first memory；And
If there are first memories in the memory, by the data storage of the first memory described in the memory to the memory
Described in the corresponding privately owned caching of the first memory, and the data of the memory in the memory in addition to first memory are stored
Into the corresponding privately owned caching of the memory in addition to first memory and shared buffer memory, wherein first memory does not make
With shared buffer memory, the data sensitive to the side-channel attack based on shared buffer memory are stored in first memory.
2. the method according to claim 1, wherein further include:
The data of the corresponding privately owned caching of the memory are obtained, and are judged in the corresponding memory of the privately owned caching with the presence or absence of institute
State the first memory；
If in the corresponding memory of the privately owned caching, there are first memories, by the corresponding interior private for saving as first memory
There are the data of caching to be directly stored in corresponding memory.
3. method according to claim 1 or 2, which is characterized in that with the presence or absence of preset in the judgement memory
First memory, comprising:
Obtain the initial address and zone length of first memory respectively from the first register and the second register；
If judgement, which is known, has the address in [initial address, termination address] range in the address of the memory, then really
There are first memories in the fixed memory, wherein the termination address be the initial address and zone length and.
4. method according to claim 1 or 2, which is characterized in that with the presence or absence of preset in the judgement memory
First memory, comprising:
Obtain the initial address and Mask data of first memory respectively from third register and the 4th register；
Be equal to by bit and the result of operation with the Mask data if judgement is known to exist in the address of the memory
The address of the initial address, it is determined that there are first memories in the memory.
5. the method according to claim 1, wherein the described pair of side-channel attack based on shared buffer memory is sensitive
Data include: the local variable and code of program.
6. the method according to claim 1, wherein first memory includes preset memory allocation function point
The memory matched.
7. a kind of data storage device characterized by comprising
First judging unit for obtaining the data of memory to be stored, and judges in the memory with the presence or absence of preset the
One memory；And
First writing unit, if determining that there are first memories in the memory for first judging unit, by institute
The data for stating the first memory described in memory are stored into the corresponding privately owned caching of the first memory described in the memory, and by institute
The data for stating the memory in memory in addition to first memory are stored to the corresponding private of memory in addition to first memory
Have in caching and shared buffer memory, wherein first memory does not use shared buffer memory, is stored in first memory to being based on
The data of the side-channel attack sensitivity of shared buffer memory.
8. device according to claim 7, which is characterized in that further include:
Second judgment unit for obtaining the data of the corresponding privately owned caching of the memory, and judges that the privately owned caching is corresponding
Memory in whether there is first memory；
Second writing unit, if determining to exist in the corresponding memory of the privately owned caching for the second judgment unit described
The data of the corresponding interior privately owned caching for saving as first memory are directly stored in corresponding memory by the first memory.
9. device according to claim 7 or 8, which is characterized in that first judging unit is specifically used for:
Obtain the initial address and zone length of first memory respectively from the first register and the second register；
If judgement, which is known, has the address in [initial address, termination address] range in the address of the memory, then really
There are first memories in the fixed memory, wherein the termination address be the initial address and zone length and.
10. device according to claim 7 or 8, which is characterized in that first judging unit is specifically used for:
Obtain the initial address and Mask data of first memory respectively from third register and the 4th register；
Be equal to by bit and the result of operation with the Mask data if judgement is known to exist in the address of the memory
The address of the initial address, it is determined that there are first memories in the memory.
11. device according to claim 7, which is characterized in that the described pair of side-channel attack based on shared buffer memory is sensitive
Data include: program local variable and code.
12. device according to claim 7, which is characterized in that first memory includes preset memory allocation function
The memory of distribution.
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