CN107704405B - Device for sharing one I2C host by multiple paths of same I2C address equipment - Google Patents
Device for sharing one I2C host by multiple paths of same I2C address equipment Download PDFInfo
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- CN107704405B CN107704405B CN201710828208.6A CN201710828208A CN107704405B CN 107704405 B CN107704405 B CN 107704405B CN 201710828208 A CN201710828208 A CN 201710828208A CN 107704405 B CN107704405 B CN 107704405B
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- 239000003990 capacitor Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000004891 communication Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a device for sharing an I2C host by multiple paths of same I2C address equipment, which comprises: the system comprises a main board, at least two identical back boards and at least two connectors; the number of the connectors is the same as that of the back plates; the mainboard is provided with a BMC chip and a multiplexer; the input end of the multiplexer is connected with the BMC chip, the output end of the multiplexer is connected with each connector, and each connector is connected with a backboard; GPIO configuration information is set in FW of the BMC chip. The device reduces the design difficulty of the back plate, improves the production line production and assembly process and improves the production efficiency.
Description
Technical Field
The invention relates to the field of I2C equipment, in particular to a device for sharing an I2C host by multiple paths of same I2C address equipment.
Background
In the backplane, two devices are generally arranged on an I2C bus, one is a thermal sensor for recording backplane temperature information, the other is a CP L D for recording hard disk related information, the two devices are arranged on the same I2C bus, and I2C addresses of the two devices are different, if more than two same backplanes are used in one complete machine and only one I2C host is provided at the end of the motherboard to communicate with the backplanes at the same time, several identical I2C devices are arranged on one I2C bus, so that the normal communication of the I2C bus is influenced.
It is current practice to configure several different I2C addresses for each I2C device on the backplane and switch the I2C addresses with a skip cap so that when two or more backplanes are used simultaneously, I2C devices of the same address do not appear on the same I2C bus. Although the devices with the same I2C address on the same I2C bus are avoided, the engineering operation is inconvenient, the I2C address is adjusted by manually adjusting the configuration of the jump cap every time, human errors are easy to occur, and the assembly production efficiency is reduced.
Disclosure of Invention
In order to solve the above problems, the present invention provides a device in which multiple devices with the same I2C address share one I2C host, so as to implement normal communication between the I2C host of the BMC chip and the devices on multiple I2C links.
The technical scheme of the invention is as follows: an apparatus for sharing an I2C host among multiple identical I2C address devices, comprising: the system comprises a main board, at least two identical back boards and at least two connectors; the number of the connectors is the same as that of the back plates;
the mainboard is provided with a BMC chip and a multiplexer; the input end of the multiplexer is connected with the BMC chip, the output end of the multiplexer is connected with each connector, and each connector is connected with a backboard;
GPIO configuration information is set in FW of the BMC chip.
Further, the multiplexer is an SN74CB3Q3253 chip.
Furthermore, pins 7, 9, 14, 2, 1 and 15 of the multiplexer are respectively connected with the BMC chip; a 16 pin of the multiplexer is connected with a pull-up power supply, and the 16 pin of the multiplexer is also grounded through a first capacitor; the 8-pin of the multiplexer is grounded.
Further, the device also comprises a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a pull-up resistor R5 and a pull-up resistor R6;
the 6 pin, the 5 pin, the 4 pin, the 10 pin, the 11 pin and the 12 pin of the multiplexer are respectively connected to a pull-up power supply through a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a pull-up resistor R5 and a pull-up resistor R6; the 3 pins and 13 pins of the multiplexer are suspended.
Further, the connector includes a first connector, a second connector and a third connector;
The device provided by the invention has the advantages that multiple paths of devices with the same I2C address share one I2C host, the multiplexer is arranged on the mainboard, GPIO configuration information is arranged in FW of a BMC chip on the mainboard, the multiplexer is controlled by the BMC chip, the I2C host of the BMC chip and the devices on multiple I2C links can normally communicate, the design difficulty of the backboard is reduced, the production and assembly process of a production line is improved, and the production efficiency is improved.
Drawings
FIG. 1 is a circuit schematic of an embodiment of the present invention.
In the figure, U1-multiplexer, U2-BMC chip, J1-first connector, J2-second connector, J3-third connector, R1, R2, R3, R4, R5 and R6-pull-up resistor.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.
The apparatus for sharing one I2C host by multiple paths of same I2C address devices provided by this embodiment includes: the main board, at least two same backplanes, at least two connectors. The connectors correspond to the backplanes, and the number of the connectors is the same as that of the backplanes.
As shown in fig. 1, a BMC chip U2 and a multiplexer U1 are disposed on the motherboard, an input terminal of the multiplexer U1 is connected to the BMC chip U2, an output terminal of the multiplexer U1 is connected to each connector, and each connector is connected to a backplane.
To realize the control of the multiplexer U1 by the BMC chip U2, GPIO configuration information is set in the FW of the BMC chip U2.
In this embodiment, multiplexer U1 may use an SN74CB3Q3253 chip. Pins 7, 9, 14, 2, 1 and 15 of the multiplexer U1 are respectively connected with the BMC chip U2; the 16 pin of the multiplexer U1 is connected with a pull-up power supply, and the 16 pin of the multiplexer U1 is also grounded through a first capacitor C1; the 8 pin of multiplexer U1 is connected to ground.
The BMC chip U2 may control S0, S1, and S L1 of the multiplexer U1 via three GPIO signals I2C _ MUX1_ EN, I2C _ MUX _ SE L0, I2C _ MUX _ SE L1,
The three pins have high and low levels, so that a pair of I2C hosts on the BMC chip U2 can communicate with four I2C links respectively, and only one I2C link can communicate with the I2C host on the BMC chip U2 at the same time point, so that the device addresses on the four I2C links can be the same.
In this embodiment, three connectors may be provided: a first connector J1, a second connector J2, and a third connector J3, which are connected to a backplane, respectively. In order to realize connection with the three backplanes, a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a pull-up resistor R5 and a pull-up resistor R6 are arranged. The 6 pin, the 5 pin, the 4 pin, the 10 pin, the 11 pin and the 12 pin of the multiplexer U1 are respectively connected to a pull-up power supply through a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a pull-up resistor R5 and a pull-up resistor R6; the 3 rd pin and the 13 rd pin of the multiplexer U1 are suspended. Pins 2 and 3 of the first connector J1 are respectively connected with pins 10 and 6 of the multiplexer U1; pin 1 of the first connector J1 is grounded; pins 2 and 3 of the second connector J2 are respectively connected with pins 11 and 5 of the multiplexer U1; pin 1 of the second connector J2 is grounded; pins 2 and 3 of the third connector J3 are respectively connected with pins 12 and 4 of the multiplexer U1; the 1 pin of the third connector J3 is grounded.
The user may also connect two or four backplanes using two or four connectors as desired. By using the device, in the design of the backboard, the same I2C equipment does not need to be provided with a plurality of I2C addresses through the jump cap, so that the design of the backboard is simple, and the operation of changing the jump cap during assembly of a production line is avoided.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.
Claims (2)
1. An apparatus for sharing an I2C host among multiple identical I2C address devices, comprising: the system comprises a main board, at least two identical back boards and at least two connectors; the number of the connectors is the same as that of the back plates;
the mainboard is provided with a BMC chip and a multiplexer; input terminal of multiplexer and
the BMC chip is connected, the output end of the multiplexer is connected with each connector, and each connector is connected with a backboard;
GPIO configuration information is set in FW of the BMC chip;
the multiplexer is an SN74CB3Q3253 chip;
pins 7, 9, 14, 2, 1 and 15 of the multiplexer are respectively connected with the BMC chip; a 16 pin of the multiplexer is connected with a pull-up power supply, and the 16 pin of the multiplexer is also grounded through a first capacitor; the 8-pin of the multiplexer is grounded;
the device also comprises a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a pull-up resistor R5 and a pull-up resistor R6;
the 6 pin, the 5 pin, the 4 pin, the 10 pin, the 11 pin and the 12 pin of the multiplexer are respectively connected to a pull-up power supply through a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a pull-up resistor R5 and a pull-up resistor R6; the 3 pins and 13 pins of the multiplexer are suspended.
2. The apparatus of claim 1, wherein the connectors comprise a first connector, a second connector and a third connector;
pins 2 and 3 of the first connector are respectively connected with pins 10 and 6 of the multiplexer;
the 1 pin of the first connector is grounded;
pins 2 and 3 of the second connector are respectively connected with pins 11 and 5 of the multiplexer;
the pin 1 of the second connector is grounded;
pins 2 and 3 of the third connector are respectively connected with pins 12 and 4 of the multiplexer;
the third connector has pin 1 connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710828208.6A CN107704405B (en) | 2017-09-14 | 2017-09-14 | Device for sharing one I2C host by multiple paths of same I2C address equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710828208.6A CN107704405B (en) | 2017-09-14 | 2017-09-14 | Device for sharing one I2C host by multiple paths of same I2C address equipment |
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| CN107704405A CN107704405A (en) | 2018-02-16 |
| CN107704405B true CN107704405B (en) | 2020-07-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201229748A (en) * | 2011-01-10 | 2012-07-16 | Hon Hai Prec Ind Co Ltd | Server and method for controlling opening of channels |
| CN104123260A (en) * | 2013-04-29 | 2014-10-29 | 鸿富锦精密工业（深圳）有限公司 | BMC read-only memory (ROM) control system and method |
| CN104298583A (en) * | 2013-07-15 | 2015-01-21 | 鸿富锦精密工业（深圳）有限公司 | Mainboard management system and method based on baseboard management controller |
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2017
- 2017-09-14 CN CN201710828208.6A patent/CN107704405B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201229748A (en) * | 2011-01-10 | 2012-07-16 | Hon Hai Prec Ind Co Ltd | Server and method for controlling opening of channels |
| CN104123260A (en) * | 2013-04-29 | 2014-10-29 | 鸿富锦精密工业（深圳）有限公司 | BMC read-only memory (ROM) control system and method |
| CN104298583A (en) * | 2013-07-15 | 2015-01-21 | 鸿富锦精密工业（深圳）有限公司 | Mainboard management system and method based on baseboard management controller |
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| CN107704405A (en) | 2018-02-16 |
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Effective date of registration: 20200618 Address after: 215100 No. 1 Guanpu Road, Guoxiang Street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Applicant after: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 450000 Henan province Zheng Dong New District of Zhengzhou City Xinyi Road No. 278 16 floor room 1601 Applicant before: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY Co.,Ltd. |
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