CN107680942A - Line carrier plate and preparation method thereof - Google Patents

Line carrier plate and preparation method thereof Download PDF

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Publication number
CN107680942A
CN107680942A CN201610619178.3A CN201610619178A CN107680942A CN 107680942 A CN107680942 A CN 107680942A CN 201610619178 A CN201610619178 A CN 201610619178A CN 107680942 A CN107680942 A CN 107680942A
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Prior art keywords
layer
line
carrier plate
base material
patterned
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Granted
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CN201610619178.3A
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Chinese (zh)
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CN107680942B (en
Inventor
林俊廷
王琮熙
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Xinxing Electronics Co Ltd
Unimicron Technology Corp
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Xinxing Electronics Co Ltd
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Publication of CN107680942B publication Critical patent/CN107680942B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The present invention provides a kind of line carrier plate and preparation method thereof, and wherein line carrier plate includes base material, patterned line layer and photoimageable dielectric layer.Base material has relative first surface and second surface.Patterned line layer is configured at first surface, and the line width of patterned line layer is tapered by the direction of first surface towards second surface.Photoimageable dielectric layer corresponding pattern line layer is arranged in base material.In addition, a kind of preparation method of line carrier plate is also mentioned.The present invention is beneficial to the being electrically insulated property of lifting base material and improves the thermal coefficient of expansion of base material, and uses and to form line width towards the cumulative patterned line layer in line carrier plate surface.

Description

Line carrier plate and preparation method thereof
Technical field
The present invention relates to a kind of line carrier plate and preparation method thereof, more particularly to one kind to have photoimageable dielectric layer (photo- Imaginable dielectric layer) line carrier plate.
Background technology
Wiring board techniques now develop into embedded line support plate from general common non-embedded line support plate (embedded trace board).Specifically, the feature of general common non-embedded line support plate is prominent for circuit In on the surface of dielectric layer, and it is interior be embedded in dielectric layer that the feature of embedded line support plate, which is circuit,.
For the embedded line support plate of individual layer, the insulating materials between the cabling of line carrier plate is, for example, with anti-welding green Based on paint.Therefore, anti-welding green paint is in addition to the anti-welding layer material as the surface of line carrier plate, also line as line carrier plate simultaneously Dielectric insulation material between road.However, the thermal coefficient of expansion of the being electrically insulated property and material of anti-welding green paint in itself (Coefficient of Thermal Expansion, CTE) is all not so good as traditional dielectric material.In the micro- of electronic installation now The development trend of type, the area of line carrier plate must also reduce accordingly, therefore the cabling closeness on line carrier plate also needs phase Improve over the ground.But as described above, due to the embedded line support plate of individual layer anti-welding green paint being electrically insulated property not as good as traditional Dielectric material and limit the required minimum separation distances between cabling, and then limit is produced to the design of the cabling of line carrier plate System, it is unfavorable for the further reduction of the area of line carrier plate or thickness.
The content of the invention
The present invention provides a kind of line carrier plate, and it has photoimageable dielectric layer.Photoimageable dielectric layer is configured at the base of line carrier plate In material, with the thermal coefficient of expansion for lifting the being electrically insulated property of base material and improving base material, and use and to form line width towards line carrier plate table The cumulative patterned line layer in face.
The line carrier plate of the present invention includes base material, patterned line layer and photoimageable dielectric layer.Base material has relative One surface and second surface.Patterned line layer is configured at first surface, and the line width of patterned line layer is by first surface Direction towards second surface is tapered.Photoimageable dielectric layer corresponding pattern line layer is arranged in base material.
The preparation method of the line carrier plate of the present invention includes：First carrier is provided, line carrier plate is made with lower thereon.In detail For thin, the first carrier has relative the 3rd surface and the 4th surface.3rd surface and the 4th surface sequentially configure respectively from Type film and the first metal layer.Photoimageable dielectric layer is formed on the first metal layer, and patterns photoimageable dielectric layer.It is dry to form patterning Film layer patterns the first metal layer and photoimageable dielectric layer that photopolymer layer exposes part on photoimageable dielectric layer.With pattern Change photopolymer layer is plating mask, and plating second metal layer is on the first metal layer of part.First surface process layer is formed in the On two metal levels.Patterning photopolymer layer is removed, to expose photoimageable dielectric layer and the first metal layer.Using photoimageable dielectric layer as etching Mask etches the first metal layer, with forming patterned line layer on mould release membrance.Anti-welding material is coated with patterned line layer And to form base material on photoimageable dielectric layer, and expose first surface process layer.Base material has relative first surface and two Surface, and first surface contact mould release membrance.The line width of patterned line layer is tapered by the direction of first surface towards second surface.Match somebody with somebody The second carrier is put on the second surface of base material, and the first carrier is removed by mould release membrance by first surface.Form the second table Face process layer is in the patterned line layer exposed to first surface.
In one embodiment of this invention, the section profile of above-mentioned patterned line layer is in inverted trapezoidal.
In one embodiment of this invention, above-mentioned base material has multiple perforations, and perforation connects first surface respectively And second surface.
In one embodiment of this invention, above-mentioned photoimageable dielectric layer corresponds to contact patterns line layer.
In one embodiment of this invention, above-mentioned line carrier plate also includes first surface process layer, and first surface Process layer is exposed to second surface and is covered in the bottom surface of partially patterned line layer.
In one embodiment of this invention, the composition material of above-mentioned first surface process layer includes nickel, gold or its alloy.
In one embodiment of this invention, above-mentioned line carrier plate also includes carrier, and carrier is configured at second surface On.
In one embodiment of this invention, the composition material of above-mentioned base material includes anti-welding material.
In one embodiment of this invention, above-mentioned line carrier plate also includes second surface process layer, exposed to the first table Face and the top surface of overlay pattern line layer.
In one embodiment of this invention, chip is suitable to configuration on the first surface, is handled with second surface in electrical contact Layer and patterned line layer.
In one embodiment of this invention, the mode of above-mentioned formation second surface process layer includes carrying out electroless plating.
Cause the base material of line carrier plate based on the line carrier plate in above-mentioned, of the invention multiple embodiments and its production method In there is photoimageable dielectric layer, to lift the being electrically insulated property of base material, and the thermal coefficient of expansion for improving base material can not be effectively with holding The problem of matched coefficients of thermal expansion of load chip or patterned line layer.In addition, the base material of line carrier plate has relative One surface and second surface, and the line width of patterned line layer is tapered towards second surface by first surface so that pattern lines Layer can have larger bonding area on the surface of line carrier plate, in favor of being formed in subsequent technique with larger area Chip and routing connection pad.
For features described above of the invention and advantage can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make Carefully it is described as follows.
Brief description of the drawings
Fig. 1 is the schematic diagram of the line carrier plate according to one embodiment of the invention；
Fig. 2 is the schematic diagram of the line carrier plate according to another embodiment of the present invention；
Fig. 3 A to Fig. 3 I are the schematic diagrames of the Making programme of Fig. 1 line carrier plate.
Reference：
50：Chip；
100：Line carrier plate；
110：Base material；
110a：Perforate；
112：First surface；
113：Anti-welding material；
114：Second surface；
120：Patterned line layer；
130：Photoimageable dielectric layer；
130a：Perforation；
142：First surface process layer；
144：Second surface process layer；
160：Soldered ball；
170：Packing colloid；
210：First carrier；
212：3rd surface；
214：4th surface；
215：Upper carrier；
216：Adhesion coating；
217：Lower carrier；
220、270：Mould release membrance；
230：The first metal layer；
240：Second metal layer；
250：Pattern photopolymer layer；
260：The carrier of carrier/second.
Embodiment
Fig. 1 is the schematic diagram of the line carrier plate according to one embodiment of the invention.In the present embodiment, line carrier plate 100 Including base material 110, patterned line layer 120 and light-sensitive medium layer 130.As shown in figure 1, base material 110 has relative first Surface 112 and second surface 114.Patterned line layer 120 is embedded in the first surface 112 of base material, and patterned line layer 120 line width is tapered from the direction of first surface 112 to second surface 114.In the present embodiment, patterned line layer 120 exists Profile on section is, for example, inverted trapezoidal wide at the top and narrow at the bottom.
In the present embodiment, the corresponding pattern line layer 120 of photoimageable dielectric layer 130 is configured in base material 110, and photosensitive Jie Electric layer 130 corresponds to each other with patterned line layer 120 and contacted.In addition, line carrier plate 100 include first surface process layer 142 and Second surface process layer 144, its connection pad respectively as soldered ball, routing and chip.As shown in figure 1, first surface process layer 142 are configured at the bottom surface of partially patterned line layer 120.Second surface process layer 144 is configured at the top of patterned line layer 120 Face, and on the first surface 112 being exposed to.Furthermore as shown in figure 1, line carrier plate 100 comprises additionally in carrier 260, it is configured In on the second surface 114 of base material 110, and there is mould release membrance 270 between base material 110 and carrier 260.
In the present embodiment, base material 110 is mainly made up of anti-welding material 113, and anti-welding material 113 is, for example, anti- Weld green paint or other similar dielectric materials.In addition, the composition of first surface process layer 142 and second surface process layer 144 Material is, for example, the alloy material of nickel, gold or aforementioned metal.As shown in figure 1, anti-welding material 113 can expose and be configured at pattern Change the second surface process layer 144 on line layer 120.In the present embodiment, anti-welding material 11 can be used as base material 110 simultaneously Surface welding resisting layer and circuit between dielectric insulation layer.Furthermore the first surface 112 of base material 110 has multiple perforates 110a, and perforate 110a can be electroplated or the mode of electroless plating (electroless plating) inserts line layer and welding resisting layer Material.
In the present embodiment, due to being electrically insulated property and material the heat in itself of the anti-welding material 113 that forms base material 110 The matching of the coefficient of expansion is all not as good as general traditional dielectric material, therefore, the present embodiment 110 further configuration sense in base material Light dielectric layer 130, which can effectively lift being electrically insulated for base material 110, ability and improves the matching problem of the thermal coefficient of expansion of material.
Specifically, in the present embodiment, line carrier plate 100 is directly exhausted as the dielectric of base material 110 to prevent wlding material 113 Edge material can effectively reduce the thickness of overall line carrier plate 100, without separately configuring other dielectrics in line carrier plate 100 Layer.However, when subsequently chip (not shown) is configured on base material 110, due to thermal coefficient of expansion between chip and base material 110 Difference, and produce relative stress and strain, it easily produces injury in itself for chip.Therefore, in the present embodiment, will Photoimageable dielectric layer 130 is configured at the problem of matched coefficients of thermal expansion that can improve base material 110 and chip in base material 110, to slow down Due to stress caused by the difference of thermal coefficient of expansion and strain between chip and base material 110, and reduce for chip in itself Injury.
Fig. 1 is refer again to, in the present embodiment, due to the patterning in the first surface 112 and perforate 110a of base material 110 The section profile of line layer 120 is the shape in inverted trapezoidal wide at the top and narrow at the bottom.Therefore, in the pattern of first surface 112 of base material 110 The connection pad of chip or routing with larger area can be formed by changing on line layer 120.
Fig. 2 is the schematic diagram of the line carrier plate according to another embodiment of the present invention.The present embodiment and Fig. 1 embodiment Difference is, chip 50 is can configure on the first surface 112 of base material 100, and it is electrically connected with the on first surface 112 Two surface-treated layers 144 and patterned line layer 120.In addition, after the completion of chip 50 configures, the second of base material 110 is configured at Carrier 260 on surface 114 can remove via mould release membrance 270 from second surface 114.Furthermore exposed to the second of base material 110 The first surface process layer 142 on surface 114, it can carry out planting ball technique thereon, to form soldered ball (solder bump) 160.Cause This, chip 50 can be electrically connected with other chips or line carrier plate via soldered ball 160.In the present embodiment, the of base material 110 Packing colloid 170 is can configure on one surface 112 to cover chip 50 and patterned line layer 120, and protection is provided to it.
Fig. 3 A to Fig. 3 I are the schematic flow sheets of the preparation method of Fig. 1 line carrier plate.It refer to Fig. 3 A to Fig. 3 I, circuit The step of preparation method of support plate 100, includes：First carrier 210 (such as Fig. 3 A) is provided.In the present embodiment, the first carrier 210 With the 3rd relative surface 212 and the 4th surface 214, and can sequentially match somebody with somebody respectively on the 3rd surface 212 and the 4th surface 214 Put mould release membrance 220 and the first metal layer 230.The first metal layer 230 of the present embodiment is, for example, layers of copper.As shown in Figure 3A, this reality The first carrier 210 for applying example can be the multilayer carrier that is collectively constituted by upper carrier 215 and lower carrier 217, and upper carrier 215 And attaching of being adhered each other by adhesion coating 216 between lower carrier 217.
Then, as shown in Figure 3 B, the photoimageable dielectric layer 130 after patterned can be pressed together on the 3rd surface 212 and the 4th table On the first metal layer 230 in face 214.In the present embodiment, the photoimageable dielectric layer 130 being pressed on the first metal layer 230 first passes through Patterned by photoetching process, in wherein forming multiple perforation 130a, to expose the first gold medal of part in successive process Belong to layer 230.In the present embodiment, upper carrier 215 and lower carrier 217 and its mould release membrance 220 and the first metal layer 230 on surface Subsequently all carried out with identical fabrication steps.Therefore, in following accompanying drawing and explanation, by the table of above carrier 215 and its 3rd Illustrated exemplified by the technique carried out on face 212, and the process portion on the surface 214 of lower carrier 217 and its 4th will no longer Repeatedly repeat and show.
As shown in Figure 3 C, patterning photopolymer layer 250 can be formed on photoimageable dielectric layer 130, and it is sudden and violent to pattern photopolymer layer 250 Reveal photoimageable dielectric layer 130, perforation 130a therein and the partial the first metal layer 230 of part.Then, as shown in Figure 3 D, Patterning photopolymer layer 250 and the photoimageable dielectric layer 130 of above-mentioned part can be used as plating mask, with the part in perforation 130a the Second metal layer 240 is electroplated on the surface of one metal level 230.In the present embodiment, second metal layer 240 is, for example, electro-coppering Layer.
As shown in FIGURE 3 E, first surface process layer 142 can be then formed in a manner of plating in second metal layer 240. In the present embodiment, the weldering that first surface process layer 142 can be in the plant ball technique of follow-up line carrier plate 100 as soldered ball 160 Pad.Then, as illustrated in Figure 3 F, patterning photopolymer layer 250 is removed, to expose its remaining part for being patterned the masking of photopolymer layer 250 The photoimageable dielectric layer 130 and the first metal layer 230 divided.
Then, as shown in Figure 3 G, photoimageable dielectric layer 130 can be used as etching mask, with first for foregoing remainder Metal level 230 is etched, and patterned line layer 120 is formed on the mould release membrance 220 on the 3rd surface 212.
Then, as shown in figure 3h, anti-welding material 113 is coated with patterned line layer 120 and photoimageable dielectric layer 130, with Base material 110 is formed, and anti-welding material 113 exposes first surface process layer 142.Foregoing base material 100 has relative the One surface 112 and second surface 114.In addition, mould release membrance 220 and base material 110 on the 3rd surface 212 of the first carrier 210 First surface 112 contacts with each other.As shown in figure 3h, the section profile of patterned line layer 120 by base material 110 first surface 112 is tapered toward the direction towards second surface 114.
As shown in fig. 31, the second carrier 260 is attached on the second surface 114 of base material 110, and the second carrier 260 There is mould release membrance 270 between base material 110.Then, on the first surface 112 of base material 110 is removed via mould release membrance 220 One carrier 210.Then, to be, for example, electroless technology mode, the pattern on the first surface 112 exposed to base material 110 Change and second surface process layer 144 is formed on line layer 120.So far, the making of line carrier plate 100 is substantially completed.
In the Making programme of the line carrier plate 100 of the invention described above, because photoimageable dielectric layer 130 can directly be used to make For plating and etching mask, therefore, the first list processing layer 142 when plating second metal layer 240 and thereon and etching first During metal level 230, without configuring other dry films or photoresist layer in addition.In addition, in the manufacturing process of line carrier plate 100, when After the completion of the plating of two metal levels 240, in second metal layer 240 can Direct Electroplating form first surface process layer 142, to be used as plant Ball pad, and in formation soldered ball 160 in first surface process layer 142 in subsequent technique.In other words, the processing procedure side of the present embodiment Formula is completed to plant the making of ball pad in the lump during line carrier plate 100 makes.Therefore, in successive process, circuit The solderable soldered ball 160 in surface of support plate 100 so that the chip 50 being configured on line carrier plate 100 can be by soldered ball 160 and other Chip or support plate be electrically connected with.
In summary, line carrier plate of multiple embodiments of the invention and preparation method thereof can be by the making of line carrier plate During using photoimageable dielectric layer as plating or etching mask, to electroplate second metal layer, first surface process layer and lose The first metal layer is carved, to form patterned line layer.In addition, after line carrier plate completes, photoimageable dielectric layer can be embedded in In the base material of line carrier plate, to lift the being electrically insulated property of base material, and improve base material and carrying chip and patterned circuit The matching problem of the thermal coefficient of expansion of the material of layer.Furthermore in the preparation method of the line carrier plate in the present invention, line carrier plate exists It is the plant ball pad that electrodepositable forms soldered ball in manufacturing process, further to simplify the processing step of line carrier plate.
In addition, in embodiments of the invention, the section profile of the patterned line layer of line carrier plate can be Inverted trapezoidal wide at the top and narrow at the bottom, to increase patterned line layer in the chip on the surface of line carrier plate and the connection pad area of routing.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, all in the present invention In the range of.

Claims (12)

  1. A kind of 1. line carrier plate, it is characterised in that including：
    Base material, there is relative first surface and second surface；
    Patterned line layer, the first surface is configured at, and the line width of the patterned line layer is by the first surface court The direction of the second surface is tapered；And
    Photoimageable dielectric layer, the corresponding patterned line layer are arranged in the base material.
  2. 2. line carrier plate according to claim 1, it is characterised in that the section profile of the patterned line layer is terraced in falling Shape.
  3. 3. line carrier plate according to claim 1, it is characterised in that the base material has multiple perforations, connects institute respectively State first surface and the second surface.
  4. 4. line carrier plate according to claim 1, it is characterised in that the photoimageable dielectric layer correspondingly contacts the patterning Line layer.
  5. 5. line carrier plate according to claim 1, it is characterised in that also including first surface process layer, exposed to described Second surface and the bottom surface for being covered in the part patterned line layer.
  6. 6. line carrier plate according to claim 5, it is characterised in that the composition material of the first surface process layer includes Nickel, gold or its alloy.
  7. 7. line carrier plate according to claim 1, it is characterised in that also including carrier, be configured at described the second of base material On surface.
  8. 8. line carrier plate according to claim 1, it is characterised in that the composition material of the base material includes anti-welding material.
  9. 9. line carrier plate according to claim 1, it is characterised in that also including second surface process layer, exposed to described First surface and the top surface for covering the patterned line layer.
  10. 10. line carrier plate according to claim 9, it is characterised in that chip is suitable to configuration on the first surface, with The second surface process layer in electrical contact and the patterned line layer.
  11. A kind of 11. preparation method of line carrier plate, it is characterised in that including：
    First carrier is provided, first carrier has relative the 3rd surface and the 4th surface, wherein the 3rd surface and Mould release membrance and the first metal layer are sequentially configured on 4th surface respectively；
    Photoimageable dielectric layer is formed on the first metal layer, and patterns the photoimageable dielectric layer；
    Patterning photopolymer layer is formed on the photoimageable dielectric layer, and the patterning photopolymer layer exposes described the of part One metal level and the photoimageable dielectric layer；
    Using the patterning photopolymer layer as plating mask, plating second metal layer on the first metal layer of the part, And first surface process layer is formed in the second metal layer；
    The patterning photopolymer layer is removed, to expose the photoimageable dielectric layer of another part and the first metal layer；
    Using photoimageable dielectric layer as etching mask, the first metal layer is etched, with forming a patterned lines on the mould release membrance Road floor；
    Anti-welding material is coated with the patterned line layer and the photoimageable dielectric layer, to form base material, and exposes institute First surface process layer is stated, wherein the base material has relative first surface and second surface, and the first surface contacts The mould release membrance, and the line width of the patterned line layer is tapered by the direction of the first surface towards the second surface；
    The second carrier is configured on the second surface, and first carrier by the mould release membrance by the first surface Remove；And
    Second surface process layer is formed in the patterned line layer exposed to the first surface.
  12. 12. the preparation method of line carrier plate according to claim 11, it is characterised in that form the second surface processing The mode of layer includes carrying out electroless plating.
CN201610619178.3A 2016-08-01 2016-08-01 Line carrier plate and preparation method thereof Active CN107680942B (en)

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CN107680942B CN107680942B (en) 2019-10-11

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090314525A1 (en) * 2005-06-01 2009-12-24 Mitsui Mining & Smelting Co., Ltd. Mold for Wiring Substrate Formation and Process for Producing the Same, Wiring Substrate and Process for Producing the Same, Process for Producing Multilayered Laminated Wiring Substrate and Method for Viahole Formation
US20120222299A1 (en) * 2009-01-09 2012-09-06 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a printed circuit board
CN103066049A (en) * 2011-10-24 2013-04-24 联致科技股份有限公司 Package substrate and manufacture method thereof
US20150333004A1 (en) * 2014-05-13 2015-11-19 Qualcomm Incorporated Substrate and method of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090314525A1 (en) * 2005-06-01 2009-12-24 Mitsui Mining & Smelting Co., Ltd. Mold for Wiring Substrate Formation and Process for Producing the Same, Wiring Substrate and Process for Producing the Same, Process for Producing Multilayered Laminated Wiring Substrate and Method for Viahole Formation
US20120222299A1 (en) * 2009-01-09 2012-09-06 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a printed circuit board
CN103066049A (en) * 2011-10-24 2013-04-24 联致科技股份有限公司 Package substrate and manufacture method thereof
US20150333004A1 (en) * 2014-05-13 2015-11-19 Qualcomm Incorporated Substrate and method of forming the same

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