US20120222299A1 - Method of manufacturing a printed circuit board - Google Patents
Method of manufacturing a printed circuit board Download PDFInfo
- Publication number
- US20120222299A1 US20120222299A1 US13/474,388 US201213474388A US2012222299A1 US 20120222299 A1 US20120222299 A1 US 20120222299A1 US 201213474388 A US201213474388 A US 201213474388A US 2012222299 A1 US2012222299 A1 US 2012222299A1
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- layer
- insulating
- insulating layer
- circuit
- embedded
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011810 insulating material Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 238000003825 pressing Methods 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 189
- 229910000679 solder Inorganic materials 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000007792 addition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- the present invention relates to a printed circuit board and a method of manufacturing the printed circuit board.
- a printed circuit board of a high density and reliability are closely related to the specifications of the desired semiconductor chip.
- the printed circuit board having high density and high reliability must further be developed to have many characteristics such as the implementation of fine circuits, excellent electrical properties, structure for high-speed transmission of signals, high reliability, high performance, slimness and the like. Accordingly, a technology for printed circuit board which is capable of forming fine circuit patterns and micro via-holes is required in order to meet these needs.
- FIGS. 1 to 5 are cross-sectional views showing a conventional process of manufacturing a printed circuit board.
- the conventional process of manufacturing a printed circuit board will now be described with reference to the drawings.
- a copper clad laminate which comprises an insulating layer 12 and copper layers 14 disposed on the insulating layer 12 is prepared.
- a via-hole 16 for the interlayer electrical connection is formed in the copper clad laminate using mechanical drilling or laser machining.
- a plated layer 18 is applied on the inner wall of the via-hole 16 as well as the copper layer 14 .
- the plated layer 18 includes an electroless plated layer formed by an electroless plating process and an electrolytic plated layer formed by an electrolytic plating process.
- the plated layer 18 is shown in FIG. 3 as being composed of a single plated layer.
- the copper layer 14 and the plated layer 18 are patterned to create a circuit layer 20 .
- a solder resist layer 22 having an opening 24 through which a pad part of the circuit layer 20 is exposed is disposed on the insulating layer 12 , thus finishing a printed circuit board 50 .
- the printed circuit board which is manufactured through the conventional process is configured such that the circuit layer 20 including the pad part is formed on the insulating layer 12 and the solder resist layer 22 for protecting the outermost circuit layer 20 is formed on the insulating layer 12 . Consequently, the printed circuit board 50 configured in this manner is problematic in that its thickness is increased and reliability of the high density circuit is deteriorated.
- the printed circuit board is configured such that the pad part and the solder resist layer 50 are formed on the insulating layer 12 , stepped portions occur in the course of machining the openings 24 through which the pad part is exposed, thus making printability of external connection terminals uneven.
- the openings must be machined while taking into consideration manufacturing error, the openings 24 are inevitably made larger than the pad part, thus reducing a degree of freedom in the design of the openings 24 .
- the present invention has been made keeping in mind the above problems occurring in the related art, and the present invention provides a printed circuit board and a method of manufacturing the same which enable configuration into a slim structure and improving the reliability of a high-density circuit.
- the present invention provides a printed circuit board and a method of manufacturing the same in which a circuit layer and a solder resist layer are embedded in an insulating layer such that there is no stepped portion between a pad part and the solder resist layer, thus increasing a degree of freedom of design.
- the present invention provides a printed circuit board including: an insulating layer; at least one circuit layer embedded in the insulating layer and having a connection pad that is embedded in the insulating layer such that one side of the connection pad is flush with a surface of the insulating layer; and a insulating materials configured to protect the circuit layer from an external environment and having an opening through which the connection pad is exposed.
- the at least one circuit layer may include a first circuit layer disposed on one side of the insulating layer and a second circuit layer disposed on the other side of the insulating layer, and the insulating layer may include a bump for connecting the first circuit layer with the second circuit layer.
- connection pad which is flush with the insulating layer may act as an exposed surface to which an external terminal is bonded.
- the insulating materials may be flush at one side with the insulating layer and may be embedded at the other side in the insulating layer.
- the at least one circuit layer may be formed on the other side of the insulating materials and may be embedded in the insulating layer.
- the at least one circuit layer may be embedded in the insulating materials.
- the insulating layer may include photosensitive insulating material.
- the present invention provides a method of manufacturing a printed circuit board, including: (A) forming at least one circuit layer on a semi-cured insulating layer, the circuit layer having a connection pad; (B) forming insulating materials on the insulating layer, the insulating materials having an opening through which the connection pad is exposed; and (C) pressing and embedding the circuit layer and the insulating materials into the insulating layer.
- the circuit layer may include: (A1) printing a first metal layer with a bump; (A2) applying a semi-cured insulating layer on the first metal layer printed with the bump; and (A3) applying a second metal layer on the insulating layer and patterning the first and second metal layers to form first and second circuit layers each having a connection pad.
- connection pad In (C) pressing and embedding the circuit layer and the insulating materials, one side of the connection pad, which is flush with the insulating layer, may act as an exposed surface to which an external terminal is bonded.
- the insulating materials may be flush at one side with the insulating layer and may be embedded at the other side in the insulating layer.
- the at least one circuit layer may be formed on the other side of the insulating materials and may be embedded in the insulating layer.
- the at least one circuit layer may be embedded in the insulating materials.
- the pressing may be executed while the insulating layer is in a semi-cured state.
- the insulating materials may be made of photosensitive insulating material.
- (B) forming the insulating materials may include: (B1) applying a photosensitive insulating material on the insulating layer; and (B2) subjecting the photosensitive insulating material to exposure and development processes to form an opening through which the connection pad is exposed.
- FIGS. 1 to 5 are cross-sectional views showing a conventional process of manufacturing a printed circuit board
- FIG. 6 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
- FIGS. 7 to 14 are cross-sectional views showing a process of manufacturing the printed circuit board shown in FIG. 6 .
- FIG. 6 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
- the printed circuit board 100 according to this embodiment is described below with reference to FIG. 6 .
- the printed circuit board 100 comprises an insulating layer 106 , circuit layers 102 a, 108 a embedded in the insulating layer 106 , and insulating materials 110 a, 110 b embedded in the surface regions of the insulating layer 106 to protect the circuit layers 102 a, 108 a from the external environment.
- the circuit layers 102 a, 108 a are configured such that the first circuit layer 102 a is formed on a side of the insulating layer 106 and the second circuit layer 108 a is formed on the other side of the insulating layer 106 .
- the first and second circuit layers 102 a, 108 a are connected to each other via bumps 104 passing through the insulating layer 106 .
- Connection pads of the circuit layers 102 a, 108 a are embedded in the insulating layer 106 such that external surfaces of the connection pads are flush with the external surfaces of the insulating layer 106 .
- one side of the connection pad is flush with the external surface of the insulating layer 106 to offer an exposed surface to which an external connection terminal such as solder ball is bonded, and the other side of the connection pad is embedded in the insulating layer 106 .
- the insulating materials 110 a, 110 b are also embedded in the insulating layer 106 such that external sides thereof are flush with the external surfaces of the insulating layer 106 in order to protect the first circuit layer 102 a and/or the second circuit layer 108 a from the external environment. Specifically, one side of each of the insulating materials 110 a, 110 b is flush with the external surface of the insulating layer 106 , and the other side of the insulating materials is embedded in the insulating layer 106 .
- circuit layers 102 a, 108 a excluding the connection pads are also embedded in the insulating layer 106 so as not to be exposed to the outside.
- the circuit layers 102 a, 108 a excluding the connection pads may be embedded in the insulating layer 106 such that the external surfaces thereof are disposed on the other sides, i.e., internal surfaces of the insulating materials 110 a, 110 b for the protection from the external environment (see FIG. 6 ) or they are embedded in the insulating materials 110 a, 110 b (see FIG. 14 ).
- the circuit layers 102 a, 108 a may have any embedded configuration as long as the circuit layers 102 a, 108 a are protected from the external environment by the insulating materials 110 a, 110 b.
- the circuit layers 102 a, 108 a are shown in FIG. 14 as being entirely embedded in the insulating materials 110 a, 110 b, circuit layers which are at least partially embedded in the insulating materials 110 a, 110 b should also be construed as falling within the scope of the present invention.
- the insulating layers 110 a, 110 b may be composed of photosensitive insulating material.
- the printed circuit board 100 is shown in FIG. 6 as having a two-layered structure, this is no more than a single exemplary structure. Accordingly, it will be appreciated that the scope of the present invention may include any of various structures wherein a multilayered buildup layer is formed, a connection pad formed on the outermost layer is embedded in an insulating layer so as to be flush with an outermost insulating layer, and an outermost circuit layer is protected by insulating materials embedded in the outermost insulating layer.
- FIGS. 7 to 14 are cross-sectional views showing a process of manufacturing the printed circuit board shown in FIG. 6 . The process is described below with reference to the drawings.
- a first metal layer 102 is prepared.
- a copper layer typically used in the creation of a circuit layer of a printed circuit board may be used.
- bumps 104 are formed on the first metal layer 102 .
- the bumps 104 may be formed using a screen print technology.
- the screen print technology is executed in a manner such that conductive paste is transferred to the metal layer through openings of a mask. Specifically, openings of the mask are aligned with the metal layer 102 , and then conductive paste is applied onto the mask. Subsequently, the conductive paste is wiped using a squeegee, so that the conductive paste is extruded through the openings of the mask and is then transferred to the first metal layer 102 into a pattern having the desired shape and height.
- a process of forming the bumps 104 through any other of known technologies also falls within the scope of the present invention.
- the conductive paste that constitutes the bumps 104 may include any conductive material, for example, one selected from among Ag, Pd, Pt, Ni and Ag/Pd.
- an insulating layer 106 is applied onto the first metal layer 102 on which the bumps 104 were formed.
- the insulating layer 106 may be configured such that its thickness is less than the height of the bumps 104 , and may be formed in a contact or noncontact way.
- the process of contact way formation is executed in a manner such that the insulating layer 106 is applied onto the first metal layer 102 on which the bumps 104 were formed.
- the bumps 104 may have a rigidity higher than that of the insulating layer 106 such that the bumps 104 penetrate through the insulating layer 106 , and the insulating layer 106 may be embodied as a semi-cured prepreg made of thermosetting resin.
- the insulating layer 106 since the insulating layer 106 has a thickness less than the height of the bumps 104 , the bumps protrude from the insulating layer 106 by the difference therebetween.
- the process of noncontact way formation is executed in a manner such that the metal layer is coated with insulating resin powder using an ink-jet print technology.
- This process is advantageous in that it minimizes problems such as deformation of the bumps and generation of fine gaps between the bumps 104 and the insulating layer 16 which may otherwise occur in the process of the contact way in which the bumps 104 are under pressure from the insulating layer 106 while penetrating through the insulating layer 106 .
- second metal layers 108 are applied onto the insulating layer 106 .
- the second metal layer 108 is formed in a manner such that the insulating layer 106 and the bumps 104 are heated to a temperature higher than a softening temperature thereof under a vacuum condition and are thus semi-cured, and then the second metal layer 108 is pressed onto the semi-cured components using a press plate such as a stainless steel plate with a flat surface. By the pressing of the second metal layer 108 , the second metal layer 108 is connected to the bumps 104 .
- the second metal layer 108 is pressed by the press plate having a flat surface, the pressure of the press plate is evenly transmitted to the insulating layer 106 , thus preventing warping or twisting from occurring throughout the substrate. Furthermore, since the pressing is executed under vacuum conditions, there is no occurrence of voids in the insulating layer 106 .
- the first metal layer 102 and the second metal layer 108 are patterned to create a first circuit layer 102 a and a second circuit layer 108 a each having a connection pad.
- the first circuit layer 102 a and the second circuit layer 108 a may be created using a typical process such as a subtractive process. Specifically, the first circuit layer 102 a and the second circuit layer 108 a may be created in a manner such that dry films are applied onto the first metal layer 102 and the second metal layer 108 and then the first and second metal layers 102 and 108 are subjected to exposure, development and etching processes in this order.
- the first circuit layer 102 a and the second circuit layer 108 a are formed on the semi-cured insulating layer 106 .
- the reason for this is because the first circuit layer 102 a, the second circuit layer 108 a and insulating materials 110 a, 110 b which are described below must be embedded in the insulating layer 106 .
- the insulating materials 110 a, 110 b having openings through which the insulating layer 106 is exposed are formed on the insulating layer 106 .
- the insulating materials 110 a, 110 b which are provided so as to serve as solder resist layers for protecting the first and second circuit layers 102 a, 108 a, may be made of a photosensitive insulating material that has a higher reliability than a general solder resist material and which allows for provision of openings by a simple process. Specifically, this procedure may be implemented by applying photosensitive insulating material 110 a, 110 b onto the insulating layer 106 and subjecting the photosensitive insulating material to exposure and development processes to form the openings through which the connection pads are exposed.
- the insulating materials 110 a, 110 b applied to the insulating layer 106 may have a thickness exceeding that of the first circuit layer 102 a and the second circuit layer 108 a so as to protect the first and second circuit layer 102 a, 108 a from the external environment.
- the first and second circuit layers 102 a, 108 a including the connection pads and the insulating materials 110 a, 110 b are pressed and are thus embedded in the insulating layer 106 .
- the embedding procedure is implemented by pressing the first and second circuit layers 102 a, 108 a and the insulating materials 110 a, 110 b into the semi-cured insulating layer 106 using a press plate such as a flat stainless steel plate.
- connection pads of the first and second circuit layers 102 a, 108 a are embedded in the insulating layer 106 such that outer surfaces thereof are flush with the surface of the insulating layer 106 .
- one side of each of the connection pads is flush with the surface of the insulating layer 106 and acts as an exposed surface on which an external connection terminal such as a solder ball is bonded, and the other side of the connection pad is embedded in the insulating layer 106 .
- the insulating materials 110 a, 110 b are also embedded in the insulating layer 106 with their external surfaces flush with the surface of the insulating layer 106 .
- one side of each of the insulating materials 110 a, 110 b is flush with the surface of the insulating layer 106 , and the other side of the insulating materials is embedded in the insulating layer 106 .
- the first and second circuit layers 102 a, 108 a excluding the connection pads thereof are embedded in the insulating layer 106 so as not to be exposed to the external environment.
- the insulating materials 110 a, 110 b may be deformed by the pressing force of the press plate and the repulsion force of the insulating layer 106 against the pressing force so that the first and second circuit layers 102 a, 108 a are disposed on the internal surfaces of the insulating materials 110 a, 110 b.
- the insulating materials 110 a, 110 b and the first and second circuit layers 102 a, 108 a may be embedded in the insulating layer 106 without their initial configuration being changed, as shown in FIG. 14 .
- first and second circuit layers 102 a, 108 a are shown in FIG. 14 as being entirely embedded in the insulating materials 110 a, 110 b, the first and second circuit layers 102 a, 108 a may be partially embedded in the insulating materials 110 a, 110 b.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
A printed circuit board and a method of manufacturing the printed circuit board, in which the printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer and having a connection pad that is embedded in the insulating layer such that one side of the connection pad is flush with a surface of the insulating layer, and insulating materials configured to protect the circuit layer from an external environment and having an opening through which the connection pad is exposed. The printed circuit board is made slim, and reliability and the degree of design freedom are increased.
Description
- This application is a U.S. divisional application filed under 37 CFR 1.53(b) claiming priority benefit of U.S. Ser. No. 12/385,003, filed in the United States on Mar. 27, 2009, now allowed, which claims earlier priority benefit to Korean Patent Application No, 10-2009-0001971, filed Jan. 9, 2009, entitled “A printed circuit board and a fabricating method the same”, the disclosures of which are incorporated herein by reference.
- 1. Field
- The present invention relates to a printed circuit board and a method of manufacturing the printed circuit board.
- 2. Description of the Related Art
- Recently, demands for a technology which directly mounts a semiconductor chip on a printed circuit board has been increasing in response to the development of highly-densified semiconductor chips and the high-speed transmission of signals. Consequently, the development of printed circuit boards of a high density and high reliability which are suitable to highly-densified semiconductor chips is required.
- Requirements for a printed circuit board of a high density and reliability are closely related to the specifications of the desired semiconductor chip. The printed circuit board having high density and high reliability must further be developed to have many characteristics such as the implementation of fine circuits, excellent electrical properties, structure for high-speed transmission of signals, high reliability, high performance, slimness and the like. Accordingly, a technology for printed circuit board which is capable of forming fine circuit patterns and micro via-holes is required in order to meet these needs.
-
FIGS. 1 to 5 are cross-sectional views showing a conventional process of manufacturing a printed circuit board. The conventional process of manufacturing a printed circuit board will now be described with reference to the drawings. - First, as shown in
FIG. 1 , a copper clad laminate which comprises aninsulating layer 12 andcopper layers 14 disposed on theinsulating layer 12 is prepared. - As shown in
FIG. 2 , a via-hole 16 for the interlayer electrical connection is formed in the copper clad laminate using mechanical drilling or laser machining. - As shown in
FIG. 3 , aplated layer 18 is applied on the inner wall of the via-hole 16 as well as thecopper layer 14. In this regard, theplated layer 18 includes an electroless plated layer formed by an electroless plating process and an electrolytic plated layer formed by an electrolytic plating process. For the convenience of explanation, theplated layer 18 is shown inFIG. 3 as being composed of a single plated layer. - As shown in
FIG. 4 , thecopper layer 14 and theplated layer 18 are patterned to create acircuit layer 20. - Finally, as shown in
FIG. 5 , asolder resist layer 22 having anopening 24 through which a pad part of thecircuit layer 20 is exposed is disposed on theinsulating layer 12, thus finishing a printedcircuit board 50. - The printed circuit board which is manufactured through the conventional process is configured such that the
circuit layer 20 including the pad part is formed on theinsulating layer 12 and thesolder resist layer 22 for protecting theoutermost circuit layer 20 is formed on theinsulating layer 12. Consequently, the printedcircuit board 50 configured in this manner is problematic in that its thickness is increased and reliability of the high density circuit is deteriorated. - Furthermore, since the printed circuit board is configured such that the pad part and the
solder resist layer 50 are formed on theinsulating layer 12, stepped portions occur in the course of machining theopenings 24 through which the pad part is exposed, thus making printability of external connection terminals uneven. In addition, since the openings must be machined while taking into consideration manufacturing error, theopenings 24 are inevitably made larger than the pad part, thus reducing a degree of freedom in the design of theopenings 24. - Accordingly, the present invention has been made keeping in mind the above problems occurring in the related art, and the present invention provides a printed circuit board and a method of manufacturing the same which enable configuration into a slim structure and improving the reliability of a high-density circuit.
- Furthermore, the present invention provides a printed circuit board and a method of manufacturing the same in which a circuit layer and a solder resist layer are embedded in an insulating layer such that there is no stepped portion between a pad part and the solder resist layer, thus increasing a degree of freedom of design.
- In an aspect, the present invention provides a printed circuit board including: an insulating layer; at least one circuit layer embedded in the insulating layer and having a connection pad that is embedded in the insulating layer such that one side of the connection pad is flush with a surface of the insulating layer; and a insulating materials configured to protect the circuit layer from an external environment and having an opening through which the connection pad is exposed.
- The at least one circuit layer may include a first circuit layer disposed on one side of the insulating layer and a second circuit layer disposed on the other side of the insulating layer, and the insulating layer may include a bump for connecting the first circuit layer with the second circuit layer.
- The one side of the connection pad which is flush with the insulating layer may act as an exposed surface to which an external terminal is bonded.
- The insulating materials may be flush at one side with the insulating layer and may be embedded at the other side in the insulating layer.
- The at least one circuit layer may be formed on the other side of the insulating materials and may be embedded in the insulating layer.
- The at least one circuit layer may be embedded in the insulating materials.
- The insulating layer may include photosensitive insulating material.
- In another aspect, the present invention provides a method of manufacturing a printed circuit board, including: (A) forming at least one circuit layer on a semi-cured insulating layer, the circuit layer having a connection pad; (B) forming insulating materials on the insulating layer, the insulating materials having an opening through which the connection pad is exposed; and (C) pressing and embedding the circuit layer and the insulating materials into the insulating layer.
- The circuit layer may include: (A1) printing a first metal layer with a bump; (A2) applying a semi-cured insulating layer on the first metal layer printed with the bump; and (A3) applying a second metal layer on the insulating layer and patterning the first and second metal layers to form first and second circuit layers each having a connection pad.
- In (C) pressing and embedding the circuit layer and the insulating materials, one side of the connection pad, which is flush with the insulating layer, may act as an exposed surface to which an external terminal is bonded.
- The insulating materials may be flush at one side with the insulating layer and may be embedded at the other side in the insulating layer.
- The at least one circuit layer may be formed on the other side of the insulating materials and may be embedded in the insulating layer.
- The at least one circuit layer may be embedded in the insulating materials.
- In (C) pressing and embedding the circuit layer and the insulating materials, the pressing may be executed while the insulating layer is in a semi-cured state.
- The insulating materials may be made of photosensitive insulating material.
- In the method, (B) forming the insulating materials may include: (B1) applying a photosensitive insulating material on the insulating layer; and (B2) subjecting the photosensitive insulating material to exposure and development processes to form an opening through which the connection pad is exposed.
- The above and other features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1 to 5 are cross-sectional views showing a conventional process of manufacturing a printed circuit board; -
FIG. 6 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention; and -
FIGS. 7 to 14 are cross-sectional views showing a process of manufacturing the printed circuit board shown inFIG. 6 . - Various advantages and features of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings.
- The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to best describe the method he or she knows for carrying out the invention.
- Concerning the designations of reference numerals in this description, it should be noted that the same reference numerals are used throughout the different drawings to designate the same or similar components. Also, in the description of the present invention, when it is considered that the detailed description of a related prior art may obscure the gist of the present invention, such a detailed description is omitted.
- Hereinafter, an embodiment of the present invention will be described in greater detail with reference to the accompanying drawings.
-
FIG. 6 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention. The printedcircuit board 100 according to this embodiment is described below with reference toFIG. 6 . - As shown in
FIG. 6 , the printedcircuit board 100 according to this embodiment comprises aninsulating layer 106,circuit layers insulating layer 106, andinsulating materials insulating layer 106 to protect thecircuit layers - The
circuit layers first circuit layer 102 a is formed on a side of theinsulating layer 106 and thesecond circuit layer 108 a is formed on the other side of theinsulating layer 106. The first andsecond circuit layers bumps 104 passing through theinsulating layer 106. - Connection pads of the
circuit layers insulating layer 106 such that external surfaces of the connection pads are flush with the external surfaces of theinsulating layer 106. Specifically, one side of the connection pad is flush with the external surface of theinsulating layer 106 to offer an exposed surface to which an external connection terminal such as solder ball is bonded, and the other side of the connection pad is embedded in theinsulating layer 106. - The insulating
materials layer 106 such that external sides thereof are flush with the external surfaces of the insulatinglayer 106 in order to protect thefirst circuit layer 102 a and/or thesecond circuit layer 108 a from the external environment. Specifically, one side of each of the insulatingmaterials layer 106, and the other side of the insulating materials is embedded in the insulatinglayer 106. - Furthermore, the circuit layers 102 a, 108 a excluding the connection pads are also embedded in the insulating
layer 106 so as not to be exposed to the outside. In this context, there are two manners in which the circuit layers 102 a, 108 a excluding the connection pads may be embedded in the insulatinglayer 106 such that the external surfaces thereof are disposed on the other sides, i.e., internal surfaces of the insulatingmaterials FIG. 6 ) or they are embedded in the insulatingmaterials FIG. 14 ). In other words, the circuit layers 102 a, 108 a may have any embedded configuration as long as the circuit layers 102 a, 108 a are protected from the external environment by the insulatingmaterials FIG. 14 as being entirely embedded in the insulatingmaterials materials - In this embodiment, the insulating
layers - Although the printed
circuit board 100 is shown inFIG. 6 as having a two-layered structure, this is no more than a single exemplary structure. Accordingly, it will be appreciated that the scope of the present invention may include any of various structures wherein a multilayered buildup layer is formed, a connection pad formed on the outermost layer is embedded in an insulating layer so as to be flush with an outermost insulating layer, and an outermost circuit layer is protected by insulating materials embedded in the outermost insulating layer. -
FIGS. 7 to 14 are cross-sectional views showing a process of manufacturing the printed circuit board shown inFIG. 6 . The process is described below with reference to the drawings. - First, as shown in
FIG. 7 , afirst metal layer 102 is prepared. As thisfirst metal layer 102, a copper layer typically used in the creation of a circuit layer of a printed circuit board may be used. - As shown in
FIG. 8 , bumps 104 are formed on thefirst metal layer 102. - In this regard, the
bumps 104 may be formed using a screen print technology. The screen print technology is executed in a manner such that conductive paste is transferred to the metal layer through openings of a mask. Specifically, openings of the mask are aligned with themetal layer 102, and then conductive paste is applied onto the mask. Subsequently, the conductive paste is wiped using a squeegee, so that the conductive paste is extruded through the openings of the mask and is then transferred to thefirst metal layer 102 into a pattern having the desired shape and height. Of course, it is to be noted that a process of forming thebumps 104 through any other of known technologies also falls within the scope of the present invention. - The conductive paste that constitutes the
bumps 104 may include any conductive material, for example, one selected from among Ag, Pd, Pt, Ni and Ag/Pd. - As shown in
FIG. 9 , an insulatinglayer 106 is applied onto thefirst metal layer 102 on which thebumps 104 were formed. - At this point, the insulating
layer 106 may be configured such that its thickness is less than the height of thebumps 104, and may be formed in a contact or noncontact way. - The process of contact way formation is executed in a manner such that the insulating
layer 106 is applied onto thefirst metal layer 102 on which thebumps 104 were formed. At this point, thebumps 104 may have a rigidity higher than that of the insulatinglayer 106 such that thebumps 104 penetrate through the insulatinglayer 106, and the insulatinglayer 106 may be embodied as a semi-cured prepreg made of thermosetting resin. In this embodiment, since the insulatinglayer 106 has a thickness less than the height of thebumps 104, the bumps protrude from the insulatinglayer 106 by the difference therebetween. - The process of noncontact way formation is executed in a manner such that the metal layer is coated with insulating resin powder using an ink-jet print technology. This process is advantageous in that it minimizes problems such as deformation of the bumps and generation of fine gaps between the
bumps 104 and the insulatinglayer 16 which may otherwise occur in the process of the contact way in which thebumps 104 are under pressure from the insulatinglayer 106 while penetrating through the insulatinglayer 106. - As shown in
FIG. 10 ,second metal layers 108 are applied onto the insulatinglayer 106. - At this point, the
second metal layer 108 is formed in a manner such that the insulatinglayer 106 and thebumps 104 are heated to a temperature higher than a softening temperature thereof under a vacuum condition and are thus semi-cured, and then thesecond metal layer 108 is pressed onto the semi-cured components using a press plate such as a stainless steel plate with a flat surface. By the pressing of thesecond metal layer 108, thesecond metal layer 108 is connected to thebumps 104. - In this regard, since the
second metal layer 108 is pressed by the press plate having a flat surface, the pressure of the press plate is evenly transmitted to the insulatinglayer 106, thus preventing warping or twisting from occurring throughout the substrate. Furthermore, since the pressing is executed under vacuum conditions, there is no occurrence of voids in the insulatinglayer 106. - As shown in
FIG. 11 , thefirst metal layer 102 and thesecond metal layer 108 are patterned to create afirst circuit layer 102 a and asecond circuit layer 108 a each having a connection pad. - At this point, the
first circuit layer 102 a and thesecond circuit layer 108 a may be created using a typical process such as a subtractive process. Specifically, thefirst circuit layer 102 a and thesecond circuit layer 108 a may be created in a manner such that dry films are applied onto thefirst metal layer 102 and thesecond metal layer 108 and then the first andsecond metal layers - In this regard, the
first circuit layer 102 a and thesecond circuit layer 108 a are formed on the semi-curedinsulating layer 106. The reason for this is because thefirst circuit layer 102 a, thesecond circuit layer 108 a and insulatingmaterials layer 106. - As shown in
FIG. 12 , the insulatingmaterials layer 106 is exposed are formed on the insulatinglayer 106. - The insulating
materials material layer 106 and subjecting the photosensitive insulating material to exposure and development processes to form the openings through which the connection pads are exposed. - Furthermore, the insulating
materials layer 106 may have a thickness exceeding that of thefirst circuit layer 102 a and thesecond circuit layer 108 a so as to protect the first andsecond circuit layer - Finally, as shown in
FIG. 13 , the first and second circuit layers 102 a, 108 a including the connection pads and the insulatingmaterials layer 106. - At this point, the embedding procedure is implemented by pressing the first and second circuit layers 102 a, 108 a and the insulating
materials insulating layer 106 using a press plate such as a flat stainless steel plate. - In this regard, the connection pads of the first and second circuit layers 102 a, 108 a are embedded in the insulating
layer 106 such that outer surfaces thereof are flush with the surface of the insulatinglayer 106. In other words, one side of each of the connection pads is flush with the surface of the insulatinglayer 106 and acts as an exposed surface on which an external connection terminal such as a solder ball is bonded, and the other side of the connection pad is embedded in the insulatinglayer 106. - The insulating
materials layer 106 with their external surfaces flush with the surface of the insulatinglayer 106. In other words, one side of each of the insulatingmaterials layer 106, and the other side of the insulating materials is embedded in the insulatinglayer 106. - At this point, the first and second circuit layers 102 a, 108 a excluding the connection pads thereof are embedded in the insulating
layer 106 so as not to be exposed to the external environment. In this procedure, the insulatingmaterials layer 106 against the pressing force so that the first and second circuit layers 102 a, 108 a are disposed on the internal surfaces of the insulatingmaterials materials layer 106 without their initial configuration being changed, as shown inFIG. 14 . Although the first and second circuit layers 102 a, 108 a are shown inFIG. 14 as being entirely embedded in the insulatingmaterials materials - Although the preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that the printed circuit board and the method of manufacturing the same are not limited thereto and that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Accordingly, such modifications, additions and substitutions should also be understood as falling within the scope of the present invention.
Claims (9)
1. A method of manufacturing a printed circuit board, comprising:
forming at least one circuit layer on a semi-cured insulating layer, the circuit layer having a connection pad;
forming insulating materials on the insulating layer, the insulating materials having an opening through which the connection pad is exposed; and
pressing and embedding the circuit layer and the insulating materials into the insulating layer.
2. The method according to claim 1 , wherein forming the at least one circuit layer comprises:
printing a first metal layer with a bump;
applying a semi-cured insulating layer on the first metal layer printed with the bump; and
applying a second metal layer on the insulating layer and patterning the first and second metal layers to form first and second circuit layers each having a connection pad.
3. The method according to claim 1 , wherein, in pressing and embedding the circuit layer and the insulating materials, one side of the connection pad, which is flush with the insulating layer, acts as an exposed surface to which an external terminal is bonded.
4. The method according to claim 1 , wherein the insulating materials are flush at one side with the insulating layer and are embedded at the other side in the insulating layer.
5. The method according to claim 4 , wherein the at least one circuit layer is formed on the other side of the insulating materials and is embedded in the insulating layer.
6. The method according to claim 4 , wherein the at least one circuit layer is embedded in the insulating materials.
7. The method according to claim 1 , wherein, in pressing and embedding the circuit layer and the insulating materials, the pressing is executed while the insulating layer is in a semi-cured state.
8. The method according to claim 1 , wherein the insulating materials are made of photosensitive insulating material.
9. The method according to claim 8 , wherein forming the insulating materials comprise:
applying a photosensitive insulating material on the insulating layer; and
subjecting the photosensitive insulating material to exposure and development processes to form an opening through which the connection pad is exposed.
Priority Applications (1)
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US13/474,388 US20120222299A1 (en) | 2009-01-09 | 2012-05-17 | Method of manufacturing a printed circuit board |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR10-2009-0001971 | 2009-01-09 | ||
KR1020090001971A KR101006603B1 (en) | 2009-01-09 | 2009-01-09 | A printed circuit board and a fabricating method the same |
US12/385,003 US8198550B2 (en) | 2009-01-09 | 2009-03-27 | Printed circuit board and method of manufacturing the same |
US13/474,388 US20120222299A1 (en) | 2009-01-09 | 2012-05-17 | Method of manufacturing a printed circuit board |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/385,003 Division US8198550B2 (en) | 2009-01-09 | 2009-03-27 | Printed circuit board and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
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US20120222299A1 true US20120222299A1 (en) | 2012-09-06 |
Family
ID=42318241
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US12/385,003 Expired - Fee Related US8198550B2 (en) | 2009-01-09 | 2009-03-27 | Printed circuit board and method of manufacturing the same |
US13/474,388 Abandoned US20120222299A1 (en) | 2009-01-09 | 2012-05-17 | Method of manufacturing a printed circuit board |
Family Applications Before (1)
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US12/385,003 Expired - Fee Related US8198550B2 (en) | 2009-01-09 | 2009-03-27 | Printed circuit board and method of manufacturing the same |
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CN110999552A (en) * | 2017-07-28 | 2020-04-10 | Lg伊诺特有限公司 | Printed circuit board |
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KR101006603B1 (en) * | 2009-01-09 | 2011-01-07 | 삼성전기주식회사 | A printed circuit board and a fabricating method the same |
KR101077380B1 (en) * | 2009-07-31 | 2011-10-26 | 삼성전기주식회사 | A printed circuit board and a fabricating method the same |
TWI504320B (en) * | 2014-06-17 | 2015-10-11 | 矽品精密工業股份有限公司 | A circuit structure and fabricating method thereof |
CN105451430A (en) * | 2014-09-02 | 2016-03-30 | 富葵精密组件(深圳)有限公司 | Partially-embedded type circuit structure and manufacturing method thereof |
US11160163B2 (en) * | 2017-11-17 | 2021-10-26 | Texas Instruments Incorporated | Electronic substrate having differential coaxial vias |
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Also Published As
Publication number | Publication date |
---|---|
US8198550B2 (en) | 2012-06-12 |
US20100175915A1 (en) | 2010-07-15 |
KR101006603B1 (en) | 2011-01-07 |
KR20100082600A (en) | 2010-07-19 |
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