CN107678896A - A kind of SRAM type FPGA upset fault injectors and fault filling method - Google Patents
A kind of SRAM type FPGA upset fault injectors and fault filling method Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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Abstract
The present invention provides a kind of SRAM type FPGA upset fault injectors and fault filling method, and wherein host computer instruction slave computer carries out device recognition on chain, obtains device model corresponding to target FPGA device ID；Upper computer selecting working interface, and indicate that slave computer carries out configuration bit by the working interface and flows back to reading；Obtain the original configuration bit stream file of target FPGA device；Host computer instruction slave computer is completed to load the power-up routine of target FPGA device using the original configuration bit stream file of target FPGA device；Host computer is according to direct fault location type, generation upset direct fault location bit stream file；And indicate that slave computer completes the direct fault location to target FPGA device using the direct fault location bit stream file by selected working interface.The present invention can overcome equipment complexity, the cost of existing hardware direct fault location high, and the fault model of existing software fault injection not enough truly causes the shortcomings of test result confidence level is not high after injecting.
Description
Technical field
The present invention relates to, more particularly to a kind of SRAM (Static RAM, SRAM) type FPGA (Field
Programmable Gate Array, field programmable gate array) overturn fault injector and fault filling method.
Background technology
The main of single particle effect includes SEU (Single Event Upset, single-particle inversion), SET (Single
Event Transient, single event transient pulse), SEL (Single Event Latch, locking single particle) etc., wherein SEU
When the most important form of expression.For SRAM type FPGA, due to the SRAM techniques that it is used, single particle effect event easily occurs
Barrier, especially single-particle inversion failure.From the point of view of the ratio of single-particle inversion failure, the proportion shared by configuration memory is maximum,
Secondly be RAM, block RAM and the trigger of LUT types, ratio shared by the single particle effect failure of other (such as SET, SEFI) compared with
Small, the SEU of configuration memory is the main form of expression of FPGA single particle effect failure.
In order that broken down less in the SRAM type FPGA courses of work as far as possible, the method for generally use direct fault location is to FPGA
Function detected.Direct fault location is the behavior by deliberately introducing failure into device, and when observing system has a failure,
To be configured to each configurable position of device, so as to ensure the functional reliability in the FPGA courses of work.
Current FPGA fault filling methods are divided into hardware fault injection, software fault injection and simulated failure and inject 3 kinds：Firmly
Part direct fault location is that failure is directly injected into examining system hardware using physical means, and special event need not be established by having
Hinder injection model, the advantages of experimentation is short, weak point is experimental facilities complexity, and cost is high.Software fault injection is to set
On the fault model of meter, change memory or content of registers carrys out the failure that analog hardware or software occur.Process is relatively easy,
Without complex appts, and hardware will not be caused to damage.Simulated failure injection be direct fault location into hardware simulation model,
With the advantages of optimal observability and controllability, hardware cost is low, shortcoming is to must be set up hardware simulation model, work
Amount is very big.
The content of the invention
The present invention is directed to problem, it is proposed that a kind of SRAM type FPGA upset fault injectors and fault filling method, its energy
Enough overcome equipment complexity, the cost of existing hardware direct fault location high, and the fault model of existing software fault injection is not true enough
Cause the shortcomings of test result confidence level is not high after injecting in fact.
The present invention is achieved through the following technical solutions：
The present invention provides a kind of SRAM type FPGA upsets fault filling method, and it includes：
Step S10, host computer instruction slave computer carry out device recognition on chain, obtain device corresponding to target FPGA device ID
Part model；
Step S20, upper computer selecting working interface, and reading instruction is flowed back to by configuration bit and indicates that slave computer passes through the work
Interface carries out configuration bit and flows back to reading；And the original configuration bit stream file of target FPGA device is obtained according to the feedback of slave computer；Institute
The original configuration bit stream file for stating target FPGA device is that slave computer flows back to the device model carried in reading instruction according to configuration bit
Look for corresponding target FPGA device and communicate what is got with the target FPGA device by working interface；
Step S30, host computer instruction slave computer are completed to target using the original configuration bit stream file of target FPGA device
The power-up routine loading of FPGA device；
Step S40, host computer is according to direct fault location type, generation upset direct fault location bit stream file；And indicate slave computer
Direct fault location using the direct fault location bit stream file by the completion of selected working interface to target FPGA device.
It is highly preferred that the fault filling method also includes：
Step S60, host computer indicate that slave computer carries out configuration memory retaking of a year or grade to target FPGA device, and according to slave computer
Feedback obtain retaking of a year or grade bit stream file, and compare the original configuration bit stream text of the retaking of a year or grade bit stream file and target FPGA device
Whether part, the configuration bit for confirming configuration memory according to comparison result overturn, and the record upset when confirming to overturn
Position.
It is highly preferred that the fault filling method also includes：
Step S70, host computer refer to according to the upturned position of record and the original configuration bit stream file of target FPGA device
Show that slave computer refreshes to the configuration register of target FPGA device.
It is highly preferred that the fault filling method also includes：
Step S80, host computer indicate that slave computer carries out configuration register read-write to target FPGA device, and according to slave computer
Feed back to the configuration information for reading configuration register, and by the original configuration position of its target FPGA device preserved with host computer
Stream file compares, and when confirming to overturn according to comparison result, then notifies slave computer to match somebody with somebody confidence using retaking of a year or grade configuration register
Cease and the configuration register of target FPGA device is refreshed.
It is highly preferred that the direct fault location type includes：It is fixed position, random, random, by turn or circuit by block by region
Netlist.
The present invention also provides a kind of SRAM type FPGA upsets fault injector, and it includes：
Host computer and slave computer；
The host computer and slave computer are in communication with each other based on Ethernet protocol；Working interface is provided with the slave computer,
The working interface communicates with target FPGA device；
The host computer includes device recognition module, device configuration bit stream acquisition module, load-on module, direct fault location mould
Block；
The device recognition module, for indicating that slave computer carries out device recognition on chain, and the mesh fed back according to slave computer
Mark FPGA device ID determines corresponding device model；
The device configures bit stream acquisition module, and for selecting working interface, instruction slave computer passes through the working interface
Configuration bit is carried out to target FPGA device corresponding to device model and flows back to reading；And target FPGA devices are obtained according to the feedback of slave computer
The original configuration bit stream file of part；The slave computer looks for corresponding target FPGA device and by described according to device model
Working interface communicates with the target FPGA device obtains the original configuration bit stream file of target FPGA device；
The load-on module, for notifying slave computer using the original configuration bit stream file of target FPGA device to target
FPGA device enters line program loading, completes the power-up routine loading to target FPGA device；
The direct fault location module, for according to direct fault location type, generation upset direct fault location bit stream file；And indicate
Slave computer completes the direct fault location to target FPGA device by selected working interface using the direct fault location bit stream file.
It is highly preferred that the host computer also includes：Configuration memory retaking of a year or grade module；
The configuration memory retaking of a year or grade module is used to notify slave computer to carry out configuration memory retaking of a year or grade to target FPGA device,
Obtain retaking of a year or grade bit stream file；And the original configuration bit stream file of the retaking of a year or grade bit stream file and target FPGA device is compared, according to
Comparison result confirms whether the configuration bit of configuration memory overturns, and records upturned position when confirming and overturning.
It is highly preferred that the host computer also includes：Configuration memory refresh module；
The configuration memory refresh module be used for according to the configuration memory retaking of a year or grade module record upturned position with
And the original configuration bit stream file of the target FPGA device of the device configuration bit stream acquisition module acquisition, instruction slave computer is to mesh
The configuration register of mark FPGA device is refreshed.
It is highly preferred that the host computer also includes：Configuration register module for reading and writing；
The configuration register module for reading and writing is used to indicate that slave computer carries out configuration register read-write to target FPGA device,
And match somebody with somebody according to the configuration information for feeding back to the configuration register for reading target FPGA device of slave computer, and by itself and the device
The original configuration bit stream file for the target FPGA device that set stream acquisition module obtains compares, and confirms to turn over according to comparison result
When turning, it indicates that the slave computer is entered using the configuration information of retaking of a year or grade configuration register to the configuration register of target FPGA device
Row refreshes.
It is highly preferred that the working interface includes SelectMap interfaces, ICAP interfaces or jtag interface.
The present invention compared with prior art, has the following technical effect that it can be seen from the technical scheme of the invention described above：
1st, the present invention can look for multiple target devices on chain by device recognition, by implementing failure to these devices
Injection can realize the direct fault location of multiple target device, and disclosure satisfy that multiple serial SRAM type FPGA direct fault location；
2nd, the present invention is provided with multiple fault modes, by selecting different fault modes, it is possible to achieve target devices
The direct fault location of different mode；
3rd, the present invention can recognize that failure and record the upturned position of FPGA device by configuration memory retaking of a year or grade, and
Upturned position can be directed to by direct fault location to target FPGA, so as to realize the flexible configuration of upturned position.
4th, the present invention can be directly changed FPGA configuration data, energy by program loading and direct fault location
Enough realize direct fault location and the testing results on chip, can in real simulation space environment FPGA single-particle inversion phenomenon,
Thus the test result that draws is true and reliable and the execution speed of hardware to be significantly faster than fault simulation of the prior art etc. soft
Part simulation velocity, equivalent to a kind of fault filling method of software combination hardware, overcome in the prior art because software fault is noted
The fault model entered is not true enough and causes the shortcomings of test result confidence level is not high after injecting.
5th, the present invention realizes direct fault location by changing FPGA configuration bits, and cost is relatively low, without bearing the extra of costliness
Hardware device, overcome the shortcomings that equipment that hardware fault is injected is complicated, cost is high.
Brief description of the drawings
Fig. 1 is the structural representation of fault injection system of the present invention；
Fig. 2 is the structural representation of host computer in the present invention；
Fig. 3 is the workflow diagram of the fault injector of the present invention.
Embodiment
To make the present invention relatively sharp, the present invention is described in detail below in conjunction with the accompanying drawings.
Embodiment one：
The present embodiment provides a kind of SRAM type FPGA upsets fault injector, and its structure is as shown in figure 1, the fault injector
Including：
Host computer, slave computer.Working interface is provided with slave computer, the failure of the working interface and target FPGA device is noted
Incoming interface communicates.Host computer and slave computer are communicated by Ethernet protocol, are such as communicated using udp protocol, Transmission Control Protocol.
Host computer is used for parameter setting, the generation of configuration bit stream, instruction transmission；Slave computer is responsible for performing associative operation.It is upper
Machine sending device identifies request instruction, the device model according to corresponding to being determined the target FPGA device ID that slave computer feeds back；And
Indicate that slave computer implements direct fault location by direct fault location interface corresponding to target FPGA device model to target FPGA device.Therefore
Hindering injector can be powered by the direct fault location interface power supply of circuit board where target FPGA or external dc.
The host computer of above-mentioned fault injector can be realized by computer.Slave computer can be realized by FPGA.Working interface
Can be SelectMap interfaces (SelectMap interfaces are the bidirectional data ports of one 8), ICAP (Internal
Configuration Access Port, internal configuration access port) interface or JTAG (Joint Test Action
Group, joint test working group, it is a kind of international standard test protocol (IEEE 1149.1 is compatible), is mainly used in chip internal
Test) interface etc., target FPGA configuration memories can be configured from these working interfaces, retaking of a year or grade and direct fault location.Mesh
Mark the FPGA that FPGA device can be Xilinx SRAM techniques.Slave computer power supply can be carried by V5FPGA SelectMap interfaces
For.
Above-mentioned fault injector support Xilinx company Spartan6, Virtex2, Virtex4, Virtex5, Virtex6,
The direct fault location of multiple Series FPGA devices such as Virtex7, Kintex7.
The structure of host computer is as shown in Fig. 2 the host computer includes following module in above-described embodiment one：
Device recognition module, device configuration bit stream acquisition module, load-on module, direct fault location module, configuration memory are returned
Read through model, configuration memory refresh module and configuration register module for reading and writing.
The function of modules and mutual signal transitive relation are as follows：
First, device recognition module
Device recognition module, for indicating that slave computer carries out device recognition on chain, and the target fed back according to slave computer
FPGA device ID determines corresponding device model；
2nd, device configuration bit stream acquisition module
Device configures bit stream acquisition module, and for selecting working interface, instruction slave computer is by the working interface to device
Target FPGA device corresponding to part model carries out configuration bit and flows back to reading；And target FPGA device is obtained according to the feedback of slave computer
Original configuration bit stream file；The slave computer looks for corresponding target FPGA device and by the work according to device model
Interface communicates with the target FPGA device obtains the original configuration bit stream file of target FPGA device；
3rd, load-on module
Load-on module, for notifying slave computer using the original configuration bit stream file of target FPGA device to target FPGA devices
Part enters line program loading, completes the power-up routine loading to target FPGA device；
4th, direct fault location module
Direct fault location module, for according to direct fault location type, generation upset direct fault location bit stream file；And indicate bottom
Machine completes the direct fault location to target FPGA device by selected working interface using the direct fault location bit stream file.
5th, configuration memory retaking of a year or grade module
Configuration memory retaking of a year or grade module, for notifying slave computer to carry out configuration memory retaking of a year or grade to target FPGA device, obtain
Obtain retaking of a year or grade bit stream file；And compare the original configuration bit stream file of the retaking of a year or grade bit stream file and target FPGA device, according to than
Whether the configuration bit of results verification configuration memory is overturn, and upturned position is recorded when confirming and overturning.
6th, configuration memory refresh module
Configuration memory refresh module, for the upturned position recorded according to the configuration memory retaking of a year or grade module and institute
The original configuration bit stream file for the target FPGA device that device configuration bit stream acquisition module obtains is stated, instruction slave computer is to target
The configuration register of FPGA device is refreshed.
7th, configuration register module for reading and writing
Configuration register module for reading and writing, for indicating that slave computer carries out configuration register read-write to target FPGA device, and
Configured according to the configuration information for feeding back to the configuration register for reading target FPGA device of slave computer, and by itself and the device
The original configuration bit stream file for the target FPGA device that bit stream acquisition module obtains compares, and confirms to overturn according to comparison result
When, it indicates that the slave computer is carried out using the configuration information of retaking of a year or grade configuration register to the configuration register of target FPGA device
Refresh.
The workflow of the fault injector of above-described embodiment one as indicated at 3, comprises the following steps：
Step S10, host computer carry out device recognition on chain, obtain device model corresponding to target FPGA device ID.
Step S20, upper computer selecting working interface, issue configuration bit and flow back to reading instruction and flowed back to slave computer, the configuration bit
Carried in reading instruction：Device model and working interface；And the original configuration of target FPGA device is obtained according to the feedback of slave computer
Bit stream file.
Working interface can be ICAP interfaces, SelectMap interfaces or jtag interface, for being carried out to target FPGA device
Load bit stream, direct fault location, configuration memory retaking of a year or grade, configuration memory retaking of a year or grade refreshing, configuration register read-write.
Slave computer parsing configuration bit flows back to reading instruction, obtains device model and working interface, passes through working interface reader
The original configuration bit stream file of target FPGA device corresponding to part model, is sent to host computer, and after this step, host computer obtains mesh
Mark the original configuration bit stream file of FPGA device.
Step S30, host computer notice slave computer is using the original configuration bit stream file of target FPGA device to target FPGA
Device enters line program loading.
In program loading procedure, the original configuration bit stream file of target FPGA device is loaded into target FPGA device,
Complete to load the power-up routine of target FPGA device.
Step S40, host computer carry out direct fault location to target FPGA device.
Host computer is according to direct fault location type, generation upset direct fault location bit stream file；And utilize the direct fault location bit stream
File completes the direct fault location to target FPGA device by slave computer.
Step S50, mode of operation is selected, if mode of operation is configuration memory retaking of a year or grade, perform step S60~S70；If
Mode of operation is configuration register read-write, then performs step S80.
Step S60, configuration memory retaking of a year or grade
Configuration memory retaking of a year or grade is carried out to target FPGA device, obtains retaking of a year or grade bit stream file, and according to retaking of a year or grade bit stream text
The original configuration bit stream file of part and target FPGA device, after confirming whether the configuration bit of configuration memory overturns, and
Upturned position is then recorded when confirming that generation is overturn, then performs step S70；Otherwise flow is terminated.
Step S70, configuration memory retaking of a year or grade refresh
According to the upturned position of record and the original configuration bit stream file of target FPGA device, target FPGA device is entered
The retaking of a year or grade of row configuration memory refreshes.Configuration memory retaking of a year or grade, which refreshes, to be referred to brush the configuration register of target FPGA device
Newly, to eliminate the influence of direct fault location.
Step S80, configuration register read-write
It is capable of the configuration information of retaking of a year or grade configuration register by configuration register read-write process, and itself and host computer is protected
The original configuration bit stream file for the target FPGA device deposited compares, and when confirming to overturn according to comparison result, then utilizes retaking of a year or grade
The configuration information of configuration register refreshes to the configuration register of target FPGA device.
The workflow of above-mentioned steps S10 device recognition, comprises the following steps：
Step S11, host computer sending device recognition command；The request comprising recognition means ID is believed in the device recognition order
Breath.
Host computer packs device recognition order, is then based on Ethernet protocol and the device recognition order is issued into bottom
Machine.
Step S12, host computer monitor whether to receive the confirmation of slave computer feedback.
Step S13, before setting time reaches, host computer receives the confirmation of slave computer feedback, then it is true to parse this
Recognize information, therefrom obtain chain on direct fault location in need target FPGA device ID；This target FPGA device ID can be by device
Part manufacturers set.
In host computer send chain after device recognition order, then start timing and wait the feedback of slave computer.Slave computer receives
After the device recognition order that host computer is sent, device recognition instruction is parsed first, is then communicated, read with FPGA device
The ID of the target FPGA device of direct fault location is needed on chain；Target FPGA device ID is fed back to finally by confirmation
Position machine.
Step S14, host computer match the target FPGA device ID that slave computer feeds back with the device ID storehouses in host computer.
Step S15, the match is successful for host computer, then is somebody's turn to do according to the corresponding relation of target FPGA device ID and device model
Device model corresponding to target FPGA device ID.
Device ID and device model corresponding relation are provided with the device ID storehouses of host computer, host computer matches device ID
In storehouse after existing device ID, then according to device ID and the corresponding relation of device model, it is corresponding to obtain target FPGA device ID
Device model, so far complete device recognition process.The later instruction of device model that device recognition process obtains after terminating
Generated with data and Setting Up Parameters are provided.
The workflow of above-mentioned steps S30 Programs loading, comprises the following steps：
Step S21, upper computer selecting program loading mode.
The original configuration bit stream file of the target FPGA device of acquisition is carried out decomposition packing by step S22, host computer, is formed
Single frames bit stream bag.
The original configuration bit stream file of target FPGA device flows back to reading by above-mentioned steps S20 configuration bits and obtained.
Because network interface issues the form for needing that original configuration bit stream file is decomposed into data frame, needing exist for will be more
Framing bit Traffic Decomposition is multiple single frames bit streams, and is packed, and forms single frames bit stream bag.
Step S23, the single frames bit stream bag after host computer decomposes step S22 are issued to slave computer by network interface；
Step S24, host computer wait the feedback of slave computer.
After single frames bit stream bag is loaded into target FPGA device by slave computer by selected working interface, returns to loading and complete really
Recognize.
Step S25, the loading that host computer receives slave computer return are completed to confirm.So far the journey of target FPGA device is completed
Sequence loads.
The workflow of direct fault location, comprises the following steps in above-mentioned steps S40：
Step S31, upper computer selecting direct fault location type；
The direct fault location type includes：" fixed position ", " random by region ", " random by block ", " by turn " and " circuit network
5 kinds of direct fault location types of table "；
" fixed position " refers to carry out upset direct fault location to a certain fixed bit of target FPGA device；
" random by region " refers to carry out a certain piece of physical configuration region of target FPGA device random upset failure note
Enter；
" random by block " refers to that the configuration resource (such as CLB, clock sources) of according to target FPGA device carries out overturning failure note
Enter；
" by turn " refer to that one in the configuration bit stream to target FPGA device in order is overturn direct fault location by turn；
" circuit meshwork list " is that all effective configuration bits for realizing target FPGA device are found according to circuit meshwork list, is had to these
Imitate configuration bit and carry out direct fault location.
Step S33, host computer is according to selected direct fault location type, generation upset direct fault location bit stream file；
Step S34, host computer carry out decomposition packing by direct fault location bit stream file is overturn, and form single frames bit stream bag, and lead to
Cross direct fault location instruction and be handed down to slave computer.Carried in direct fault location instruction：Single frames bit stream bag, selected working interface, device
Model.
It is identical with the decomposition packing situation of the step S22 in said procedure loading procedure to decompose the idiographic flow of packing, this
In be not described in detail.
Slave computer parsing direct fault location instruction obtains single frames bit stream bag, selected working interface, device model.According to device type
Target FPGA device, target FPGA device is loaded into by selected working interface by single frames bit stream APMB package corresponding to number finding
Afterwards, return to direct fault location and complete instruction.
Step S35, host computer receive injection feedback, confirm that direct fault location is completed.Prepare direct fault location next time.
The workflow of configuration memory retaking of a year or grade, comprises the following steps in above-mentioned steps S60：
Step S41, host computer working interface selected by, configuration memory read-back order is packed, and be handed down to bottom
Machine；Carried in the configuration memory read-back order：Device model, selected working interface.
Step S42, wait and receive the retaking of a year or grade bit stream file of slave computer feedback.
After slave computer receives configuration memory read-back order, the configuration memory read-back order is parsed, identified
Selected working interface and device model, and target FPGA device will be issued by the working interface in read-back order；And pass through this
The configuration bitstream file of configuration register in working interface retaking of a year or grade target FPGA device, and the configuration register that retaking of a year or grade is arrived
Configuration bitstream file (being referred to as retaking of a year or grade bit stream file below) transmits host computer.
Step S43, the original configuration bit stream file and retaking of a year or grade bit stream file of target FPGA device are compared in host computer.
Step S44, host computer is as found the original configuration bit stream file of target FPGA device and the bit of retaking of a year or grade bit stream file
There is difference position, illustrates that target FPGA device there occurs single-particle inversion, then records the upturned position；It is and retaking of a year or grade bit stream file is whole
Direct fault location file is managed into, the direct fault location for same upturned position next time.
After step S44 has found to overturn, then start the flow that follow-up configuration memory retaking of a year or grade refreshes.
The flow that configuration memory refreshes in above-mentioned steps S70, comprises the following steps：
Step S51, host computer find out upset according to upturned position from the original configuration bit stream file of target FPGA device
Frame where position；
The record of upturned position is completed by step S60 configuration memories read-back.Mesh has been obtained in step S20
Mark the original configuration bit stream file of FPGA device.Found out in this step S51 according to the upturned position in original bit stream file
Frame where upturned position.
Frame where upturned position is packed, is sent to by configuration memory refreshing instruction to bottom by step S52, host computer
Machine；Carried in the configuration memory refreshing instruction：Frame, selected working interface, device model where upturned position.
Step S53, wait slave computer feedback.
After slave computer receives the configuration memory refreshing instruction of host computer, parsed, identify selected working interface, device
Part model, according to the sequential of selected working interface from selected working interface, frame where the upturned position is written to target FPGA
In the configuration information of configuration memory in the configuration bitstream file of device.
Slave computer refreshes to host computer feedback upturned position and completed after the write-in of frame where upturned position is completed.
Step S54, host computer receive the feedback of slave computer, prepare the refreshing of next upturned position.
The flow that configuration register is read and write in above-mentioned steps S80, comprises the following steps：
Step S61, host computer pack register read instructions, and slave computer is sent to by network interface；The register read instructions
Include：Working interface, device model.
Step S62, wait and receive the feedback information of slave computer, the feedback information includes：Target FPGA device is posted
Storage configuration information.
After slave computer receives the register read instructions of host computer transmission, device model, working interface are therefrom parsed；Under
Position machine identifies corresponding target FPGA device by device model, and reads the target FPGA device by the working interface
Register configuration information, and it is fed back to host computer.
Step S63, the original configuration position for the target FPGA device that host computer preserves register configuration information and host computer
Stream file is contrasted, and if there is difference, illustrates that target FPGA device there occurs single-particle inversion, then performs step S64；
If the two is identical, illustrate without single-particle inversion occurs, then terminate this register read-write flow.
Step S64, host computer transmitter register write command, included in register write instruction：This register read
Configuration information, selected working interface, device model.
After slave computer receives register write instruction, therefrom parse and identify this register configuration information read, and
By selected working interface, this register configuration information read is written to target FPGA devices corresponding to device model again
In register configuration information in the configuration bitstream file of part, then feedback completes confirmation.
Step S65, receive the completion confirmation of slave computer feedback.So far configuration register read-write process is completed.
The embodiment of the present invention one using FPGA can local retaking of a year or grade and the characteristic that reconfigures, by general operations interface by failure
It is injected into the circuit of target FPGA device, it is equivalent with single-particle inversion, single event function interrupt, single-ion transient state to realize
Restorability single particle effect.Fault filling method has that the cycle is short, cost is low, to advantages such as device not damageds.
In above-described embodiment one, configuration memory retaking of a year or grade module, configuration memory refresh module can not also be included and matched somebody with somebody
Put register module for reading and writing.In this case, the fault injector is merely capable of realizing direct fault location function.
In above-described embodiment one, configuration memory retaking of a year or grade module, configuration memory refresh module can not also be included, it is this
In the case of, the fault injector has lacked the function being modified to the data of configuration memory compared with embodiment one.
Configuration register module for reading and writing, in this case, the fault injector can not also be included in above-described embodiment one
Configuration register read-write capability is lacked compared with embodiment one.
Embodiment two：
The embodiment of the present invention two also provides a kind of SRAM type FPGA upsets fault filling method, and flow and reality is embodied in it
It is identical to apply the workflow of fault injector in example one, is not detailed herein.
In above-described embodiment two, step S60- step S70, in this case, the fault filling method can not also be included
The function that retaking of a year or grade and refreshing are carried out to the configuration memory of target FPGA device is lacked.
Step S80 can not also be included in above-described embodiment two, in this case, the fault filling method has lacked to mesh
The function that the configuration register of mark FPGA device is written and read.
Although the present invention is disclosed as above with preferred embodiment, embodiment is not for limiting the present invention's.Not
In the spirit and scope for departing from the present invention, any equivalence changes done or retouching, the protection domain of the present invention is also belonged to.Cause
This protection scope of the present invention should be using the content that claims hereof is defined as standard.
Claims (10)
1. a kind of SRAM type FPGA overturns fault filling method, it is characterised in that the fault filling method includes：
Step S10, host computer instruction slave computer carry out device recognition on chain, obtain device type corresponding to target FPGA device ID
Number；
Step S20, upper computer selecting working interface, and reading instruction is flowed back to by configuration bit and indicates that slave computer passes through the working interface
Carry out configuration bit and flow back to reading；And the original configuration bit stream file of target FPGA device is obtained according to the feedback of slave computer；The mesh
The original configuration bit stream file of mark FPGA device is that slave computer flows back to the device model carried in reading instruction according to configuration bit and looked for
Communicate what is got to corresponding target FPGA device and by working interface with the target FPGA device；
Step S30, host computer instruction slave computer are completed to target FPGA using the original configuration bit stream file of target FPGA device
The power-up routine loading of device；
Step S40, host computer is according to direct fault location type, generation upset direct fault location bit stream file；And indicate that slave computer utilizes
The direct fault location bit stream file completes the direct fault location to target FPGA device by selected working interface.
2. according to claim 1 overturn fault filling method according to a kind of SRAM type FPGA, it is characterised in that the event
Barrier method for implanting also includes：
Step S60, host computer indicate that slave computer carries out configuration memory retaking of a year or grade to target FPGA device, and according to the anti-of slave computer
Feedback obtains retaking of a year or grade bit stream file, and compares the original configuration bit stream file of the retaking of a year or grade bit stream file and target FPGA device, root
Whether the configuration bit for confirming configuration memory according to comparison result overturns, and records upturned position when confirming and overturning.
3. according to claim 2 overturn fault filling method according to a kind of SRAM type FPGA, it is characterised in that the event
Barrier method for implanting also includes：
Step S70, host computer is according to the upturned position of record and the original configuration bit stream file of target FPGA device, under instruction
Position machine refreshes to the configuration register of target FPGA device.
4. fault filling method is overturn according to a kind of SRAM type FPGA according to claim 1 or 3, it is characterised in that institute
Stating fault filling method also includes：
Step S80, host computer indicate that slave computer carries out configuration register read-write to target FPGA device, and according to the anti-of slave computer
The configuration information for reading configuration register is fed back to, and the original configuration bit stream of its target FPGA device preserved with host computer is literary
Part compares, and when confirming to overturn according to comparison result, then notifies slave computer to utilize the configuration information pair of retaking of a year or grade configuration register
The configuration register of target FPGA device is refreshed.
5. according to claim 1 overturn fault filling method according to a kind of SRAM type FPGA, it is characterised in that the event
Barrier injection type includes：
It is fixed position, random, random, by turn or circuit meshwork list by block by region.
6. a kind of SRAM type FPGA overturns fault injector, it is characterised in that the fault injector includes：
Host computer and slave computer；
The host computer and slave computer are in communication with each other based on Ethernet protocol；Working interface is provided with the slave computer, the work
Make interface to communicate with target FPGA device；
The host computer includes device recognition module, device configuration bit stream acquisition module, load-on module, direct fault location module；
The device recognition module, for indicating that slave computer carries out device recognition on chain, and the target fed back according to slave computer
FPGA device ID determines corresponding device model；
The device configures bit stream acquisition module, and for selecting working interface, instruction slave computer is by the working interface to device
Target FPGA device corresponding to part model carries out configuration bit and flows back to reading；And target FPGA device is obtained according to the feedback of slave computer
Original configuration bit stream file；The slave computer looks for corresponding target FPGA device and by the work according to device model
Interface communicates with the target FPGA device obtains the original configuration bit stream file of target FPGA device；
The load-on module, for notifying slave computer using the original configuration bit stream file of target FPGA device to target FPGA devices
Part enters line program loading, completes the power-up routine loading to target FPGA device；
The direct fault location module, for according to direct fault location type, generation upset direct fault location bit stream file；And indicate bottom
Machine completes the direct fault location to target FPGA device by selected working interface using the direct fault location bit stream file.
7. a kind of SRAM type FPGA upsets fault injector according to claim 6, it is characterised in that the host computer is also
Including：
Configuration memory retaking of a year or grade module；
The configuration memory retaking of a year or grade module is used to notify slave computer to carry out configuration memory retaking of a year or grade to target FPGA device, obtains
Retaking of a year or grade bit stream file；And the original configuration bit stream file of the retaking of a year or grade bit stream file and target FPGA device is compared, according to comparison
Whether the configuration bit of results verification configuration memory overturns, and records upturned position when confirming and overturning.
8. a kind of SRAM type FPGA upsets fault injector according to claim 7, it is characterised in that the host computer is also
Including：
Configuration memory refresh module；
The configuration memory refresh module is used for upturned position and the institute recorded according to the configuration memory retaking of a year or grade module
The original configuration bit stream file for the target FPGA device that device configuration bit stream acquisition module obtains is stated, instruction slave computer is to target
The configuration register of FPGA device is refreshed.
9. a kind of SRAM type FPGA upset fault injectors according to claim 6 or 8, it is characterised in that described upper
Machine also includes：
Configuration register module for reading and writing；
The configuration register module for reading and writing is used to indicate that slave computer carries out target FPGA device configuration register read-write, and root
According to the configuration information for feeding back to the configuration register for reading target FPGA device of slave computer, and by itself and the device configuration bit
The original configuration bit stream file for flowing the target FPGA device that acquisition module obtains compares, and confirms to overturn according to comparison result
When, it indicates that the slave computer is carried out using the configuration information of retaking of a year or grade configuration register to the configuration register of target FPGA device
Refresh.
10. a kind of SRAM type FPGA upsets fault injector according to claim 6, it is characterised in that the work connects
Mouth includes SelectMap interfaces, ICAP interfaces or jtag interface.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108646106A (en) * | 2018-03-14 | 2018-10-12 | 北京航空航天大学 | Miniature ICAP controllers with single-particle inversion direct fault location function |
| CN109858195A (en) * | 2019-03-22 | 2019-06-07 | 中国科学院光电技术研究所 | The on-line simulation system of necessary position single-particle inversion failure on a kind of SRAM type FPGA |
| CN109947609A (en) * | 2019-03-12 | 2019-06-28 | 江南大学 | A kind of software-hardware synergism acceleration method and system towards direct fault location |
| CN112988431A (en) * | 2021-03-18 | 2021-06-18 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113032222A (en) * | 2021-04-13 | 2021-06-25 | 浙江威固信息技术有限责任公司 | Solid state disk resistant to single event functional interruption |
| CN113254288A (en) * | 2021-06-02 | 2021-08-13 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020157071A1 (en) * | 2001-04-13 | 2002-10-24 | Schiefele Walter P. | Method for creating circuit redundancy in programmable logic devices |
| CN102332307A (en) * | 2011-07-28 | 2012-01-25 | 中国空间技术研究院 | Test system and method for single event effect of SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array) |
| CN103198868A (en) * | 2013-04-16 | 2013-07-10 | 西北核技术研究所 | Fault simulation system and fault analysis method for single event upset |
| CN103577643A (en) * | 2013-11-06 | 2014-02-12 | 中国空间技术研究院 | SRAM type FPGA single event upset effect simulation method |
-
2017
- 2017-09-13 CN CN201710823233.5A patent/CN107678896B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020157071A1 (en) * | 2001-04-13 | 2002-10-24 | Schiefele Walter P. | Method for creating circuit redundancy in programmable logic devices |
| CN102332307A (en) * | 2011-07-28 | 2012-01-25 | 中国空间技术研究院 | Test system and method for single event effect of SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array) |
| CN103198868A (en) * | 2013-04-16 | 2013-07-10 | 西北核技术研究所 | Fault simulation system and fault analysis method for single event upset |
| CN103577643A (en) * | 2013-11-06 | 2014-02-12 | 中国空间技术研究院 | SRAM type FPGA single event upset effect simulation method |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108646106A (en) * | 2018-03-14 | 2018-10-12 | 北京航空航天大学 | Miniature ICAP controllers with single-particle inversion direct fault location function |
| CN108646106B (en) * | 2018-03-14 | 2020-06-02 | 北京航空航天大学 | Miniature ICAP controller with single event upset fault injection function |
| CN109947609A (en) * | 2019-03-12 | 2019-06-28 | 江南大学 | A kind of software-hardware synergism acceleration method and system towards direct fault location |
| CN109858195A (en) * | 2019-03-22 | 2019-06-07 | 中国科学院光电技术研究所 | The on-line simulation system of necessary position single-particle inversion failure on a kind of SRAM type FPGA |
| CN109858195B (en) * | 2019-03-22 | 2022-11-08 | 中国科学院光电技术研究所 | Online simulation system for necessary bit single-particle upset fault on SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN112988431A (en) * | 2021-03-18 | 2021-06-18 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN112988431B (en) * | 2021-03-18 | 2022-07-08 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113032222A (en) * | 2021-04-13 | 2021-06-25 | 浙江威固信息技术有限责任公司 | Solid state disk resistant to single event functional interruption |
| CN113032222B (en) * | 2021-04-13 | 2022-10-28 | 浙江威固信息技术有限责任公司 | Solid state disk resistant to single event functional interruption |
| CN113254288A (en) * | 2021-06-02 | 2021-08-13 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
| CN113254288B (en) * | 2021-06-02 | 2021-09-21 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
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