CN103246582B - A kind of FPGA fault detection method and device - Google Patents
A kind of FPGA fault detection method and device Download PDFInfo
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Abstract
The invention provides a kind of FPGA fault detection method, the method includes：Load the fpga chip inspection software previously generating；Using described fpga chip inspection software, fault detect is carried out to fpga chip；Obtain the failure detection result to fpga chip for the fpga chip inspection software, the fpga chip testing result according to obtaining determines the hardware circuit of fault in fpga chip.Present invention also offers a kind of FPGA failure detector.The present invention is capable of detecting when the hardware circuit of fpga chip internal fault, and cost is relatively low.
Description
Technical field
The present invention relates to circuit fault-toleranr technique field, particularly to a kind of field programmable gate array (FPGA) fault
Detection method and device.
Background technology
Fpga chip low cost, has the advantages that the motility of overprogram, is widely used in signal processing, control
System, the field such as data transfer.In the operative scenario of fpga chip, by external environment high temperature, electromagnetic environment is severe, and chip
The factor such as power supply or interface signal overshoot affects, more and more longer with fpga chip run time, the crystal in fpga chip
Pipe circuit etc. can be damaged, and then leads to the depositor (reg) in fpga chip, look-up table (lut), random access memory
(RAM), multiplier (DSP), phaselocked loop (PLL), serial transceiver (SERDES), the hardware circuit such as signal driver (BUFFER)
Faulty resource is so that fpga chip cannot normal work.
After fpga chip internal hardware circuit resource fault, user can not actively perceive, only using this FPGA core
Piece, find this fpga chip cannot normal work when, just can determine that the internal hardware circuit resource fault of this fpga chip.And
And, after finding fpga chip fault, only the fpga chip of fault is returned to manufacturer, by X is shone to fpga chip
Light, just can determine that the hardware circuit resource of fpga chip internal fault, and testing cost is higher.
Content of the invention
In view of this, it is an object of the invention to provide a kind of FPGA fault detection method, the method is capable of detecting when
The hardware circuit resource of fpga chip internal fault, and cost is relatively low.
In order to achieve the above object, the invention provides a kind of FPGA fault detection method, the method includes：
Load the fpga chip inspection software previously generating；
Using described fpga chip inspection software, fault detect is carried out to fpga chip；
Obtain the failure detection result to fpga chip for the fpga chip inspection software, according to the fpga chip detection knot obtaining
Fruit determines the hardware circuit of fault in fpga chip.
Present invention also offers a kind of FPGA failure detector, this device includes：Software loading unit, fault detect list
Unit, fault determining unit；
Described software loading unit, for loading the fpga chip inspection software previously generating；
Described fault detection unit, for carrying out fault detect using described fpga chip inspection software to fpga chip；
Described fault determining unit, for obtaining the failure detection result to fpga chip for the fpga chip inspection software, root
Determine the hardware circuit of fault in fpga chip according to the fpga chip testing result obtaining.
From technical scheme above, in the present invention, treated by previously generating fpga chip inspection software being loaded into
In the fpga chip of detection, using this fpga chip inspection software, fault is carried out to the hardware circuit in fpga chip to be detected
Detection is such that it is able to detect the hardware circuit of fpga chip internal fault, and cost is than relatively low.
Brief description
Fig. 1 is embodiment of the present invention FPGA fault detection method flow chart；
Fig. 2 is the fault detect schematic diagram to DSP for the embodiment of the present invention；
Fig. 3 is the fault detect schematic diagram to RAM for the embodiment of the present invention；
Fig. 4 is the fault detect schematic diagram to PLL for the embodiment of the present invention；
Fig. 5 is the fault detect schematic diagram to BUFFER for the embodiment of the present invention；
Fig. 6 is the fault detect schematic diagram to SERDES for the embodiment of the present invention；
Fig. 7 is the embodiment of the present invention to a line reg in FPGA and lut testing process schematic diagram；
Fig. 8 is the structural representation of embodiment of the present invention FPGA failure detector.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, develop simultaneously embodiment below in conjunction with the accompanying drawings,
Technical scheme is described in detail.
Referring to Fig. 1, Fig. 1 is embodiment of the present invention FPGA fault detection method flow chart, comprises the following steps：
The fpga chip inspection software that step 101, loading previously generate；
Step 102, using described fpga chip inspection software, fault detect is carried out to fpga chip；
Step 103, the acquisition failure detection result to fpga chip for the fpga chip inspection software, according to the FPGA core obtaining
Piece testing result determines the hardware circuit of fault in fpga chip.
In the embodiment of the present invention shown in Fig. 1, before step 101 in addition it is also necessary to first examine to the IOBUS interface of FPGA
Survey, be specifically as follows：First pass through IOBUS interface and write preset data in arbitrary depositor of FPGA, and arbitrary post to described
Data-conversion in storage, then read the data in described arbitrary depositor, the data of reading and preset data are compared,
If the read out data identical with preset data value of the inverted it is determined that IOBUS interface is normal, otherwise, it determines IOBUS interface
Fault.
In the embodiment of the present invention shown in Fig. 1, using described fpga chip inspection software to fpga chip described in step 102
The method carrying out fault detect is specifically as follows：
FPGA is divided into first area and second area.
Generate input signal for the first area block in first area, this input signal is input in first area
Each first area block so that this input signal flow through in this first area block all reg and lut after output signal, according to
The input signal of first area block and output signal judge to whether there is reg or lut of fault in this first area block；For
In two regions, the other hardware circuits in addition to reg and lut generate input signal, this input signal are input to described other hard
Part circuit, judges described other hardware circuit whether fault according to described other input signal of hardware circuits and output signal.
Generate input signal for the first area block in second area, this input signal is input in second area
Each first area block so that this input signal flow through in this first area block all reg and lut after output signal, according to
The input signal of first area block and output signal judge to whether there is reg or lut of fault in this first area block；For
Described other hardware circuit in one region generates input signal, this input signal is input to other hard described in first area
Part circuit, judges described other hardware circuit whether fault according to described other input signal of hardware circuits and output signal.
In fact, fault detect is carried out to fpga chip using described fpga chip inspection software described in step 102
Method can also adopt other multiple methods, for example, FPGA is divided into the region of two or more than two, successively to each area
Hardware circuit in domain carries out fault detect, and finally realizes the fault detect to all hardware circuit in fpga chip；Or,
Select the one or more of regions after dividing, first fault detect is carried out to the hardware circuit in the region selecting, more right
Hardware circuit in remaining region carries out fault detect etc..
Described other hardware circuit can include multiplier DSP.To the reg in each the first area block in first area
When being tested with lut, fault detect can be carried out by each DSP in second area simultaneously.To each in second area
When reg and lut in one region unit is tested, fault detect can be carried out by each DSP in first area simultaneously.
Specifically the embodiment of the present invention shown in Figure 2 to the detection method of each DSP is illustrated to the fault detect of DSP
Figure, data (the first data as shown in Figure 2 and the second data, the also as DSP of or random generation set in advance by two
Input signal) be input to DSP to be tested, compare the output data (namely output signal) of DSP and taking advantage of of two input datas
Long-pending, if identical, illustrate that this DSP is normal, if it is not the same, this DSP fault is then described, the position of this fault DSP can be recorded
Confidence ceases.Here, in FPGA, the quantity of DSP and position are related to the model of specific FPGA, can be based on detected FPGA
Model determine the position of each DSP therein.In the rear end unbound document for detecting FPGA, DSP can be tied to and treat
On the position of test (also will the positional information of each DSP be written in the unbound document of rear end), after being based in detection
In the unbound document of end, the positional information of each DSP of record is detected.Due to being to be detected for each DSP, if
DSP fault is detected, then can be accurately positioned the position of the DSP of fault.
Described other hardware circuit can also include random access memory ram.To each the first area block in first area
In reg and lut when being tested, fault detect can be carried out by each RAM in second area simultaneously.To in second area
When reg and lut in each first area block is tested, fault detect can be carried out by each RAM in first area simultaneously.
Wherein, for the detection method of each RAM embodiment of the present invention shown in Figure 3, the fault detect of RAM is shown
It is intended to, be first randomly generated or preset a data (as shown in the 3rd data in Fig. 3), this data can be one
PN18 data, then according to the order that address is incremented by writes the data to RAM to be tested, this data is being write each RAM full
Afterwards, the order being incremented by according still further to address reads data from this RAM, if there is arbitrary address, is written to the data of this address
Inconsistent with the data reading from this address, then can determine this RAM fault at described arbitrary address, described appointing can be recorded
One address.Detection to RAM can also be pin-pointed to the abort situation of RAM.Here, in FPGA the quantity of RAM and position with
The model of specific FPGA is related, can determine the position of each RAM therein, Ke Yi based on the model of detected FPGA
For detect in the rear end unbound document of FPGA by RAM be tied to position to be tested (also will each RAM positional information
Be written in the unbound document of rear end), in detection can based on rear end unbound document in the positional information of each RAM of record enter
Row detection.
Described other hardware circuit can also include phase-locked loop pll.To in each the first area block in first area
When reg and lut is tested, fault detect can be carried out by each PLL in second area simultaneously.To each in second area
When reg and lut in the block of first area is tested, fault detect can be carried out by each PLL in first area simultaneously.
Wherein, for the detection method of each PLL embodiment of the present invention shown in Figure 4, the fault detect of PLL is shown
It is intended to, the pin input clock of this fpga chip is input to PLL to be tested as the reference clock of PLL, when this PLL divides out
Clock, drives an enumerator 1 using the clock that PLL divides out, also utilizes the pin input clock of fpga chip to drive another simultaneously
One enumerator 2, then compares the value of two enumerators, if identical it is determined that this PLL does not break down, if it is not the same,
Then determine this PLL fault, the Position Number of this PLL can be recorded.Here, in FPGA the quantity of PLL and position with specific
The model of FPGA is related, can determine the position of each PLL therein based on the model of detected FPGA, can be for examining
Survey in the rear end unbound document of FPGA PLL is tied on position to be tested and (also will the positional information of each PLL be written to
In the unbound document of rear end), in detection can based on rear end unbound document in the positional information of each PLL of record examined
Survey.Due to being to be detected for each PLL, and because the position of each PLL is fixed, if PLL fault is detected, can
To be accurately positioned the position of the PLL of fault.
Described other hardware circuit can also include BUFFER.To the reg in each the first area block in first area
When being tested with lut, fault detect can be carried out by each BUFFER in second area simultaneously.To each in second area
When reg and lut in the block of first area is tested, fault detect can be carried out by each BUFFER in first area simultaneously.
Wherein, the fault to BUFFER for the detection method of each BUFFER embodiment of the present invention shown in Figure 5
Detects schematic diagram, the pin input clock of fpga chip is input to BUFFER to be tested as input signal, using this
The output clock of BUFFER drives an enumerator 3, drives another meter using the pin input clock of this fpga chip simultaneously
Number devices 4, compare the value of two enumerators, if identical it is determined that this BUFFER does not break down, if it is not the same, then determining
This BUFFER fault, records the Position Number of this BUFFER.Here, the quantity of BUFFER and position and specific FPGA in FPGA
Model related, the position of each BUFFER therein can be determined based on the model of detected FPGA, can be for examining
Survey in the rear end unbound document of FPGA BUFFER be tied on position to be tested (also will each BUFFER positional information
Be written in the unbound document of rear end), detection when can based on rear end unbound document in record each BUFFER position letter
Breath is detected.Due to being to be detected for each BUFFER, and because the position of each BUFFER is fixed, if detection
To BUFFER fault, then can be accurately positioned the position of the BUFFER of fault.
Described other hardware circuit can also include SERDES.To the reg in each the first area block in first area
When being tested with lut, fault detect can be carried out by each SERDES in second area simultaneously.To each in second area
When reg and lut in the block of first area is tested, fault detect can be carried out by each SERDES in first area simultaneously.
Wherein, the fault to SERDES for the detection method of each SERDES embodiment of the present invention shown in Figure 6
SERDES to be tested is configured to loopback mode by detects schematic diagram in advance, and generates at random or preset a data (such as
Shown in the 4th data in Fig. 6), this data can be PN18 data, by this data input to configured good SERDES loopback mould
The SERDES of formula, the data of this SERDES loopback output and the data inputting this SERDES is compared, if identical, really
This SERDES fixed does not break down, if it is not the same, then determining this SERDES fault, records the Position Number of this SERDES.This
In, in FPGA, the quantity of SERDES and position are related to the model of specific FPGA, can model based on detected FPGA
Determine the position of each SERDES therein, in practical implementations, can incite somebody to action in the rear end unbound document for detecting FPGA
SERDES is tied on position to be tested (also will the positional information of each SERDES be written in the unbound document of rear end),
Can be detected based on the positional information of each SERDES of record in the unbound document of rear end during detection.Due to each SERDES
Position fix, if BUFFER fault is detected, the position of the BUFFER of fault can be accurately positioned.
Described FPGA is divided into first area and the method for second area is specifically as follows：FPGA is divided into upper and lower two
Individual region, corresponds respectively to first area and second area, and wherein, first area includes the 1st row of FPGA to xth row, the
Two regions include remaining (x+1)th row to last column of FPGA, and wherein x is more than 0, and of the total line number less than FPGA
Individual natural number.FPGA two regions in left and right be can also be divided into, first area and second area corresponded respectively to, wherein, the
One region includes the 1st of FPGA and arranges y row, and second area includes the last string that remaining y+1 arranges FPGA, its
Middle y is more than 0, and a natural number of the total columns less than FPGA.Here, described row and column, is all basic with FPGA
Programmable logic cells are unit, and a line refers to the basic programmable logic cells of a line in FPGA, and string refers to string base
This programmable logic cells.Described basic programmable logic cells are made up of reg and lut, according to the difference of FPGA model, base
The composition of reg and lut in this programmable logic cells also differs, and the configuration of relatively more classical basic programmable unit is one
Individual depositor adds a look-up table.
Wherein, when FPGA is divided into upper and lower two regions, described first area block refers to a line of FPGA；As general
When FPGA is divided into two regions in left and right, described first area block refers to the string of FPGA.
It can be seen that, FPGA is divided into behind first area and second area, to the reg in first area and second area and
When lut carries out fault detect, it is merely able to detect the row or column that reg or lut fault occurs, but the row that can not specifically position
Or the concrete abort situation in row, therefore, in addition it is also necessary to further FPGA is divided into the 3rd region and the 4th area in the present embodiment
Domain, and fault detect is carried out to reg and lut in the second area block in the 3rd region and the 4th region, specifically include：
Generate input signal for the second area block in the 3rd region, this input signal is input in the 3rd region
Each second area block so that this input signal flow through in this second area block all reg and lut after output signal, according to
This input signal and output signal judge to whether there is reg or lut of fault in this second area block；
Generate input signal for the second area block in the 4th region, this input signal is input in the 4th region
Each second area block so that this input signal flow through in this second area block all reg and lut after output signal, according to
This input signal and output signal judge to whether there is reg or lut of fault in this second area block.
Here, the 3rd region and four-range divide and should cooperate with the division of first area and second area,
For example, when first area and second area are according to upper and lower two region divisions, the 3rd region and the 4th region should be according to left sides
Right two region divisions, correspondingly, first area block refers to a line in FPGA, and second area block refers to the string in FPGA；
When first area and second area are according to upper and lower two region divisions, the 3rd region and the 4th region should be according to left and right two
Region division, correspondingly, first area block refers to the string in FPGA, and second area block refers to a line in FPGA.
In the present embodiment, identical with the fault detection method of reg with lut of every string to every a line, below with to a line
Illustrate as a example the method that reg and lut is detected.
Referring to Fig. 7, Fig. 7 be the embodiment of the present invention to a line reg in FPGA and lut testing process schematic diagram, as Fig. 7 institute
Show, this row reg and lut is together in series, form test row, then, the input of this row is comprised to input set in advance or random
Many bit serial data stream of the inclusion 0 and 1 generating, this data flow shifts on reg and lut of this row, and finally from from this row
Afterbody reg or lut output stream, then whether the input according to this row and output stream are assured that this row
There is reg or lut of fault.
Here, for a set fpga chip, the position of the basic programmable logic cells of every a line or every string
Fixing, in basic programmable logic cells, the position of reg and lut is also fixed, and therefore, it can according to reg and lut in this row or column
Positional information, in the rear end unbound document for detecting FPGA, reg and lut in this row or column is tied to position to be tested
Put (also will in this row or column the positional information of reg and lut be written in the unbound document of rear end), be based on reg in detection
With positional information in every row or each column for the lut, the method or existing of series connection reg and lut being provided using fpga chip manufacturer
All reg and lut that in technology, the method for other series connection reg and lut is connected in this row or column, then just can be with input traffic
Carry out fault test.
Be can determine according to the method for testing of reg and lut to every a line：
When first area block refers to a line of FPGA, and second area block refers to the string of FPGA, correspondingly,
Input signal is input to each the first area block in first area or second area, so that this input signal stream
Output signal after all reg and lut in this first area block, judges this firstth area according to this input signal and output signal
The method that whether there is reg or lut of fault in the block of domain is specifically as follows：By in the every a line in first area or second area
Reg and lut be concatenated, input includes 0 and 1 many bit serial data stream, and this data flow moves on reg and lut of this row
Position, judges whether the data flow from afterbody reg or lut of this row output is identical with the data flow inputting, if identical,
Determine that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record the line number of this fault；
Input signal is input to each the second area block in the 3rd region or the 4th region, so that this input signal stream
Output signal after all reg and lut in this second area block, judges this secondth area according to this input signal and output signal
The method that whether there is reg or lut of fault in the block of domain is specifically as follows：By in the every string in the 3rd region or the 4th region
Reg and lut be concatenated, input includes 0 and 1 many bit serial data stream, and this data flow moves on reg and lut of this row
Position, judges whether the data flow from the afterbody reg of this row output identical with the data flow inputting, if identical it is determined that
Reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, records the row number of this fault.
When first area block refers to the string of FPGA, and second area block refers to a line of FPGA, correspondingly,
Input signal is input to each the first area block in first area or second area, so that this input signal stream
Output signal after all reg and lut in this first area block, judges this firstth area according to this input signal and output signal
The method that whether there is reg or lut of fault in the block of domain is specifically as follows：By in the every string in first area or second area
Reg and lut be concatenated, input includes 0 and 1 many bit serial data stream, and this data flow moves on reg and lut of this row
Position, judges whether the data flow from afterbody reg or lut of this row output is identical with the data flow inputting, if identical,
Determine that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record the row number of this fault；
Input signal is input to each the second area block in the 3rd region or the 4th region, so that this input signal stream
Output signal after all reg and lut in this second area block, judges this secondth area according to this input signal and output signal
The method that whether there is reg or lut of fault in the block of domain is specifically as follows：By in the every a line in the 3rd region or the 4th region
Reg and lut be concatenated, input includes 0 and 1 many bit serial data stream, and this data flow moves on reg and lut of this row
Position, judges whether the data flow from afterbody reg or lut of this row output is identical with the data flow inputting, if identical,
Determine that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record the row number of this fault.
By the fault detect to the first area block in first area and second area, and to the 3rd region and the 4th
The fault detect of the second area block in region, and then can be accurately true it may be determined that there is the row and column of reg or lut fault
Determine the particular location of reg or lut fault.
Above method of the present invention embodiment is described in detail, present invention also offers a kind of FPGA fault detect
Device.
Referring to Fig. 8, Fig. 8 is the structural representation of embodiment of the present invention FPGA failure detector, and this device includes：Software
Loading unit 810, fault detection unit 820, fault determining unit 830；Wherein,
Software loading unit 810, for loading the fpga chip inspection software previously generating；
Fault detection unit 820, for carrying out fault detect using described fpga chip inspection software to fpga chip；
Fault determining unit 830, for obtaining the failure detection result to fpga chip for the fpga chip inspection software, according to
The fpga chip testing result obtaining determines the hardware circuit of fault in fpga chip.
Described fault detection unit 820 includes：Area division unit 821, signal input unit 822, signal comparing unit
823；Wherein,
Area division unit 821, for being divided into first area and second area by FPGA；
Signal input unit 822, for generating input signal for the first area block in first area, this input is believed
Number it is input to each the first area block in first area, so that this input signal flows through all reg in this first area block
With output signal after lut；For generating input signal for the other hardware circuits in addition to reg and lut in second area, will
This input signal is input to other hardware circuits described in second area, so that described other hardware circuit output signal；For
Generate input signal for the first area block in second area, by this input signal be input in second area each first
Region unit so that this input signal flow through in this first area block all reg and lut after output signal；For for first
Described other hardware circuit in region generates input signal, this input signal is input to described other hard in first area
Part circuit, so that described other hardware circuit output signal；
Signal comparing unit 823, for being input to each first area block in first area according to signal input unit 822
Input signal and this first area block output signal judge in this first area block whether there is fault reg or lut；With
In be input to according to signal input unit 822 in second area described other hardware circuits input signal and second area in
The output signal of described other hardware circuits judge described other hardware circuits in second area whether fault；For basis
Signal input unit 822 is input to the output letter of the input signal of each first area block and this first area block in second area
Number judge in this first area block, to whether there is reg or lut of fault；For being input to first according to signal input unit 822
The output signal of the described other hardware circuit in the input signal and first area of described other hardware circuit in region is sentenced
Described other hardware circuits whether fault in disconnected first area.
Described other hardware circuit includes multiplier DSP；
The input signal that described signal input unit 822 is directed to DSP generation includes the first data and the second data；
Described signal input unit 822, for by described first data and the second data input first area or the secondth area
Each DSP in domain；
Described signal comparing unit 823, in signal input unit 822 by described first data and the second data input
To after each DSP, the data of this DSP output is compared with the product of described first data and the second data, if identical,
Then determining that this DSP does not break down, if it is not the same, then determining this DSP fault, recording the Position Number of this DSP.
Described other hardware circuit includes random access memory ram；
The input signal that described signal input unit 822 is directed to RAM generation is the 3rd data；
Described signal input unit 822, being further used for writing the 3rd data according to the order that address is incremented by expires each
RAM；
Described signal comparing unit 823, for counting the 3rd according to the order that address is incremented by signal input unit 822
According to writing after each RAM full, read data according to the order that address is incremented by from this RAM, if there is arbitrary address, be written to this
The data of address with from the data that this address reads inconsistent it is determined that this RAM in described arbitrary address at fault, and record institute
State arbitrary address.
Described other hardware circuit includes phase-locked loop pll；
The input signal that described signal input unit 822 is directed to PLL generation is the pin input clock of this fpga chip；
Described signal input unit 822, is further used for the pin input clock of this fpga chip as each PLL's
Reference clock is input to this PLL, drives an enumerator using the clock that this PLL divides out；
Described signal comparing unit 823, for making the pin input clock of this fpga chip in signal input unit 822
After reference clock for each PLL is input to this PLL, drive another counting using the pin input clock of this fpga chip
Device, is compared with clock-driven enumerator and the meter driving using the pin input clock of this fpga chip that PLL divides out
Number devices value, if identical it is determined that this PLL does not break down, if it is not the same, then determining this PLL fault, record this PLL
Position Number.
Described other hardware circuit includes BUFFER；
When the input signal that described signal input unit 822 is directed to BUFFER generation is the pin input of this fpga chip
Clock；
Described signal input unit 822, is further used for the pin input clock of this fpga chip as input signal
It is input to each BUFFER, the output clock using this BUFFER drives an enumerator；
Described signal comparing unit 823, for making the pin input clock of this fpga chip in signal input unit 822
It is input to after each BUFFER for input signal, the pin input clock using this fpga chip drives another enumerator, than
Relatively utilize BUFFER's to export clock-driven enumerator and the enumerator driving using the pin input clock of this fpga chip
Value, if identical it is determined that this BUFFER does not break down, if it is not the same, then determining this BUFFER fault, record should
The Position Number of BUFFER.
Described other hardware circuit includes SERDES；
The input signal that described signal input unit 822 is directed to SERDES generation is the 4th data；
Described signal input unit 822, is further used for described 4th data input to configured good SERDES loopback
Each SERDES of pattern；
Described signal comparing unit 823, in signal input unit 822 by described 4th data input to configured good
After each SERDES of SERDES loopback mode, the data of this SERDES loopback output is compared with described 4th data,
If identical it is determined that this SERDES does not break down, if it is not the same, then determining this SERDES fault, record this SERDES
Position Number.
Described area division unit, is further used for for FPGA being divided into the 3rd region and the 4th region；
Described signal input unit 822, is further used for generating input signal for the second area block in the 3rd region,
This input signal is input to each the second area block in the 3rd region, so that this input signal flows through in this second area block
All reg and lut after output signal；It is further used for generating input signal for the second area block in the 4th region, will
This input signal is input to each the second area block in the 4th region, so that this input signal flows through in this second area block
Output signal after all reg and lut；
Described signal comparing unit 823, is further used for being input to each in the 3rd region according to signal input unit 822
The output signal of the input signal of second area block and this second area block judges to whether there is fault in this second area block
Reg or lut；It is further used for being input to the input letter of each second area block in the 4th region according to signal input unit 822
Number and this second area block output signal judge in this second area block whether there is fault reg or lut.
Described first area block is a line in FPGA；Described second area block is the string in FPGA；
To xth row, described second area is that the (x+1)th row of FPGA arrives last to the first row for FPGA for the described first area
OK, wherein x is more than 0, and a natural number of the total line number less than FPGA；
Described 3rd region is that the first row of FPGA arranges to y, and described 4th region is that the y+1 of FPGA arranges FPGA's
Last string；Wherein y is more than 0, and a natural number of the total columns less than FPGA；
Described signal input unit 822 is in each firstth area being input to input signal in first area or second area
Domain block so that this input signal flow through in this first area block all reg and lut after output signal when, be used for：By the firstth area
Reg and lut in every a line in domain or second area is concatenated, and input includes 0 and 1 many bit serial data stream, so that
This data flow shifts on reg and lut of this row, and the afterbody reg in this row or lut output stream；To input
Signal input each second area block in the 3rd region or the 4th region, so that this input signal flows through this second area block
In all reg and lut after output signal when, be used for：By reg and lut in the every string in the 3rd region or the 4th region
It is concatenated, input includes 0 and 1 many bit serial data stream, so that this data flow shifts on reg and lut of this row, and
Afterbody reg or lut output stream in this row；
Described signal comparing unit 823 is being input in first area or second area often according to signal input unit 822
The input signal of individual first area block and the output signal of this first area block judge to whether there is fault in this first area block
Reg or lut when, be used for：Judge the data flow of afterbody reg or lut output and the data inputting this row from every a line
Whether stream identical, if identical it is determined that reg and lut of this row is normal, otherwise, it determines there is reg or lut of fault in this row,
Record the line number of this fault；Each second area in 3rd region or the 4th region is being input to according to signal input unit 822
The output signal of the input signal of block and this second area block judges to whether there is reg or lut of fault in this second area block
When, it is used for：Judge whether the data flow from afterbody reg or lut of every string output is identical with the data flow of this row of input,
If identical it is determined that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record this fault
Row number.
Described fault detection unit 820 software loading unit 810 load the fpga chip inspection software that previously generates it
Before, it is further used for：First pass through IOBUS interface and write preset data in arbitrary depositor of FPGA, and arbitrary post to described
Data-conversion in storage, then read the data in described arbitrary depositor, the data of reading and preset data are compared,
If the read out data identical with preset data value of the inverted it is determined that IOBUS interface is normal, otherwise, it determines IOBUS interface
Fault.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement done etc., should be included within the scope of protection of the invention.
Claims (18)
1. a kind of programming logic gate array FPGA fault detection method is it is characterised in that the method includes：
Load the fpga chip inspection software previously generating；
Using described fpga chip inspection software, fault detect is carried out to fpga chip；
Obtain the failure detection result to fpga chip for the fpga chip inspection software, true according to the fpga chip testing result obtaining
Determine the hardware circuit of fault in fpga chip；
Wherein, carry out fault detect using described fpga chip inspection software to fpga chip to include：
FPGA is divided into first area and second area；
Generate input signal for the first area block in first area, this input signal is input to each in first area
First area block so that this input signal flow through in this first area block all reg and lut after output signal, according to first
The input signal of region unit and output signal judge to whether there is reg or lut of fault in this first area block；For the secondth area
In domain, the other hardware circuits in addition to reg and lut generate input signal, and this input signal is input to described other hardware electricity
Road, judges described other hardware circuit whether fault according to described other input signal of hardware circuits and output signal；
Generate input signal for the first area block in second area, this input signal is input to each in second area
First area block so that this input signal flow through in this first area block all reg and lut after output signal, according to first
The input signal of region unit and output signal judge to whether there is reg or lut of fault in this first area block；For the firstth area
In domain, the other hardware circuits in addition to reg and lut generate input signal, and this input signal is input to described in first area
Whether other hardware circuits, the input signal according to described other hardware circuit and output signal judge described other hardware circuit
Fault.
2. FPGA fault detection method according to claim 1 is it is characterised in that described other hardware circuit includes multiplication
Device DSP；
The input signal generating for DSP includes the first data and the second data；
This input signal is input to other hardware circuits described in first area or second area, according to described other hardware electricity
The input signal on road and output signal judge whether fault includes described other hardware circuit：
By each DSP in described first data and the second data input first area or second area, by the number of this DSP output
Be compared according to the product with described first data and the second data, if identical it is determined that this DSP does not break down, if
Differ it is determined that this DSP fault, record the Position Number of this DSP.
3. FPGA fault detection method according to claim 1 is it is characterised in that described other hardware circuit includes at random
Memory RAM；
It is the 3rd data for the input signal that RAM generates；
According to the order that address is incremented by, the 3rd data is written to each RAM, after the 3rd data is write each RAM full, presses
The order being incremented by according to address reads data from this RAM, if there is arbitrary address, is written to the data of this address and from this ground
Data that location reads inconsistent it is determined that this RAM fault at described arbitrary address, and record described arbitrary address.
4. FPGA fault detection method according to claim 1 is it is characterised in that described other hardware circuit includes locking phase
Ring PLL；
The input signal generating for PLL is the pin input clock of this fpga chip；
The pin input clock of this FPGA is input to this PLL as the reference clock of each PLL, this PLL divides out clock, profit
Drive an enumerator with the clock that PLL divides out, drive another meter using the pin input clock of this fpga chip simultaneously
Number devices, compare the value of two enumerators, if identical it is determined that this PLL does not break down, if it is not the same, then determining this PLL
Fault, records the Position Number of this PLL.
5. FPGA fault detection method according to claim 1 is it is characterised in that described other hardware circuit includes signal
Driver BUFFER；
The input signal generating for BUFFER is the pin input clock of this fpga chip；
The pin input clock of this FPGA is input to each BUFFER as input signal, using the output clock of this BUFFER
Drive an enumerator, drive another enumerator using the pin input clock of this fpga chip simultaneously, compare two countings
The value of device, if identical it is determined that this BUFFER does not break down, if it is not the same, then determining this BUFFER fault, record should
The Position Number of BUFFER.
6. FPGA fault detection method according to claim 1 is it is characterised in that described other hardware circuit includes serial
Transceiver SERDES；
It is the 4th data for the input signal that SERDES generates；
By each SERDES of described 4th data input to configured good SERDES loopback mode, this SERDES loopback is exported
Data be compared with described 4th data, if identical it is determined that this SERDES does not break down, if it is not the same, then
Determine this SERDES fault, record the Position Number of this SERDES.
7. FPGA fault detection method according to claim 1 is it is characterised in that the method further includes：
FPGA is divided into the 3rd region and the 4th region；
Generate input signal for the second area block in the 3rd region, this input signal is input to each in the 3rd region
Second area block so that this input signal flow through in this second area block all reg and lut after output signal, according to second
The input signal of region unit and output signal judge to whether there is reg or lut of fault in this second area block；
Generate input signal for the second area block in the 4th region, this input signal is input to each in the 4th region
Second area block so that input signal flow through in this second area block all reg and lut after output signal, according to the secondth area
The input signal of domain block and output signal judge to whether there is reg or lut of fault in this second area block.
8. FPGA fault detection method according to claim 7 it is characterised in that
Described first area block is a line in FPGA；Described second area block is the string in FPGA；
Described first area be FPGA the first row arrive xth row, described second area for FPGA (x+1)th row to last column,
Wherein x is more than 0, and a natural number of the total line number less than FPGA；
Described 3rd region is that the first row of FPGA arranges to y, and described 4th region is that the y+1 of FPGA arranges the last of FPGA
String；Wherein y is more than 0, and a natural number of the total columns less than FPGA；
Input signal is input to each the first area block in first area or second area, so that this input signal flows through this
Output signal after all reg and lut in the block of first area, the input signal according to this first area block and output signal judge
In this first area block, the method for reg or lut with the presence or absence of fault is：By in the every a line in first area or second area
Reg and lut be concatenated, input includes 0 and 1 many bit serial data stream, and this data flow moves on reg and lut of this row
Position, judges whether the data flow from afterbody reg or lut of this row output is identical with the data flow inputting, if identical,
Determine that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record the line number of this fault；
Input signal is input to each the second area block in the 3rd region or the 4th region, so that this input signal flows through this
Output signal after all reg and lut in second area block, the input signal according to this second area block and output signal judge
In this second area block, the method for reg or lut with the presence or absence of fault is：By in the every string in the 3rd region or the 4th region
Reg and lut be concatenated, input includes 0 and 1 many bit serial data stream, and this data flow moves on reg and lut of this row
Position, judges whether the data flow from afterbody reg or lut of this row output is identical with the data flow inputting, if identical,
Determine that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record the row number of this fault.
9. FPGA fault detection method according to claim 1 it is characterised in that
Before loading the fpga chip inspection software previously generating, further include：Fault inspection is carried out to the IOBUS interface of FPGA
Survey, specially：First pass through IOBUS interface and write preset data in arbitrary depositor of FPGA, and to described arbitrary depositor
In data-conversion, then read the data in described arbitrary depositor, the data of reading and preset data be compared, if
The data reading is identical with preset data value of the inverted it is determined that IOBUS interface is normal, otherwise, it determines the event of IOBUS interface
Barrier.
10. a kind of programming logic gate array FPGA failure detector is it is characterised in that this device includes：Software loads single
Unit, fault detection unit, fault determining unit；
Described software loading unit, for loading the fpga chip inspection software previously generating；
Described fault detection unit, for carrying out fault detect using described fpga chip inspection software to fpga chip；
Described fault determining unit, for obtaining the failure detection result to fpga chip for the fpga chip inspection software, according to obtaining
The fpga chip testing result taking determines the hardware circuit of fault in fpga chip；
Wherein, described fault detection unit includes：
Area division unit, for being divided into first area and second area by FPGA；
Signal input unit, for generating input signal for the first area block in first area, this input signal is inputted
Each first area block in first area, so that after this input signal flows through all reg and lut in this first area block
Output signal；For generating input signal for the other hardware circuits in addition to reg and lut in second area, this is inputted
Signal input is to hardware circuits other described in second area, so that described other hardware circuit output signal；For for
First area block in two regions generates input signal, this input signal is input to each first area in second area
Block so that this input signal flow through in this first area block all reg and lut after output signal；For for first area
In described other hardware circuits generate input signals, by this input signal be input in first area described other hardware electricity
Road, so that described other hardware circuit output signal；
Signal comparing unit, for being input to the input signal of each first area block in first area according to signal input unit
Judge in this first area block, to whether there is reg or lut of fault with the output signal of this first area block；For according to signal
Input block is input to described other hard in the input signal and second area of the described other hardware circuit in second area
The output signal of part circuit judges the described other hardware circuits whether fault in second area；For according to signal input unit
The output signal being input to the input signal of each first area block and this first area block in second area judges this firstth area
Whether there is reg or lut of fault in the block of domain；Described other hard in first area for being input to according to signal input unit
The output signal of the described other hardware circuit in the input signal and first area of part circuit judges described in first area
Other hardware circuits whether fault.
11. FPGA failure detectors according to claim 10 are it is characterised in that described other hardware circuit includes taking advantage of
Musical instruments used in a Buddhist or Taoist mass DSP；
The input signal that described signal input unit is directed to DSP generation includes the first data and the second data；
Described signal input unit, for by described first data and the second data input in first area or second area
Each DSP；
Described signal comparing unit, in signal input unit by described first data and the second data input to each DSP
Afterwards, by this DSP output data be compared with the product of described first data and the second data, if identical it is determined that this
DSP does not break down, if it is not the same, then determining this DSP fault, records the Position Number of this DSP.
12. FPGA failure detectors according to claim 10 it is characterised in that described other hardware circuit include with
Machine memory RAM；
The input signal that described signal input unit is directed to RAM generation is the 3rd data；
Described signal input unit, is further used for, according to the order that address is incremented by, the 3rd data is write each RAM full；
Described signal comparing unit, expires each for writing the 3rd data according to the order that address is incremented by signal input unit
After RAM, read data from this RAM according to the order that address is incremented by, if there is arbitrary address, be written to the data of this address
With from the data that this address reads inconsistent it is determined that this RAM in described arbitrary address at fault, and record described arbitraryly
Location.
13. FPGA failure detectors according to claim 10 are it is characterised in that described other hardware circuit includes locking
Phase ring PLL；
The input signal that described signal input unit is directed to PLL generation is the pin input clock of this FPGA；
Described signal input unit, when being further used for the pin input clock of this fpga chip as the reference of each PLL
Clock is input to this PLL, drives an enumerator using the clock that this PLL divides out；
Described signal comparing unit, in signal input unit using the pin input clock of this fpga chip as each PLL
Reference clock be input to this PLL after, the pin input clock using this fpga chip drives another enumerator, is compared with
Clock-driven enumerator and the value of the enumerator being driven using the pin input clock of this fpga chip that PLL divides out, such as
Really identical it is determined that this PLL does not break down, if it is not the same, then determining this PLL fault, record the Position Number of this PLL.
14. FPGA failure detectors according to claim 10 are it is characterised in that described other hardware circuit includes letter
Number driver BUFFER；
The input signal that described signal input unit is directed to BUFFER generation is the pin input clock of this FPGA；
Described signal input unit, is further used for being input to often the pin input clock of this fpga chip as input signal
Individual BUFFER, the output clock using this BUFFER drives an enumerator；
Described signal comparing unit, in signal input unit using the pin input clock of this fpga chip as input signal
After being input to each BUFFER, the pin input clock using this fpga chip drives another enumerator, is compared with
The value exporting clock-driven enumerator and the enumerator driving using the pin input clock of this fpga chip of BUFFER, such as
Really identical it is determined that this BUFFER does not break down, if it is not the same, then determining this BUFFER fault, record this BUFFER's
Position Number.
15. FPGA failure detectors according to claim 10 are it is characterised in that described other hardware circuit includes going here and there
Row transceiver SERDES；
The input signal that described signal input unit is directed to SERDES generation is the 4th data；
Described signal input unit, is further used for described 4th data input is every to configured good SERDES loopback mode
Individual SERDES；
Described signal comparing unit, in signal input unit by described 4th data input to configured good SERDES loopback
After each SERDES of pattern, the data of this SERDES loopback output is compared with described 4th data, if identical,
Determining that this SERDES does not break down, if it is not the same, then determining this SERDES fault, recording the Position Number of this SERDES.
16. FPGA failure detectors according to claim 10 it is characterised in that
Described area division unit, is further used for for FPGA being divided into the 3rd region and the 4th region；
Described signal input unit, is further used for generating input signal for the second area block in the 3rd region, and this is defeated
Enter signal input each second area block in the 3rd region, so that this input signal flows through owning in this second area block
Output signal after reg and lut；It is further used for generating input signal for the second area block in the 4th region, this is inputted
Signal input each second area block in the 4th region, so that this input signal flows through owning in this second area block
Output signal after reg and lut；
Described signal comparing unit, is further used for being input to each second area block in the 3rd region according to signal input unit
Input signal and this second area block output signal judge in this second area block whether there is fault reg or lut；Enter
One step is used for being input to the input signal of each second area block and this second area in the 4th region according to signal input unit
The output signal of block judges to whether there is reg or lut of fault in this second area block.
17. FPGA failure detectors according to claim 16 it is characterised in that
Described first area block is a line in FPGA；Described second area block is the string in FPGA；
Described first area be FPGA the first row arrive xth row, described second area for FPGA (x+1)th row to last column,
Wherein x is more than 0, and a natural number of the total line number less than FPGA；
Described 3rd region is that the first row of FPGA arranges to y, and described 4th region is that the y+1 of FPGA arranges the last of FPGA
String；Wherein y is more than 0, and a natural number of the total columns less than FPGA；
Described signal input unit in each the first area block being input to input signal in first area or second area, with
When making this input signal flow through output signal after all reg and lut in this first area block, it is used for：By first area or
Reg and lut in every a line in two regions is concatenated, and input includes 0 and 1 many bit serial data stream, so that this data
Stream shifts on reg and lut of this row, and the afterbody reg in this row or lut output stream；Input signal is defeated
Enter each the second area block in the 3rd region or the 4th region, so that this input signal flows through the institute in this second area block
When having output signal after reg and lut, it is used for：Reg and lut in every string in 3rd region or the 4th region is contacted
Come, input includes 0 and 1 many bit serial data stream, so that this data flow shifts on reg and lut of this row, and in this row
Afterbody reg or lut output stream；
Described signal comparing unit is being input to each first area in first area or second area according to signal input unit
The output signal of the input signal of block and this first area block judges to whether there is reg and lut of fault in this first area block
When, it is used for：Judge whether the data flow from afterbody reg or lut of every a line output is identical with the data flow of this row of input,
If identical it is determined that reg and lut of this row is normal, otherwise, it determines this row has reg or lut of fault, record this fault
Line number；Be input to according to signal input unit in the 3rd region or the 4th region the input signal of each second area block and
When the output signal of this second area block judges reg or lut that whether there is fault in this second area block, it is used for：Judge from
Whether the data flow of the afterbody reg or lut output of every string is identical with the data flow inputting this row, if identical, really
Reg and lut of this row fixed is normal, otherwise, it determines this row has reg or lut of fault, records the row number of this fault.
18. FPGA failure detectors according to claim 10 it is characterised in that
Before described fault detection unit loads, in software loading unit, the fpga chip inspection software previously generating, use further
In：First pass through IOBUS interface and write preset data in arbitrary depositor of FPGA, and to the data in described arbitrary depositor
Negate；Read the data in described arbitrary depositor again, the data of reading and preset data be compared, if the read out number
According to identical with preset data value of the inverted it is determined that IOBUS interface is normal, otherwise, it determines IOBUS interface fault.
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| US9652327B2 (en) | 2015-04-17 | 2017-05-16 | Microsoft Technology Licensing, Llc | Restoring service acceleration |
| US10296392B2 (en) | 2015-04-17 | 2019-05-21 | Microsoft Technology Licensing, Llc | Implementing a multi-component service using plural hardware acceleration components |
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| CN105589772A (en) * | 2015-08-07 | 2016-05-18 | 杭州华三通信技术有限公司 | Method and apparatus for detecting logic crash of FPGA chip |
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