CN109947609A - A kind of software-hardware synergism acceleration method and system towards direct fault location - Google Patents
A kind of software-hardware synergism acceleration method and system towards direct fault location Download PDFInfo
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Abstract
The present invention provides a kind of software-hardware synergism acceleration method and system towards direct fault location, belongs to technical field of integrated circuits；It include: S100 according to pumping signal generation random fault sequence；S200 microprocessor group is loaded according to the pumping signal load operating；S300 is according to the random fault sequence by microprocessor group described in direct fault location；S400 is analyzed and is shown the fail result of the microprocessor group.A kind of software-hardware synergism acceleration method and system towards direct fault location provided is provided, software is effectively combined with hardware operation, the time overhead of FPGA hardware emulation platform direct fault location can be substantially reduced, actual scene is effectively simulated, i.e. any moment during microprocessor runs program can all can be carried out direct fault location.
Description
Technical field
The software-hardware synergism acceleration method and system towards direct fault location that the present invention relates to a kind of, and in particular, to a kind of
Software-hardware synergism acceleration method and system towards direct fault location, belongs to technical field of integrated circuits.
Background technique
With the progress of integrated circuit processing technique, supply voltage is continued to decline, working frequency constantly increases, processor pair
Soft error is more and more sensitive, especially in the safety-criticals such as aerospace field, is seriously affected by radiation-induced single particle effect
The reliability of microprocessor, therefore reliability assessment is increasingly becoming most critical in the reliable processor R&D process of high safety
One of link.
Direct fault location has mould as a kind of technological means for being widely used in processor reliability assessment, common method
Quasi- direct fault location, software fault injection and FPGA (Field Programmable Gate Array, field programmable gate array)
Direct fault location.Simulated failure injection uses physical method, such as heavy ion radiation, pin grade to inject, and injects failure, has quick
And the characteristics of close to actual conditions, but this method needs expensive experimental facilities, and cost is excessively high.Software fault injection passes through emulation
Software carry out direct fault location, have the advantages that facilitate it is controllable, but using this method progress a large amount of direct fault locations when, simulation velocity mistake
Slowly, cause time overhead excessive.Traditional FPGA direct fault location generallys use the method for reconfiguring FPGA or modifying source code and carries out
Direct fault location, it is much lower that speed compares that software fault injection is fast, cost compares simulated failure injection, but this method is negative for difference
The processor and different faults model of load require to reconfigure FPGA or modification source code, time overhead are still larger.Therefore,
The time overhead for reducing direct fault location is necessary.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of software-hardware synergisms towards direct fault location to add
Fast method and system, the operation load bank of integrated processor and fault model library in FPGA, on host computer directly at configuration
Operation load and the fault model of device are managed, direct fault location is realized in control, and receives and show direct fault location output as a result, dropping significantly
Also there is good observation property and controllability while low time overhead.
The present invention provides a kind of software-hardware synergism accelerated method towards direct fault location, comprising:
S100 generates random fault sequence according to pumping signal；
S200 microprocessor group is loaded according to the pumping signal load operating；
S300 is according to the random fault sequence by microprocessor group described in direct fault location；
S400 is analyzed and is shown the fail result of the microprocessor group.
Further, before step S200 further include:
S000 establishes the operation load bank for running microprocessor group；Fault model is established according to the failure that will be injected
Library；
S001 is received for generating random fault sequence and loading the pumping signal of the microprocessor group operation load.
Further, the fault model library includes fault injection time, fault type, trouble duration, failure
Position and number of errors.
Further, after step S001 further include:
S002 initializes the register；
Microprocessor group described in S003 saves all value of register at direct fault location moment, then executes S200.
Further, step S300 includes:
S301 starts timing；
S302 judges whether to meet fault injection time, if so, executing step S303；Otherwise, return step S301
S303 is implanted sequentially failure to the second microprocessor by fault injection time according to the random fault sequence, then
It is performed simultaneously step S304 and step S304 '；
The register value at direct fault location moment is re-loaded in the register by the second microprocessor described in S304, with
Step S305 is executed afterwards；
The register value of preservation is re-loaded in the register by S304 ' first microprocessor, then executes step
S305；
S305 judges whether to complete the input of last failure, if so, executing step S400；Otherwise, return step S303.
Further, step S400 includes:
S401 extracts the output result of first microprocessor described in the register and second microprocessor；
S402 is compared analysis to the value of extraction, obtains number of faults and failure modes result；
S403 direct fault location and analysis process terminate；
S404 shows the number of faults and the failure modes result.
A kind of software-hardware synergism acceleration system towards direct fault location, using above-mentioned a kind of towards the soft or hard of direct fault location
Part cooperates with accelerated method, and the environment changing system of the front end exploitation includes:
FPGA hardware emulation platform, for controlling direct fault location module and microprocessor according to pumping signal, and to micro- place
It manages device and executes direct fault location；
The direct fault location module generates random fault sequence for being controlled by FPGA hardware emulation platform, analyzes and defeated
It is out of order and analyzes result；
The microprocessor is loaded for being controlled load operating by FPGA hardware emulation platform, and by the FPGA hardware
Emulation platform injects failure；
Host computer shows the direct fault location module point for providing pumping signal for the FPGA hardware emulation platform
The failure analysis result analysed and exported；
The host computer, is also used to establish the operation load bank for microprocessor operation, and according to will inject
Failure establishes fault model library；
Timer, the timer are used for timing, provide standard for fault injection time.
Further, the fault model library includes fault injection time, fault type, trouble duration, failure
Position and number of errors.
Further, the microprocessor includes first microprocessor and the second microprocessor, wherein
The first microprocessor, for negative according to the load of load running library and the operation of second microprocessor load
Carry identical operation load, the references object as second microprocessor；
Second microprocessor, for being loaded according to load running library load operating, the experiment pair as direct fault location
As.
Compared with prior art, the present invention is with following the utility model has the advantages that provided by the invention a kind of towards direct fault location
Software-hardware synergism acceleration method and system, software is effectively combined with hardware operation, by the operation for establishing a processor
Load bank and fault model library so that every time carry out direct fault location when directly on host computer config failure model and microprocessor
Operation load, and FPGA hardware emulation platform is sent in the form of excitation, and it is flat to reconfigure FPGA hardware emulation
Platform or modification source code, can substantially reduce the time overhead of FPGA hardware emulation platform direct fault location.In addition, the present invention is counting
When device direct fault location is carried out to the second microprocessor when meeting the fault injection time parameter configured in fault model, effectively mould
Actual scene is intended, i.e. any moment during microprocessor runs program can all can be carried out direct fault location.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of flow chart of an embodiment of software-hardware synergism accelerated method towards direct fault location of the invention.
Fig. 2 is a kind of process of another embodiment of software-hardware synergism accelerated method towards direct fault location of the invention
Figure.
Fig. 3 is a kind of process of another embodiment of software-hardware synergism accelerated method towards direct fault location of the invention
Figure.
Fig. 4 is a kind of process of another embodiment of software-hardware synergism accelerated method towards direct fault location of the invention
Figure.
Fig. 5 is a kind of structural schematic diagram of software-hardware synergism acceleration system towards direct fault location of the invention.
Fig. 6 is that a kind of FPGA hardware emulation platform of software-hardware synergism acceleration system towards direct fault location of the invention shows
It is intended to.
Fig. 7 is the state transition diagram of direct fault location module.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Combined with specific embodiments below to being originally described in detail.Following embodiment will be helpful to those skilled in the art
This is further understood, but does not limit this in any form.It should be pointed out that those skilled in the art,
Under the premise of not departing from this design, various modifications and improvements can be made.These belong to this protection scope.
Shown in referring to Fig.1, an implementation of the present invention provides a kind of software-hardware synergism accelerated method towards direct fault location
Example, comprising:
S100 generates random fault sequence according to pumping signal；
S200 microprocessor group is loaded according to pumping signal load operating；
S300 is according to random fault sequence by direct fault location microprocessor group；
The fail result of S400 analysis and display microprocessor group.
Specifically, pumping signal is issued by host computer, received by FPGA hardware emulation platform, FPGA hardware emulation platform root
According to the running of pumping signal control direct fault location module and microprocessor group, and failure analysis result is fed back by communication bus
To host computer, by the fail result of host computer display microprocessor group.
Referring to an implementation of shown in Fig. 2, the present invention provides a kind of software-hardware synergism accelerated method towards direct fault location
Example, comprising:
S000 establishes the operation load bank for running microprocessor group；Fault model is established according to the failure that will be injected
Library；
S001 is received for generating random fault sequence and loading the pumping signal of microprocessor group operation load；
S002 initialization register；
S003 microprocessor group saves all value of register at direct fault location moment, then executes S200；
S100 generates random fault sequence according to pumping signal；
S200 microprocessor group is loaded according to pumping signal load operating；
S300 is according to random fault sequence by direct fault location microprocessor group；
The fail result of S400 analysis and display microprocessor group.
Specifically, host computer generates ratio by carrying out RTL modeling to operation load bank, microprocessor, direct fault location module
Special stream file realizes and loads to the power-up routine of FPGA hardware emulation platform that host computer provides sharp for FPGA hardware emulation platform
Signal is encouraged, receive and shows failure analysis result.The method of the present invention be by microprocessor after direct fault location again to deposit
All value of register is loaded in device to judge number of faults and fault type, therefore when testing process starts, will need to first be posted
All values of storage are stored in microprocessor group, then initialization register, it is enabled to carry out the preparation for being reloaded value.Fortune
Row load bank provides different operation programs for microprocessor.
Referring to an implementation of shown in Fig. 3, the present invention provides a kind of software-hardware synergism accelerated method towards direct fault location
Example, comprising:
S000 establishes the operation load bank for running microprocessor group；Fault model is established according to the failure that will be injected
Library；
S001 is received for generating random fault sequence and loading the pumping signal of microprocessor group operation load；
S002 initialization register；
S003 microprocessor group saves all value of register at direct fault location moment, then executes S200；
S100 generates random fault sequence according to pumping signal；
S200 microprocessor group is loaded according to pumping signal load operating；
S301 starts timing；
S302 judges whether to meet fault injection time, if so, executing step S303；Otherwise, return step S301；
S303 is implanted sequentially failure to the second microprocessor by fault injection time according to random fault sequence, then simultaneously
Execute step S304 and step S304 '；
The register value at direct fault location moment is re-loaded in register by the second microprocessor of S304, then executes step
Rapid S305；
The register value of preservation is re-loaded in register by S304 ' first microprocessor, then executes step S305；
S305 judges whether to complete the input of last failure, if so, executing step S400；Otherwise, return step S303；
The fail result of S400 analysis and display microprocessor group.
Specifically, each failure has corresponding injection length in random fault sequence, direct fault location module is initially entered
When direct fault location state, two microprocessors start load operating load, counter starts timing；When counter meets failure
When injection length, direct fault location module successively executes direct fault location, stress state, i.e. direct fault location module control is in corresponding position
It sets and direct fault location is carried out to the second microprocessor, after the completion of direct fault location, again by the register value at the direct fault location moment
It is loaded into register, actual scene can be simulated in this way, is i.e. any moment during microprocessor runs program is ok
Inject failure.
Referring to an implementation of shown in Fig. 4, the present invention provides a kind of software-hardware synergism accelerated method towards direct fault location
Example, comprising:
S000 establishes the operation load bank for running microprocessor group；Fault model is established according to the failure that will be injected
Library；
S001 is received for generating random fault sequence and loading the pumping signal of microprocessor group operation load；
S002 initialization register；
S003 microprocessor group saves all value of register at direct fault location moment, then executes S200；
S100 generates random fault sequence according to pumping signal；
S200 microprocessor group is loaded according to pumping signal load operating；
S301 starts timing；
S302 judges whether to meet fault injection time, if so, executing step S303；Otherwise, return step S301
S303 is implanted sequentially failure to the second microprocessor by fault injection time according to random fault sequence；
The register value at direct fault location moment is re-loaded in register by the second microprocessor of S304；
The register value of preservation is re-loaded in register by S304 ' first microprocessor；
S305 judges whether to complete the input of last failure, if so, executing step S401；Otherwise, return step S303.
S401 extracts the output result of first microprocessor and the second microprocessor in register；
S402 is compared analysis to the value of extraction, obtains number of faults and failure modes result；
S403 direct fault location and analysis process terminate；
S404 shows number of faults and failure modes result.
Specifically, direct fault location module executes comparative analysis state, control event when direct fault location goes to last
Hinder analyzer comparative analysis two microprocessors output as a result, and after saving failure modes result, into end state,
All number of faults and failure modes result are exported and shown to host computer by communication bus.
Referring to shown in Fig. 5-Fig. 7, using a kind of software-hardware synergism towards direct fault location of preceding claim embodiment
Accelerated method, the software-hardware synergism acceleration system towards direct fault location that the invention also provides a kind of, comprising:
FPGA hardware emulation platform, for controlling direct fault location module and microprocessor group according to pumping signal, and to micro-
Processor group executes direct fault location；
Direct fault location module generates random fault sequence for being controlled by FPGA hardware emulation platform, analyzes and exports event
Barrier analysis result；
Microprocessor group loads for being controlled load operating by FPGA hardware emulation platform, and is emulated and put down by FPGA hardware
Platform injects failure, and microprocessor group includes first microprocessor and the second microprocessor；
Host computer, for providing pumping signal for FPGA hardware emulation platform, showing direct fault location module analysis and exporting
Failure analysis result.
Referring to shown in Fig. 6, in the preferred embodiment of this part, direct fault location module include fault model library, error listing,
Fault analyzer, direct fault location manager；
Fault model library provides different fault models for error listing；
Error listing generates corresponding failure sequence according to the fault model of upper computer selecting；
Fault analyzer is analyzed and compares the output of two microprocessors as a result, classifying to failure, and exports failure
Classification results；
As shown in fig. 7, nucleus module of the direct fault location manager as direct fault location module, mainly passes through 7 state realities
Now to the control of direct fault location, each execution state is as follows:
(1) it initializes: after FPGA hardware emulation platform receives the direct fault location start command on communication bus,
The state of corresponding registers is initialized, or resets or set number；
(2) it interrupts: after FPGA hardware emulation platform receives the direct fault location interruptive command on communication bus, directly
It taps into end state；
(3) save: after the completion of initialization, two microprocessors setting all registers at the direct fault location moment
All save；
(4) failure note direct fault location: is carried out to the second microprocessor in corresponding position according to the failure sequence generated
Enter；
(5) it loads: after the completion of direct fault location, being filled with the microprocessor of failure for the register at the direct fault location moment
Value is re-loaded in register, in addition, when last for detecting direct fault location, into comparative analysis state；
(6) comparative analysis: when completing last direct fault location and after loaded all registers, when postponing certain
Between, by the output results of two microprocessors be compared analysis, and save the classification results of failure；
(7) terminate: all number of faults and failure modes result are transferred on communication bus.
Referring to shown in Fig. 6, in the preferred embodiment of this part, host computer is also used to establish for the operation of microprocessor group
Load bank is run, and fault model library is established according to the failure that will be injected.
In the preferred embodiment of this part, fault model library include fault injection time, fault type, failure continue when
Between, abort situation and number of errors etc..
Referring to shown in Fig. 6, in the preferred embodiment of this part, microprocessor group includes first microprocessor and second micro- place
Manage device, wherein
First microprocessor, it is identical for being loaded according to the load of load running library with the operation that the second microprocessor loads
Operation load, the references object as the second microprocessor；
Second microprocessor, for being loaded according to load running library load operating, the experimental subjects as direct fault location.
In the preferred embodiment of this part, timer, timer is used for timing, provides standard for fault injection time.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring substantive content of the invention.
Claims (10)
1. a kind of software-hardware synergism accelerated method towards direct fault location characterized by comprising
S100 generates random fault sequence according to pumping signal；
S200 microprocessor group is loaded according to the pumping signal load operating；
S300 is according to the random fault sequence by microprocessor group described in direct fault location；
S400 is analyzed and is shown the fail result of the microprocessor group.
2. a kind of software-hardware synergism accelerated method towards direct fault location according to claim 1, which is characterized in that
Before step S200 further include:
S000 establishes the operation load bank for running microprocessor group；Fault model library is established according to the failure that will be injected；
S001 is received for generating random fault sequence and loading the pumping signal of the microprocessor group operation load.
3. a kind of software-hardware synergism accelerated method towards direct fault location according to claim 2, which is characterized in that described
Fault model library include fault injection time, fault type, trouble duration, abort situation and number of errors.
4. a kind of software-hardware synergism accelerated method towards direct fault location according to claim 2, which is characterized in that step
After S001 further include:
S002 initializes the register；
Microprocessor group described in S003 saves all value of register at direct fault location moment, then executes S200.
5. a kind of software-hardware synergism accelerated method towards direct fault location according to claim 1, which is characterized in that step
S300 includes:
S301 starts timing；
S302 judges whether to meet fault injection time, if so, executing step S303；Otherwise, return step S301
S303 is implanted sequentially failure to the second microprocessor by fault injection time according to the random fault sequence, then simultaneously
Execute step S304 and step S304 '；
The register value at direct fault location moment is re-loaded in the register by the second microprocessor described in S304, is then held
Row step S305；
The register value of preservation is re-loaded in the register by S304 ' first microprocessor, then executes step S305；
S305 judges whether to complete the input of last failure, if so, executing step S401；Otherwise, return step S303.
6. according to a kind of software-hardware synergism accelerated method towards direct fault location according to claim 1, which is characterized in that
Step S400 includes:
S401 extracts the output result of first microprocessor described in the register and second microprocessor；
S402 is compared analysis to the value of extraction, obtains number of faults and failure modes result；
S403 direct fault location and analysis process terminate；
S404 shows the number of faults and the failure modes result.
7. a kind of software-hardware synergism acceleration system towards direct fault location, which is characterized in that apply claim 1-6 any one
A kind of software-hardware synergism accelerated method towards direct fault location, the software-hardware synergism towards direct fault location accelerate system
System, comprising:
FPGA hardware emulation platform, for controlling direct fault location module and microprocessor according to pumping signal, and to microprocessor
Execute direct fault location；
The direct fault location module generates random fault sequence for being controlled by FPGA hardware emulation platform, analyzes and exports event
Barrier analysis result；
The microprocessor group is loaded for being controlled load operating by FPGA hardware emulation platform, and is imitated by the FPGA hardware
True platform injects failure；
Host computer shows the direct fault location module analysis simultaneously for providing pumping signal for the FPGA hardware emulation platform
The failure analysis result of output；
The host computer is also used to establish the operation load bank for microprocessor operation, and according to the failure that will be injected
Establish fault model library；
Timer, the timer are used for timing, provide standard for fault injection time.
8. a kind of software-hardware synergism acceleration system towards direct fault location according to claim 7, which is characterized in that described
Fault model library include fault injection time, fault type, trouble duration, abort situation and number of errors.
9. a kind of software-hardware synergism acceleration system towards direct fault location according to claim 8, which is characterized in that described
Fault model library is for providing different fault models for error listing.
10. a kind of software-hardware synergism acceleration system towards direct fault location according to claim 7, which is characterized in that institute
Stating microprocessor group includes first microprocessor and the second microprocessor, wherein
The first microprocessor, for loading phase according to the load of load running library and the operation that second microprocessor loads
Same operation load, the references object as second microprocessor；
Second microprocessor, for being loaded according to load running library load operating, the experimental subjects as direct fault location.
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