CN107678731A - A kind of high frequency asynchronous randomizer based on FPGA - Google Patents
A kind of high frequency asynchronous randomizer based on FPGA Download PDFInfo
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- CN107678731A CN107678731A CN201711080455.9A CN201711080455A CN107678731A CN 107678731 A CN107678731 A CN 107678731A CN 201711080455 A CN201711080455 A CN 201711080455A CN 107678731 A CN107678731 A CN 107678731A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
Abstract
The invention belongs to technical field of data processing, discloses a kind of high frequency asynchronous randomizer based on FPGA, is provided with sampling module, is sampled by Click circuits, improves frequency caused by random number；Dither signal is sampled as stochastic source by sampling pulse to it caused by real random number generator using multigroup isometric phase inverter oscillating loop phase XOR；Pseudorandom number generator enters line disturbance using true random number to it, strengthens the randomness of pseudo random number with this；User according to oneself need true random number and pseudo random number are selected by true and false random number selecting module.Digital circuit clock jitter and phase drift working mechanism are utilized using one kind, stochastic source is used as using multigroup phase inverter oscillating loop.Output can arbitrarily be selected is true random number or pseudo random number, significantly facilitates the operation of user, makes that the function of system is more perfect, and operability is stronger.
Description
Technical field
The invention belongs to technical field of data processing, more particularly to a kind of high frequency asynchronous randomizer based on FPGA
Background technology
With the rapid development of computer network and the communication technology, the security of information data is more and more important, password skill
Art has also obtained rapid development therewith as the core technology of information security.Random number can be used for serving as in cryptographic algorithm
Key, in the authentication protocol as challenge data, random filler or random mask etc. are used as in some specific occasions.
Not only have a wide range of applications in information security field randomizer, be statistically also widely used.Cause
This, the design of randomizer has highly important meaning.
At present, mainly there are three kinds of schemes in the design of real random number generator：Directly amplify method, discrete event chaos
Method, oscillator sample method.The above two are mainly used in the unit design of customization, are all limited by device technology technology, nothing
Method is across process reuse.In addition, the speed ratio that the randomizer come out using these conceptual designs generates random number is relatively low, one
As only tens Kb/s.If use it for information security field, it will the efficiency of serious limitation secure communication, it is logical safety will to be turned into
The bottleneck of letter.And oscillator sample method is used, do not need to use common logic unit only, hardware spending is small, and generates
The efficiency high of random number.
The content of the invention
The problem of existing for prior art, the invention provides a kind of high frequency asynchronous random number generation based on FPGA
Device.
The present invention is achieved in that
A kind of high frequency asynchronous randomizer based on FPGA is provided with sampling module, including：
Sampling module is sampled by Click circuits, improves frequency caused by random number；
Real random number generator is connected with sampling module, with caused by multigroup isometric phase inverter oscillating loop phase XOR
Dither signal is sampled as stochastic source by sampling pulse to it；
Pseudorandom number generator is connected to form by LFSR and real random number generator, using true random number to LFSR
Output its enter line disturbance, strengthen the randomness of pseudo random number with this；
True and false random number selecting module, is connected with real random number generator module and pseudorandom number generator module respectively
Connect, true random number and pseudo random number are selected according to the needs of oneself.
Further, the Click circuits have two pairs of I/O nodes, and a pair of of left side in_R/in_A is used for and left
Click is communicated, and another pair out_R/out_A of right is used for and the Click of right is communicated.
Further, the real random number generator, can when the loop that 2N+1 phase inverter composition closes inside FPGA
To obtain the oscillator signal of a high frequency.
Further, the high-frequency generator is started by pulse enable signals.
Further, the linear feedback shift register is made up of shift register and feedback function two parts.
Advantages of the present invention and good effect are：
The high frequency asynchronous randomizer based on FPGA utilizes digital circuit clock jitter and phase using one kind
Drift working mechanism, stochastic source is used as using multigroup phase inverter oscillating loop.Pseudorandom number generator is designed based on LSFR, is made
By the use of real random number generator as its disruption and recovery, produced by multiple LSFR, can be produced when each sampled signal arrives simultaneously
The numerical value of more bits.The design, as its sampled signal, can improve system frequency using Click circuits.And devise one
Individual true and false random number selection circuit, can arbitrarily select output is true random number or pseudo random number, the user significantly facilitated
Operation, make that the function of system is more perfect, and operability is stronger.
The shortcomings that compared to prior art and deficiency, the invention has the advantages that：
1. employing asynchronous Click circuit modules carrys out drive circuit, so as to greatly improve frequency caused by random number.
Because the inherent clock frequency of Xilinx vc707 development platforms is 200MHz, carry out drive circuit according to synchronised clock, at random
It is 200MHz that number highest, which produces frequency, and this secondary design produces frequency using asynchronous Click circuit modules come drive circuit, random number
Rate can reach 289MHz.
2nd, true and false random number selecting module is employed to control the generation of true and false random number, so can be according to the need of user
Ask to export true random number or pseudo random number, so as to greatly meet the demand of user.
3rd, be not to be realized using algorithm in the design of pseudorandom number generator, but using real random number generator come
Line disturbance is entered to pseudo random number, the complexity that not only avoid algorithm and the correlation reduction for causing pseudo random number.
Brief description of the drawings
Fig. 1 is the system diagram of the high frequency asynchronous randomizer provided in an embodiment of the present invention based on FPGA；
Fig. 2 is Click circuit diagrams provided in an embodiment of the present invention；
Fig. 3 is the oscillogram of Click circuits provided in an embodiment of the present invention；
Fig. 4 is high-frequency generator pulse signal figure provided in an embodiment of the present invention；
Fig. 5 is acquisition dither signal figure provided in an embodiment of the present invention；
Fig. 6 is true random source design module map provided in an embodiment of the present invention；
Fig. 7 is feedback shift register FSR figures provided in an embodiment of the present invention；
Fig. 8 is linear feedback shift register LFSR figures provided in an embodiment of the present invention；
Fig. 9 is high-speed pseudo-random number generator schematic diagram provided in an embodiment of the present invention；
Figure 10 is Select circuit theory diagrams provided in an embodiment of the present invention；
Figure 11 is Simulation results figure provided in an embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to embodiments, to the present invention
It is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to
Limit the present invention.
1 the application principle of the present invention is further described to accompanying drawing 11 and specific embodiment below in conjunction with the accompanying drawings.
High frequency asynchronous randomizer provided in an embodiment of the present invention based on FPGA includes sampling module, true random number
Generator module, pseudorandom number generator module and true and false random number selecting module.
As shown in Figure 1.Wherein：
Sampling module is sampled using Click circuits, and this module can improve frequency caused by random number；
Real random number generator is designed based on gate delay difference, with multigroup isometric phase inverter oscillating loop phase
Then dither signal caused by XOR is sampled as stochastic source by sampling pulse to it；
Pseudorandom number generator is entered using a kind of pseudorandom number generator based on LFSR using true random number to it
Line disturbance, strengthen the randomness of pseudo random number with this；
For true and false random number selecting module for meeting that user's needs are designed, user can be according to the needs of oneself
To select true random number and pseudo random number.
Sampling pulse is produced using Click circuits, sample frequency can be improved using Click circuits.The asynchronous controls of Click
The schematic diagram of circuit processed as shown in Fig. 2 have two pairs of input/output to realize " bound data binding " two-phase carrying out shake communication agreement,
A pair of the left side (in_R/in_A) is used for and the Click of left is communicated, and another pair (out_R/out_A) of right is used for and right
Click communication.When inputting handshake request signal in_R rises, uprise signal by XOR gate, it is then defeated with same OR gate
The signal gone out pass through with door and, trigger FF is worked, while have activated local Fire, the value of then trigger output will point
Supplementary biography is to in_A and out_R.Wherein in_A shows a Click circuit in response, and out_R represents to carry out shaking hands next time
Request.Then the Click modules of left and right two-stage will reset this Click in_A and out_R, while eliminate local Fire.
Local Fire carries out data processing within the period activated and cancelled.
Single click modules are used in this secondary design, different vibrations is inputted respectively in input in_R and out_A
Signal, so as to be Click Module cycles output fire signals, in the rising edge of fire signals to true random number and pseudo random number
Sampled.
Click circuits and its oscillogram as shown in figure 3,
Real random number generator, when the loop that 2N+1 phase inverter composition closes, can obtain one inside FPGA
The running clock of high frequency, the cycle of the clock signal is relevant with the number of gate delay and phase inverter, and unrelated with external signal.
High-frequency generator by pulse enable signals as shown in figure 4, start the high-frequency generator.Because each door prolongs
When the time difference, the output time of two groups of oscillation rings of equal length is also different.If by the group 1 and group of equal length
The output phase XOR of 2 two groups of oscillation rings can be obtained by one group of new waveform being made up of random signal, as shown in Figure 5.
The design of true random source module is as shown in Figure 6.
Linear feedback shift register is made up of two parts：Shift register and feedback function.
As shown in Figure 7.Shift register is a bit sequence, when generating a position every time, all positions in shift register
One is all moved to right, the position of removal is exactly result, and the leftmost bit vacated carries out what computing obtained by feedback function to other all
As a result fill.When feedback function is linear function, this feedback shift register FSR is exactly LFSR.One is simplest,
The most frequently used, be easiest to realize LFSR be feedback function be shift register in some simple XORs in position, as shown in Figure 8.
The position for participating in XOR is referred to as tap.One n bit lengths LFSR is up to 2nIndividual internal state, its cycle are up to
2n- 1, because all-zero state is self-closing.
High-speed pseudo-random number generator DPFSR principles are as shown in Figure 9.
DPFSR is by scramble disturbing source, multiple linear feedback shift register LFSR, logic controller and data buffer storages
What device was formed.For wherein scramble disturbing source using real random number generator, main function is that the output dynamically to LFSR is entered
Line disturbance, the correlation of pseudo random number output is reduced with this.Using LFSR primarily to facilitating High-Speed Hardware to realize.Control
Logic plays state of a control conversion, and coordinates the effect of all parts work.It is temporary that the random number of generation is input to data buffer
When store, prepared for the calling of system, data buffer being capable of real time automatic update content therein.
What the control logic one in Fig. 8 was carried out using XOR gate.Control logic two is one and turns serializer circuit, data
Buffer being capable of real time automatic update content therein.The DPFSR course of work is mainly：M LFSR original state all
After setting, DPFSR enters normal operating conditions.In DPFSR normal operating conditions, LFSR work and previously described work
Process is roughly the same, simply during work real random number generator interference.Real random number generator is done to LFSR
Disturb and XOR is mainly carried out by the output of real random number generator and a certain position of LFSR registers, obtained value substitutes
Position originally, others all keep constant.By schematic diagram, it can be seen that, DPFSR operating efficiency is m times of single channel LFSR, can
To produce mbits simultaneously.Caused random number is deposited into data after further disorder processing, according to FIFO principle and delayed
In depositing.That is, random number caused by every time is arranged in order from front to back according to precedence in data buffer, when slow
When rushing device completely, the random number of foremost is abandoned, and random number order below moves forward.
True and false random number selection circuit to true and false random number for switching over, and the circuit is by logic gates structure
Into its circuit diagram is as illustrated, S is switching signal, and when switching off (i.e. S=0), system exports pseudo random number, when switch closes
System output true random number when closing (S=1).Its circuit diagram is as shown in the figure.Select circuit function expression formulas are：
Its circuit theory diagrams is as shown in Figure 10.
Its post-layout simulation results exhibit is as shown in figure 11；Wherein：True_random is the true random number of single-bit,
Pseudorandom is single-bit pseudo random number, and random_number is the true and false random number of select circuits selection, and prn is
Two bit pseudo-random numbers.
Result prn [0] caused by LFSR0 and LFSR1 and prn [1] are detected, its data is shown in annex 1, and it is detected
As a result it is as follows.
Total test number n=567547
(1) single-bit detects
The number that " 0 " occurs in prn [0] is 283463, and the ratio shared by it is 0.49945292
The number that " 1 " occurs is 284084, and the ratio shared by it is 0.5005471
The number that " 0 " occurs in prn [1] is 284005, and the ratio shared by it is 0.5004079
The number that " 1 " occurs is 283542, and the ratio shared by it is 0.4995921
It can be seen that 0,1 probability is roughly equal, tested by bit distribution, further illustrate that uniform properties are preferable
(2) frequency detects
Prn [0] frequency is 0.67948735
Prn [1] frequency is 0.37771145
(3) operation detection (run distribution)
Prn [0] transition times are 283091
Prn [1] transition times are 284043
It it is expected that transition times are (1+567547)/2=283774
prn[0]
Distance of swimming Ck values are as follows：
0 distance of swimming：C1=70841, C2=35295, C3=17571, C4=8861, C5=4515
1 distance of swimming：C1=70316, C2=35558, C3=17794, C4=8935, C5=4520
prn[1]
Distance of swimming Ck values are as follows：
0 distance of swimming：C1=70939, C2=35693, C3=17667, C4=8799, C5=4445
1 distance of swimming：C1=70226, C2=35398, C3=17638, C4=8960, C5=4391
Theoretical value：C1=70943.625, C2=35471.8125, C3=17735.90625, C4=8867.953125,
C5=4433.976563
Its derivation formula is E (CK)=2-(K+1)(n-k+3), K is substituted into 1,2..., n-2 respectively, n=56754, test knot
Fruit can consider that output sequence correlation is smaller.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (5)
- A kind of 1. high frequency asynchronous randomizer based on FPGA, it is characterised in that it is described based on FPGA high frequency asynchronous with Machine number generator includes：Sampling module；The sampling module is sampled by Click circuits to frequency caused by random number；Real random number generator, it is connected with sampling module, to be trembled caused by multigroup isometric phase inverter oscillating loop phase XOR Dynamic signal is sampled as stochastic source by sampling pulse to stochastic source；Pseudorandom number generator, it is connected with real random number generator, pseudorandom number generator is disturbed using true random number Disorderly, for strengthening the randomness of pseudo random number；True and false random number selecting module, is connected with real random number generator module and pseudorandom number generator module respectively, right True random number and pseudo random number are selected.
- 2. the high frequency asynchronous randomizer based on FPGA as claimed in claim 1, it is characterised in that the Click electricity There are two pairs of I/O nodes on road, and a pair of of left side in_R/in_A is used for and the Click of left is communicated, another pair out_ of right R/out_A is used for and the Click of right is communicated.
- 3. the high frequency asynchronous randomizer based on FPGA as claimed in claim 1, it is characterised in that the true random number Generator, when the loop that 2N+1 phase inverter composition closes, obtains the running clock of a high frequency inside FPGA.
- 4. the high frequency asynchronous randomizer based on FPGA as claimed in claim 1, it is characterised in that the higher-order of oscillation Device is by pulse enable signal enablings.
- 5. the high frequency asynchronous randomizer based on FPGA as claimed in claim 1, it is characterised in that the linear feedback Shift register forms by shift register and with embedded feedback function two parts.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111124363A (en) * | 2019-12-28 | 2020-05-08 | 武汉瑞纳捷电子技术有限公司 | True random number generation method and true random number generator |
| CN113485671A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
| CN114244397A (en) * | 2022-02-25 | 2022-03-25 | 北京智芯微电子科技有限公司 | Frequency hopping communication device, method, chip, transmitter and storage medium |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111124363A (en) * | 2019-12-28 | 2020-05-08 | 武汉瑞纳捷电子技术有限公司 | True random number generation method and true random number generator |
| CN113485671A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
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| CN114244397A (en) * | 2022-02-25 | 2022-03-25 | 北京智芯微电子科技有限公司 | Frequency hopping communication device, method, chip, transmitter and storage medium |
| CN114244397B (en) * | 2022-02-25 | 2022-05-10 | 北京智芯微电子科技有限公司 | Frequency hopping communication device, method, chip, transmitter and storage medium |
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