CN107678731B - High-frequency asynchronous random number generator based on FPGA - Google Patents
High-frequency asynchronous random number generator based on FPGA Download PDFInfo
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- CN107678731B CN107678731B CN201711080455.9A CN201711080455A CN107678731B CN 107678731 B CN107678731 B CN 107678731B CN 201711080455 A CN201711080455 A CN 201711080455A CN 107678731 B CN107678731 B CN 107678731B
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Abstract
The invention belongs to the technical field of data processing, and discloses a high-frequency asynchronous random number generator based on an FPGA (field programmable gate array). The high-frequency asynchronous random number generator is provided with a sampling module, and samples are carried out through a Click circuit so as to improve the frequency of random number generation; the true random number generator takes jitter signals generated by different or different groups of equal-length inverter oscillation loops as random sources and samples the random sources through sampling pulses; the pseudo-random number generator scrambles the pseudo-random number by adopting a true random number so as to enhance the randomness of the pseudo-random number; the user selects the true random number and the pseudo random number through the true pseudo random number selection module according to the needs of the user. A working mechanism utilizing clock jitter and phase drift of a digital circuit is adopted, and a plurality of groups of inverter oscillation loops are used as random sources. The output true random number or pseudo random number can be selected at will, so that the operation of a user is greatly facilitated, the function of the system is more complete, and the operability is stronger.
Description
Technical Field
The invention belongs to the technical field of data processing, and particularly relates to a high-frequency asynchronous random number generator based on an FPGA (field programmable gate array)
Background
With the rapid development of computer networks and communication technologies, the security of information data becomes more and more important, and the cryptographic technology has also been rapidly developed as the core technology of information security. Random numbers may be used in cryptographic algorithms to act as keys, in authentication protocols as challenge data, in some specific instances as random padding bits or random masks, etc. The random number generator not only has wide application in the field of information security, but also is widely applied in statistics. Therefore, the design of random number generators is of great importance.
Currently, there are three main schemes for designing true random number generators: direct amplification method, discrete event chaos method, and oscillator sampling method. The former two are mainly used for custom-made unit design, are limited by device process technology, and cannot be reused across processes. In addition, the random number generator designed by the schemes has a low rate of generating random numbers, and generally has only dozens of Kb/s. If the method is used in the field of information security, the efficiency of secure communication is severely limited, and the method becomes a bottleneck of the secure communication. And by adopting the oscillator sampling method, not only the common logic unit is used, the hardware cost is low, but also the efficiency of generating the random number is high.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a high-frequency asynchronous random number generator based on an FPGA.
The present invention is achieved in such a way that,
a high-frequency asynchronous random number generator based on FPGA is provided with a sampling module, comprising:
the sampling module is used for sampling through a Click circuit, and the frequency of random number generation is improved;
the true random number generator is connected with the sampling module, takes jitter signals generated by different or equal-length inverter oscillation loops of a plurality of groups as random sources, and samples the random sources through sampling pulses;
the pseudo random number generator is formed by connecting an LFSR module and a true random number generator, and the true random number is adopted to disturb the output of the LFSR so as to enhance the randomness of pseudo random numbers;
and the true pseudo-random number selection module is respectively connected with the true random number generator module and the pseudo-random number generator module and is used for selecting the true random number and the pseudo-random number according to the needs of the user.
Further, the Click circuit has two pairs of input/output nodes, one pair in _ R/in _ A on the left for communicating with the Click on the left, and the other pair out _ R/out _ A on the right for communicating with the Click on the right.
Further, the true random number generator is inside the FPGA, and when 2N +1 inverters form a closed loop, a high-frequency oscillation signal can be obtained.
Further, the high frequency oscillator is started by a single pulse enable signal.
Furthermore, the linear feedback shift register consists of a shift register and a feedback function.
The invention has the advantages and positive effects that:
the high-frequency asynchronous random number generator based on the FPGA adopts a working mechanism of utilizing clock jitter and phase drift of a digital circuit and takes a plurality of groups of inverter oscillation loops as random sources. The pseudo-random number generator is designed based on LSFR, and uses true random number generator as its perturbation mechanism, and is generated by multiple LSFR simultaneously, and can generate multi-bit value when each sampling signal arrives. The design adopts a Click circuit as a sampling signal, so that the system frequency can be improved. And a true pseudo-random number selection circuit is designed, so that the true random number or the pseudo-random number can be randomly selected to be output, the operation of a user is greatly facilitated, the function of the system is more perfect, and the operability is stronger.
Compared with the defects and shortcomings of the prior art, the invention has the following beneficial effects:
1. the asynchronous Click circuit module is adopted to drive the circuit, so that the frequency of random number generation is greatly improved. Because the inherent clock frequency of the Xilinx vc707 development platform is 200MHz, if a synchronous clock is adopted to drive the circuit, the highest generation frequency of the random number is 200MHz, and the circuit is driven by adopting an asynchronous Click circuit module in the design, and the generation frequency of the random number can reach 289MHz.
2. The generation of the true pseudo-random number is controlled by adopting the true pseudo-random number selection module, so that the true random number or the pseudo-random number can be output according to the requirements of users, and the requirements of the users are greatly met.
3. The pseudo-random number generator is not implemented by an algorithm in design, but a true random number generator is used for scrambling the pseudo-random number, so that the complexity of the algorithm is avoided and the correlation of the pseudo-random number is reduced.
Drawings
FIG. 1 is a system diagram of an FPGA-based high frequency asynchronous random number generator provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of a Click circuit provided by an embodiment of the invention;
FIG. 3 is a waveform diagram of a Click circuit provided by an embodiment of the invention;
FIG. 4 is a diagram of a high frequency oscillator pulse signal provided by an embodiment of the present invention;
FIG. 5 is a diagram of obtaining a wobble signal according to an embodiment of the present invention;
FIG. 6 is a block diagram of a design of a true random source provided by an embodiment of the present invention;
FIG. 7 is a diagram of a feedback shift register FSR provided in accordance with an embodiment of the present invention;
FIG. 8 is a diagram of a linear feedback shift register LFSR provided by an embodiment of the invention;
FIG. 9 is a schematic diagram of a high speed pseudo-random number generator provided by an embodiment of the present invention;
FIG. 10 is a schematic diagram of a Select circuit according to an embodiment of the present invention;
fig. 11 is a diagram of a simulation result of a circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The application of the present invention will be further described with reference to the accompanying drawings 1-11 and the specific embodiments.
The high-frequency asynchronous random number generator based on the FPGA comprises a sampling module, a true random number generator module, a pseudo random number generator module and a true pseudo random number selection module.
As shown in fig. 1. Wherein:
the sampling module adopts a Click circuit for sampling, and the module can improve the frequency of random number generation;
the true random number generator is designed based on different gate delays, takes different or generated jitter signals of a plurality of groups of equal-length inverter oscillation loops as random sources, and then samples the random sources through sampling pulses;
the pseudo-random number generator adopts a pseudo-random number generator based on an LFSR (Linear feedback Shift register), and adopts a true random number to disturb the pseudo-random number so as to enhance the randomness of the pseudo-random number;
the true pseudo-random number selection module is designed to meet the needs of a user, and the user can select the true random number and the pseudo-random number according to the needs of the user.
A Click circuit is used to generate the sampling pulses and the sampling frequency can be increased. The schematic diagram of the Click asynchronous control circuit is shown in fig. 2, and there are two pairs of inputs/outputs to implement a "constrained data binding" two-phase handshake protocol, where the left pair (in _ R/in _ a) is used for the Click communication on the left, and the right pair (out _ R/out _ a) is used for the Click communication on the right. When the input handshake request signal in _ R rises, the signal goes high through the xor gate, and then the signal output from the xor gate passes through the and gate, so that the flip-flop FF operates, and at the same time, the local Fire is activated, and then the value output from the flip-flop is transmitted to in _ a and out _ R, respectively. Where in _ a indicates that the last Click circuit was acknowledged and out _ R indicates that the next handshake request is made. Then the two stages of Click modules will reset in _ A and out _ R of the Click while canceling the local Fire. The local Fire processes data during the time period of activation and cancellation.
In the design, a single Click module is used, different oscillation signals are respectively input into input ends in _ R and out _ A, so that the Click module circularly outputs a fire signal, and a true random number and a pseudo random number are sampled at the rising edge of the fire signal.
The Click circuit and its waveform diagram are shown in figure 3,
the true random number generator is inside the FPGA, and when 2N +1 inverters form a closed loop, a high-frequency oscillation clock can be obtained, and the period of the clock signal is related to the gate delay and the number of the inverters and is not related to an external signal.
High frequency oscillator the high frequency oscillator is started by a single pulse enable signal as shown in figure 4. Due to the difference of the delay time of each gate, the output time of two groups of oscillation rings with the same length is also different. If the outputs of two sets of oscillation rings of group 1 and group 2 of the same length are xored, a new set of waveforms made up of random signals can be obtained, as shown in fig. 5.
The design of a true random source module is shown in FIG. 6.
The linear feedback shift register consists of two parts: a shift register and a feedback function.
As shown in fig. 7. The shift register is a bit sequence, when one bit is generated each time, all bits in the shift register are shifted to the right by one bit, the shifted bits are the result, and the left-most bit which is vacated is filled with the result obtained by operating all other bits by a feedback function. When the feedback function is a linear function, the feedback shift register FSR is the LFSR. One of the simplest, and most common, LFSRs that is most easily implemented is a simple xor of the feedback function for certain bits in the shift register, as shown in fig. 8.
The bits that participate in the exclusive or operation are called taps. An LFSR having a length of n bits of at most 2 n Internal states with a period of at most 2 n -1, since the all zero state is self-closing.
The high speed pseudo random number generator DPFSR principle is shown in fig. 9.
The DPFSR is composed of a scrambling disturbance source, a plurality of linear feedback shift registers LFSR, a logic controller and a data buffer. The scrambling disturbance source adopts a true random number generator and is mainly used for dynamically scrambling the output of the LFSR so as to reduce the correlation of pseudo-random number output. The LFSR is mainly used to facilitate high-speed hardware implementation. The control logic plays a role in controlling state transition and coordinating the work of each component. The generated random number is input into a data buffer for temporary storage, so that preparation is made for calling of the system, and the data buffer can automatically update the content in the data buffer in real time.
The control logic one in fig. 8 is performed by using an exclusive or gate. The second control logic is a parallel-serial circuit, and the data buffer can automatically update the content in the parallel-serial circuit in real time. The working process of the DPFSR is mainly as follows: after the initial states of the m LFSRs are all set, the DPFSR enters a normal working state. In the normal operating state of the DPFSR, the operation of the LFSR is substantially the same as described above, except that the true random number generator interferes during operation. The interference of the true random number generator to the LFSR is mainly to carry out XOR operation on the output of the true random number generator and a certain bit of the LFSR register, the obtained value replaces the original bit, and the others are kept unchanged. As can be seen from the schematic diagram, the DPFSR has m times of working efficiency of the single-way LFSR, and mbits can be generated simultaneously. The generated random numbers are stored into a data cache according to the FIFO principle after further scrambling. That is, the random numbers generated each time are sequentially arranged from front to back in the data buffer in chronological order, and when the buffer is full, the foremost random number is discarded, and the following random numbers are sequentially advanced.
The true pseudo random number selection circuit is used for switching a true pseudo random number, and the circuit is composed of a logic gate circuit, a circuit diagram of the circuit is shown, S is a switch signal, the system outputs the pseudo random number when the switch is opened (namely, S = 0), and the system outputs the true random number when the switch is closed (S = 1). The circuit diagram is shown in the figure. The Select circuit function expression is:
the schematic circuit diagram is shown in fig. 10.
The simulation result is shown in fig. 11; wherein: true _ random is a single-bit true random number, pseudorandom is a single-bit pseudo random number, random _ number is a true pseudo random number selected by the select circuit, and prn is a two-bit pseudo random number.
The results prn [0] and prn [1] from LFSR0 and LFSR1 were examined, and the data are shown in appendix 1, and the examination results are shown below.
Total number of tests n =567547
(1) Single bit detection
The frequency of 0 in prn 0 is 283463, and its proportion is 0.49945292
The frequency of occurrence of '1' is 284084, and the proportion of the 1 is 0.5005471
The frequency of occurrence of "0" in prn 1 is 284005, and its ratio is 0.5004079
The frequency of occurrence of "1" is 283542, and the proportion of the 1 is 0.4995921
It can be seen that the probabilities of 0,1 are approximately equal, and the better uniformity characteristic is further illustrated by the bit distribution test
(2) Frequency detection
prn [0] frequency 0.67948735
The frequency of prn [1] is 0.37771145
(3) Operation detection (run distribution)
The hop count of prn [0] is 283091
The jump number of prn 1 is 284043
The expected jumping frequency is (1 + 567547)/2 =283774
prn[0]
The run Ck values are as follows:
run 0: c1=70841, C2=35295, C3=17571, C4=8861, C5=4515
Run 1: c1=70316, C2=35558, C3=17794, C4=8935, C5=4520
prn[1]
The run Ck values are as follows:
run 0: c1=70939, C2=35693, C3=17667, C4=8799, C5=4445
Run 1: c1=70226, C2=35398, C3=17638, C4=8960, C5=4391
Theoretical value: c1=70943.625, C2=35471.8125, C3=17735.90625, C4=8867.953125, C5=4433.976563
Derived formula is E (C) K )＝2 -(K+1) (n-K + 3), K is substituted with 1,2, n-2, respectively, and n =56754, and the test result can be regarded as that the output sequence has small correlation.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (4)
1. The high-frequency asynchronous random number generator based on the FPGA is characterized by comprising the following components in percentage by weight: a sampling module; the sampling module samples the frequency generated by the random number through a Click circuit; the Click circuit has two pairs of input/output nodes, wherein the left pair of in _ R/in _ A is used for communicating with the Click on the left, the other right pair of out _ R/out _ A is used for communicating with the Click on the right, and the other right pair (out _ R/out _ A) is used for communicating with the Click on the right; when an input handshake request signal in _ R rises, the signal is enabled to go high through an exclusive-or gate, then the signal output by the exclusive-or gate and an AND gate are passed, so that a trigger FF works, a local Fire is activated, the value output by the trigger is respectively transmitted to in _ A and out _ R, wherein the in _ A indicates that a previous Click circuit is answered, the out _ R indicates that a next handshake request is carried out, then a Click module of the left and right stages resets the in _ A and the out _ R of the Click, the local Fire is cancelled, and the local Fire carries out data processing in the period of activation and cancellation; using a single Click module, inputting different oscillation signals into input ends in _ R and out _ A respectively, so that the Click module circularly outputs a fire signal, and sampling a true random number and a pseudo random number at the rising edge of the fire signal;
the true random number generator is connected with the sampling module, takes a plurality of groups of inverter oscillation loops with equal length different or generated jitter signals as random sources, and samples the random sources through sampling pulses;
the pseudo-random number generator is connected with the true random number generator, and is disturbed by adopting the true random number for enhancing the randomness of the pseudo-random number;
and the true pseudo-random number selection module is respectively connected with the true random number generator module and the pseudo-random number generator module and is used for selecting the true random number and the pseudo-random number.
2. The FPGA-based high frequency asynchronous random number generator of claim 1 wherein said true random number generator is internal to the FPGA to obtain a high frequency oscillating clock when 2n +1 inverters make up a closed loop.
3. The FPGA-based high frequency asynchronous random number generator of claim 2 wherein a high frequency oscillator in said true random number generator is enabled by a single pulse enable signal.
4. The FPGA-based high frequency asynchronous random number generator of claim 1 wherein a linear feedback shift register in said true random number generator is comprised of a shift register and an embedded feedback function.
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| CN113485671B (en) * | 2021-07-06 | 2024-01-30 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
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