CN113485671A - Click controller and asynchronous micro-pipeline data flow controller - Google Patents
Click controller and asynchronous micro-pipeline data flow controller Download PDFInfo
- Publication number
- CN113485671A CN113485671A CN202110760917.1A CN202110760917A CN113485671A CN 113485671 A CN113485671 A CN 113485671A CN 202110760917 A CN202110760917 A CN 202110760917A CN 113485671 A CN113485671 A CN 113485671A
- Authority
- CN
- China
- Prior art keywords
- controller
- signal
- stage
- gate
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
Abstract
The invention relates to a click controller and an asynchronous micro-pipeline data flow controller. The click controller includes: the inverter, the exclusive-OR gate and the trigger with the first output end connected to the first input end in a return mode; the input end of the exclusive-OR gate inputs a Fill signal of a previous-stage click controller and a drain signal of a next-stage click controller; the exclusive-OR gate is used for generating four local clock signals from the Fill signal and the drain signal; the output end of the exclusive-or gate is connected with the second input end of the trigger; the second output end of the trigger is connected with the input end of the inverter; the trigger is also used for outputting full signals of the next-stage click controller; the inverter is used for inverting the full signal and outputting an empty signal of a last-stage click controller; the empty signal is a response signal of a last-stage click controller. The invention has the characteristics of simple circuit structure and high compatibility.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a click controller and an asynchronous micro-pipeline data flow controller.
Background
The conventional click controller is a two-term signal controller, the pipeline circuit structure of the branch and confluence structure and the FIFO structure is complex, and the handshake signals of the pipeline cannot be compatible with other asynchronous pipeline controllers such as a Mousetrap or MullerC unit.
Therefore, a need exists for a click controller with a simple circuit structure and better compatibility.
Disclosure of Invention
The invention aims to provide a click controller and an asynchronous micro-pipeline data flow controller, which have the characteristics of simple circuit structure and high compatibility.
In order to achieve the purpose, the invention provides the following scheme:
a click controller comprising: the inverter, the exclusive-OR gate and the trigger with the first output end connected to the first input end in a return mode;
the input end of the exclusive-OR gate inputs a Fill signal of a previous-stage click controller and a drain signal of a next-stage click controller; the exclusive-OR gate is used for generating four local clock signals from the Fill signal and the drain signal;
the output end of the exclusive-or gate is connected with the second input end of the trigger;
the second output end of the trigger is connected with the input end of the inverter; the trigger is also used for outputting full signals of the next-stage click controller; the full signal is a request signal of a click controller;
the inverter is used for inverting the full signal and outputting an empty signal of a last-stage click controller; the empty signal is a response signal of a last-stage click controller.
Optionally, the time when the Fill signal reaches the inverter is earlier than the time when the drain signal reaches the inverter.
An asynchronous micro-pipeline data flow controller, wherein the asynchronous micro-pipeline data flow controller is connected with the click controller; the asynchronous micro-pipeline data flow controller comprises: an AND gate and a buffer;
the full signal of the last-stage click controller is input to the input end of the buffer; the output end of the buffer is connected with the first input end of the AND gate, and the second input end of the AND gate inputs an empty signal of the next-stage click controller; and the AND gate outputs a drain signal of the previous-stage click controller and a fill signal of the next-stage click controller.
An asynchronous micro-pipeline data flow controller, wherein the asynchronous micro-pipeline data flow controller is connected with the click controller; the asynchronous micro-pipeline data flow controller comprises: the first buffer is connected with the first input end of the AND gate;
the full signal of the last-stage click controller in the first branch is input to the input end of the first buffer; the output end of the first buffer is connected with the first input end of the AND gate; the input end of the second buffer inputs full signals of a last-stage click controller in a second branch; the output end of the second buffer is connected with the second input end of the AND gate; the third input end of the AND gate inputs an empty signal of the next-stage click controller; and the output end of the AND gate outputs a drain signal of the upper-stage click controller in the first branch, a drain signal of the upper-stage click controller in the second branch and a fill signal of the lower-stage click controller.
An asynchronous micro-pipeline data flow controller, wherein the asynchronous micro-pipeline data flow controller is connected with the click controller; the asynchronous micro-pipeline data flow controller comprises: an AND gate and a buffer;
the full signal of the last-stage click controller is input to the input end of the buffer; the output end of the buffer is connected with the first input end of the AND gate; the second input end of the AND gate inputs an empty signal of a next-stage click controller in the first branch; the third input end of the AND gate inputs an empty signal of a next-stage click controller in the second branch; the AND gate outputs a drain signal of the previous stage of the click controller, a fill signal of the next stage of the click controller in the first branch, and a fill signal of the next stage of the click controller in the second branch.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a click controller and an asynchronous micro-pipeline data flow controller, which are used as controllers of each stage of a pipeline and comprise two input signals Fill and drain and two output signals full and empty. The request and response signals Fill and drain from the upper-stage pipeline and the lower-stage pipeline generate four local clock signals through an exclusive-OR gate, the flip of the output Q of the trigger is controlled through a trigger signal and a reset signal which are realized through a group of rising and falling edges, the output Q of the trigger is used as the request signal full of the lower stage, and the inverted empty is used as the response signal of the upper-stage pipeline. The control device has the advantages of simple structure, higher speed and adjustable delay of each stage of the controlled pipeline.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a click controller according to the present invention;
FIG. 2 is a schematic diagram of a FIFO architecture for an asynchronous pipeline data flow controller;
FIG. 3 is a diagram of a flow merge structure of an asynchronous pipeline data flow controller;
FIG. 4 is a block diagram of a branch structure of an asynchronous pipeline data flow controller.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a click controller and an asynchronous micro-pipeline data flow controller, which have the characteristics of simple circuit structure and high compatibility.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a click controller provided by the present invention, and as shown in fig. 1, the click controller provided by the present invention includes: the inverter INV, the XOR gate XOR, and the flip-flop FF having the first output terminal connected back to the first input terminal.
The input end of the exclusive-OR gate inputs a Fill signal of a previous-stage click controller and a drain signal of a next-stage click controller; the exclusive-or gate is used for generating four local clock signals from the Fill signal and the drain signal.
The output end of the exclusive-or gate is connected with the second input end of the trigger; the flip-flop output Q is controlled to flip by a set of trigger signals and reset signals implemented by a set of rising and falling edges.
The second output end of the trigger is connected with the input end of the inverter; the trigger is also used for outputting full signals of the next-stage click controller; the full signal is a request signal of a click controller;
the inverter is used for inverting the full signal and outputting an empty signal of a last-stage click controller; the empty signal is a response signal of a last-stage click controller.
To meet the timing constraints of asynchronous micro-pipeline control circuits, the Fill signal arrives at the inverter at a time earlier than the drain signal arrives at the inverter.
The click controller provided by the invention is improved on the basis of the original click controller structure, and has a simple circuit structure and higher compatibility. Simple logic processing and delay of handshake signals between all stages of the asynchronous micro-pipeline are achieved to meet timing sequence constraint of the asynchronous micro-pipeline control circuit, and FIFO, branching and confluence of the pipeline can be achieved.
Fig. 2 is a schematic diagram of a FIFO structure of an asynchronous pipeline data flow controller, as shown in fig. 2. The asynchronous micro-pipeline data flow controller provided by the invention is connected with the click controller; the asynchronous micro-pipeline data flow controller comprises: an AND gate and a buffer;
the full signal of the last-stage click controller is input to the input end of the buffer; the output end of the buffer is connected with the first input end of the AND gate, and the second input end of the AND gate inputs an empty signal of the next-stage click controller; and the AND gate outputs a drain signal of the previous-stage click controller and a fill signal of the next-stage click controller.
FIG. 3 is a schematic diagram of a merge structure of an asynchronous pipeline data flow controller, as shown in FIG. 3, the asynchronous pipeline data flow controller is connected to the click controller; the asynchronous micro-pipeline data flow controller comprises: an AND gate, a first buffer and a second buffer,
the input end of the first buffer inputs full1 signal of the last-stage click controller in the first branch; the output end of the first buffer is connected with a first input end (shown as 1 in figure 3) of the AND gate; the input end of the second buffer inputs full2 signal of the last-stage click controller in the second branch; the output end of the second buffer is connected with a second input end (shown as 2 in figure 3) of the AND gate; a third input end (shown as 0 in fig. 3) of the and gate inputs an empty signal of a next-stage click controller; and the output end of the AND gate outputs a drain1 signal of the last-stage click controller in the first branch, a drain2 signal of the last-stage click controller in the second branch and a fill signal of the next-stage click controller.
FIG. 4 is a schematic diagram of a branch structure of an asynchronous pipeline data flow controller, as shown in FIG. 4, the asynchronous pipeline data flow controller is connected to the click controller; the asynchronous micro-pipeline data flow controller comprises: an AND gate and a buffer;
the full signal of the last-stage click controller is input to the input end of the buffer; the output end of the buffer is connected with a first input end (shown as 0 in figure 4) of the AND gate; a second input end (shown as 1 in FIG. 4) of the AND gate inputs an empty1 signal of a next-stage click controller in the first branch; a third input end (shown as 2 in FIG. 4) of the AND gate inputs an empty2 signal of a next-stage click controller in the second branch; the AND gate outputs the drain signal of the previous stage of the click controller, the fill1 signal of the next stage of the click controller in the first branch, and the fill2 signal of the next stage of the click controller in the second branch.
For each stage of click controller (pipeline controller), there are two states of "empty" and "full" according to the controlled data path, which are respectively represented by the high levels of signal outputs empty and full of the pipeline controller of the previous and next stages.
When implementing the FIFO structure of the asynchronous pipeline, the fill signal of each stage of the asynchronous pipeline Data Flow Controller (DFC) represents the and of the data fill request full from the previous stage and the reply empty of the present stage, and drain represents the and of the reply empty and the full signal of the present stage of the data from the next stage. An asynchronous pipeline Data Flow Controller (DFC) processes the transmission of each stage of pipeline signals through a buffer connected with an input of an AND gate, and for each stage of pipeline control signals, the time of a request signal is required to be earlier than the arrival time of a response signal, so that the response signal from the previous stage of the AND gate between the pipeline controllers needs to pass through a buffer to meet the timing constraint condition.
When the branch pipeline structure is implemented, when the request outputs full1 and full2 of the previous stage and the response output empty of the next stage are simultaneously high level, the response input drain1 of the previous stage pipeline and the request input fill of the next stage pipeline are simultaneously pulled high level after passing through the and gate of the asynchronous pipeline Data Flow Controller (DFC).
When the converging pipeline structure is realized, when the request output full of the previous stage and the response outputs empty1 and empty2 of the next stage are simultaneously high level, after passing through the and gate of the asynchronous pipeline Data Flow Controller (DFC), the response input drain of the previous stage pipeline and the request input fill1 of the next stage pipeline are simultaneously pulled high level.
That is, when a branched or merged pipeline structure is implemented, when all controllers of a previous stage are full (full), that is, full is high level, and all controllers of a next stage are empty (empty), that is, empty is high level, an asynchronous pipeline Data Flow Controller (DFC) pulls up a drain (drain) input signal drain of the previous stage and a fill (fill) input signal fill of the next stage.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (5)
1. A click controller, comprising: the inverter, the exclusive-OR gate and the trigger with the first output end connected to the first input end in a return mode;
the input end of the exclusive-OR gate inputs a Fill signal of a previous-stage click controller and a drain signal of a next-stage click controller; the exclusive-OR gate is used for generating four local clock signals from the Fill signal and the drain signal;
the output end of the exclusive-or gate is connected with the second input end of the trigger;
the second output end of the trigger is connected with the input end of the inverter; the trigger is also used for outputting full signals of the next-stage click controller; the full signal is a request signal of a click controller;
the inverter is used for inverting the full signal and outputting an empty signal of a last-stage click controller; the empty signal is a response signal of a last-stage click controller.
2. A click controller according to claim 1, characterised in that the Fill signal arrives at the inverter earlier than the drain signal arrives at the inverter.
3. An asynchronous pipeline data flow controller, wherein the asynchronous pipeline data flow controller is connected with the click controller of any one of claims 1-2; the asynchronous micro-pipeline data flow controller comprises: an AND gate and a buffer;
the full signal of the last-stage click controller is input to the input end of the buffer; the output end of the buffer is connected with the first input end of the AND gate, and the second input end of the AND gate inputs an empty signal of the next-stage click controller; and the AND gate outputs a drain signal of the previous-stage click controller and a fill signal of the next-stage click controller.
4. An asynchronous pipeline data flow controller, wherein the asynchronous pipeline data flow controller is connected with the click controller of any one of claims 1-2; the asynchronous micro-pipeline data flow controller comprises: the first buffer is connected with the first input end of the AND gate;
the full signal of the last-stage click controller in the first branch is input to the input end of the first buffer; the output end of the first buffer is connected with the first input end of the AND gate; the input end of the second buffer inputs full signals of a last-stage click controller in a second branch; the output end of the second buffer is connected with the second input end of the AND gate; the third input end of the AND gate inputs an empty signal of the next-stage click controller; and the output end of the AND gate outputs a drain signal of the upper-stage click controller in the first branch, a drain signal of the upper-stage click controller in the second branch and a fill signal of the lower-stage click controller.
5. An asynchronous pipeline data flow controller, wherein the asynchronous pipeline data flow controller is connected with the click controller of any one of claims 1-2; the asynchronous micro-pipeline data flow controller comprises: an AND gate and a buffer;
the full signal of the last-stage click controller is input to the input end of the buffer; the output end of the buffer is connected with the first input end of the AND gate; the second input end of the AND gate inputs an empty signal of a next-stage click controller in the first branch; the third input end of the AND gate inputs an empty signal of a next-stage click controller in the second branch; the AND gate outputs a drain signal of the previous stage of the click controller, a fill signal of the next stage of the click controller in the first branch, and a fill signal of the next stage of the click controller in the second branch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110760917.1A CN113485671B (en) | 2021-07-06 | 2021-07-06 | Click controller and asynchronous micro-pipeline data flow controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110760917.1A CN113485671B (en) | 2021-07-06 | 2021-07-06 | Click controller and asynchronous micro-pipeline data flow controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113485671A true CN113485671A (en) | 2021-10-08 |
| CN113485671B CN113485671B (en) | 2024-01-30 |
Family
ID=77941195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110760917.1A Active CN113485671B (en) | 2021-07-06 | 2021-07-06 | Click controller and asynchronous micro-pipeline data flow controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113485671B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6366936B1 (en) * | 1999-01-12 | 2002-04-02 | Hyundai Electronics Industries Co., Ltd. | Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm |
| CN106059545A (en) * | 2016-06-16 | 2016-10-26 | 电子科技大学 | Time sequence control circuit for assembly line having low power consumption |
| CN106849939A (en) * | 2017-01-24 | 2017-06-13 | 四川和芯微电子股份有限公司 | CMOS phase discriminators |
| CN107678731A (en) * | 2017-11-06 | 2018-02-09 | 何安平 | A kind of high frequency asynchronous randomizer based on FPGA |
| CN110417412A (en) * | 2019-08-19 | 2019-11-05 | 苏州迅芯微电子有限公司 | A kind of clock generation method, sequence circuit and analog-digital converter |
| CN112667292A (en) * | 2021-01-26 | 2021-04-16 | 北京中科芯蕊科技有限公司 | Asynchronous miniflow line controller |
| CN113489482A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mousetrap |
-
2021
- 2021-07-06 CN CN202110760917.1A patent/CN113485671B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6366936B1 (en) * | 1999-01-12 | 2002-04-02 | Hyundai Electronics Industries Co., Ltd. | Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm |
| CN106059545A (en) * | 2016-06-16 | 2016-10-26 | 电子科技大学 | Time sequence control circuit for assembly line having low power consumption |
| CN106849939A (en) * | 2017-01-24 | 2017-06-13 | 四川和芯微电子股份有限公司 | CMOS phase discriminators |
| CN107678731A (en) * | 2017-11-06 | 2018-02-09 | 何安平 | A kind of high frequency asynchronous randomizer based on FPGA |
| CN110417412A (en) * | 2019-08-19 | 2019-11-05 | 苏州迅芯微电子有限公司 | A kind of clock generation method, sequence circuit and analog-digital converter |
| CN112667292A (en) * | 2021-01-26 | 2021-04-16 | 北京中科芯蕊科技有限公司 | Asynchronous miniflow line controller |
| CN113489482A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mousetrap |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113485671B (en) | 2024-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5087828A (en) | Timing circuit for single line serial data | |
| CN112667292B (en) | Asynchronous micro-pipeline controller | |
| US8253466B2 (en) | Clock generators for generation of in-phase and quadrature clock signals | |
| US8644439B2 (en) | Circuits and methods for signal transfer between different clock domains | |
| US7242737B2 (en) | System and method for data phase realignment | |
| CN113489482B (en) | Asynchronous micro-pipeline data flow controller based on Mouserap | |
| US6188262B1 (en) | Synchronous polyphase clock distribution system | |
| US6304125B1 (en) | Method for generating and distribution of polyphase clock signals | |
| CN113485671A (en) | Click controller and asynchronous micro-pipeline data flow controller | |
| CN114185397B (en) | Cross-clock domain data transmission circuit and method | |
| McAuley | Dynamic asynchronous logic for high-speed CMOS systems | |
| CN105306022A (en) | Asymmetric time-delay apparatus used for asynchronous circuit four-phase handshake protocol | |
| US6911854B2 (en) | Clock skew tolerant clocking scheme | |
| US6959398B2 (en) | Universal asynchronous boundary module | |
| CN113590200B (en) | Asynchronous micro-pipeline controller based on SR latch | |
| CN113114187B (en) | Asynchronous pulse transmission blocking unit, control method thereof and superconducting single-flux quantum circuit | |
| CN114696812A (en) | Asynchronous state machine of self-clocking | |
| CN218825352U (en) | Data transmission circuit, chip, electronic component, and electronic device | |
| US6154046A (en) | Preconditioning input signals of logic gates for glitch-free output signal | |
| Van Toan et al. | Energy-efficient and high performance 2-phase asynchronous micropipelines | |
| CN110825688B (en) | Clock system | |
| EP1308862A1 (en) | Optimization of the design of a synchronous digital circuit | |
| Smith et al. | Low-latency multiple clock domain interfacing without alteration of local clocks | |
| KR20010006850A (en) | Improved skew pointer generation | |
| CN106849935A (en) | A kind of clock buffer drive circuit and PLD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |