CN107659392A - A kind of clock data recovery system - Google Patents
A kind of clock data recovery system Download PDFInfo
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- CN107659392A CN107659392A CN201710146950.9A CN201710146950A CN107659392A CN 107659392 A CN107659392 A CN 107659392A CN 201710146950 A CN201710146950 A CN 201710146950A CN 107659392 A CN107659392 A CN 107659392A
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector
Abstract
The present invention provides a kind of clock data recovery system, the system includes phaselocked loop and some circuit-switched data passages, each circuit-switched data passage includes differential signal receiving port, balanced device, the deserializer being sequentially connected with, along detection module, almost linear phase detectors, integrator；Phaselocked loop provides clock for each circuit-switched data passage；Each circuit-switched data passage also includes Port Multiplier, memory FIFO, phase difference value device and phase difference value controller, the input of Port Multiplier and the output end of deserializer and the output end of integrator connect, the output of integrator also feeds back to almost linear phase detectors, memory FIFO output end and phase difference value controller, the input of phase difference value device is also connected with phase difference value controller and phaselocked loop respectively, and the output end of phase difference value device is connected with deserializer；The output end of differential signal receiving port in each circuit-switched data passage is also associated with matching impedance.
Description
Technical field
The present invention relates to data communication field, more particularly, to a kind of clock data recovery system.
Background technology
Clock data recovery system is indispensable part in high-speed communication system.Existing common clock recovery system
There are the clock recovery system based on phase-locked loop structures and blind over-sampling clock data recovery system.Clock based on phase-locked loop structures
Recovery system, when transmitter and receiver has frequency departure, good frequency following can be accomplished.But phase-locked loop structures
Larger chip area is needed to realize, it is therefore desirable to bigger cost.Blind over-sampling clock data recovery system needs smaller chip
Area, but when transmitter and receiver has frequency departure, system can not correctly recover data.More common way
It is that emitter can send a reference frequency to receiver while data are sent.Receive according to this reference frequency, do
It is consistent with the frequency of receiving terminal to transmitting terminal.This just needs the channel for increasing a reference frequency, the extra cost of increase system.
The content of the invention
The present invention provides a kind of clock data recovery system with good robustness and stability.
In order to reach above-mentioned technique effect, technical scheme is as follows：
A kind of clock data recovery system, including phaselocked loop and some circuit-switched data passages, each circuit-switched data passage include suitable
Differential signal receiving port, balanced device, the deserializer of secondary connection, along detection module, almost linear phase detectors, integrator；Institute
State phaselocked loop and provide clock for each circuit-switched data passage；Each circuit-switched data passage also includes Port Multiplier, memory FIFO, phase difference
It is worth device and phase difference value controller, the input of Port Multiplier and the output end of deserializer and the connection of the output end of integrator, integration
The output of device also feeds back to almost linear phase detectors, memory FIFO output end and phase difference value controller, phase difference value
The input of device is also connected with phase difference value controller and phaselocked loop respectively, and the output end of phase difference value device is connected with deserializer；
Differential signal receiving port in each circuit-switched data passage is also associated with matching impedance.
Further, the treated serial differential signals of equalised device need by deserializer be changed into speed parallel signals with
Facilitate the subsequent treatment of system, the process is：
It is serial poor that deserializer treats under timeticks clks control, with certain multiplying power OSR to equalised device
Sub-signal carries out over-sampling, the data that the treated serial differential signals of equalised device obtain after over-sampling, turns after frequency reducing
Change parallel signal into, the serial data after over-sampling, data [N-1 are successively placed on by the priority of sampling:0], parallel data data
[N-1:0] exported by a synchronous module cko all the time from deserializer, before and after deserializer processing, data transfer rate will not become
Change.
Further, it is described along detection module to data [N-1:0] whether data are along occurring upset and be monitored, the process
For：
By comparing parallel data data [N-1:0] whether two bit data are identical before and after, to judge that data edge is turned over
Whether turn；If front and rear two bit data are identicals, represent that the upset on data edge does not occur for this data moment；It is if preceding
Two bit data are different afterwards, then it represents that the upset that data edge is carved with during this data occurs：
Tr_position [X]=Data [X] ^Data [X-1] X=2~N-1 (1)
Tr_position [0]=Data [0] ^Data` [X-1] (2)
Wherein, Data'[N-1] represent upper timeticks cko N-1bit data.
Further, the almost linear phase detectors overturn the probability of the position occurred within a certain period of time to data edge
Counted, the probability that position of the data along upset occurs is designated as P according to the ratio OSR of over-sampling0, P1, P2……POSR-1, P0,
P1, P2……POSR-1It is shown as the following formula：
Pi=∑ tr_positioni+j*OSRI=0,1, OSR-1, j=0, K-1 (3)
Wherein, N=OSR*K, K are the integer more than or equal to 1, and within the timing statisticses cycle, Data flipping probability of happening is most
Current location of the big position as data edge, represent variable tr_po_update [OSR-1 of the data along position:0] will be corresponding
Position is " 1 ", and remaining position is " 0 "；If P1It is P0, P1, P2……POSR-1Middle the maximum, then the current location on data edge is phase
Position 1, then tr_po_update [1] is set to " 1 ", tr_po_update [0] and tr_po_update [OSR-1:2] it is " 0 ".
Further, the system data center position dat_po_using [OSR-1 being used:0] from over-sampling
Picked up in data and obtain effective data, the data center position dat_po_using [OSR-1 being used:0] it is corresponding to make
Data are along position tr_po_using [OSR-1:0], dat_po_using [OSR-1:0] and tr_po_using [OSR-1:
0] relation is as follows：
If OSR is even number：
Tr_po_using [(i+M) %OSR]=dat_po_using [i], i=0,1 ... OSR-1
If OSR is odd number：
Tr_po_using [(i+M) %OSR]=dat_po_using [i], i=0,1 ... OSR-1
According to tr_po_update [OSR-1:0] with [OSR-1:0] relation obtains lead and lag indication signal up_
Voter and dn_voter；
If OSR is even number：
up_voter[M-1:0] represented by formula below：
Up_voter [k]=(tr_po_update [(i+k+1) %OSR]s ＆tr_po_using [i])
K=0,1 ... M-1；I=0,1 ... OSR-1
dn_voter[M-1:0] represented by formula below：
Dn_voter [k]=(tr_po_update [i]s ＆tr_po_using [(i+k) %OSR])
K=0,1 ... M-1；I=0,1 ... OSR-1
If OSR is odd number：
up_voter[M-1:0] represented by formula below：
Up_voter [k]=(tr_po_update [(i+k+1) %OSR]s ＆tr_po_using [i])
K=0,1 ... M-1；I=0,1 ... OSR-1
dn_voter[M-1:0] represented by formula below：
Up_voter [k]=(tr_po_update [i]s ＆tr_po_using [(i+k+1) %OSR])
K=0,1 ... M-1；I=0,1 ... OSR-1
Up_voter [0]=1 represents that weighted value is 1 unit, and up_voter [1]=1 represents that weighted value is 2 units,
By that analogy；
Dn_voter [0]=1 represents that weighted value is 1 unit, and dn_voter [1]=1 represents that weighted value is 2 units,
By that analogy；
Integrator is directed to up_voter [M-1:0] and dn_voter [M-1:0] give above-mentioned weight respectively to be added up, product
Device is divided to be divided into the advanced integrator of phase and delayed phase integrator, the advanced integrator of phase is to up_voter [M-1:0] characterize
Weight is added up, and delayed phase integrator is to dn_voter [M-1:0] added up；If the advanced integrator of phase overflows,
So " the data center position being used " dat_po_using moves a phase towards augment direction；If delayed phase accumulates
Device is divided to overflow, then dat_po_using moves a phase towards direction is reduced；
Picked up from over-sampling data according to " the data center position being used " and obtain effective data, if dat_po_
Using [0]=1, then it is data [0], data [0+OSR] ... data [0+ (K-1) * OSR] to pick up the valid data obtained.They
Relation can be expressed as follows：
Dat_po_using if [i]=1, i=0,1,2 ... OSR-1. so picks up the valid data obtained by Port Multiplier
For data [i+j*OSR], j=0, the parallel data bit numbers N of 1 ... K-1, K and deserializer relation is expressed as：N=OSR*K.
Further, the memory FIFO is a pushup storage, and FIFO input is a variable-length
Data, FIFO output is fixed-length data.
Preferably, the phase-interpolation controller is an accumulator.
Compared with prior art, the beneficial effect of technical solution of the present invention is：
The present invention includes phaselocked loop and some circuit-switched data passages, and each circuit-switched data passage includes the differential signal being sequentially connected with
Receiving port, balanced device, deserializer, along detection module, almost linear phase detectors, integrator；The phaselocked loop is per all the way
Data channel provides clock；Each circuit-switched data passage also includes Port Multiplier, memory FIFO, phase difference value device and phase difference value control
Device processed, the input of Port Multiplier and the output end of deserializer and the connection of the output end of integrator, the output of integrator are also fed back to
Almost linear phase detectors, memory FIFO output end and phase difference value controller, the input of phase difference value device are also distinguished
It is connected with phase difference value controller and phaselocked loop, the output end of phase difference value device is connected with deserializer；Each circuit-switched data is led to
Differential signal receiving port in road is also associated with matching impedance.The noise margin of the invention for improving system well so that
System involved in the present invention has more preferable robustness and stability in adverse noise environment.
Brief description of the drawings
Fig. 1 is the structure chart of data channel all the way of the invention；
Fig. 2 is the schematic diagram for carrying out over-sampling in the present invention with certain multiplying power OSR；
Fig. 3 is tr_po_using [OSR-1 in the present invention:0] and dat_po_using [OSR-1:0] graph of a relation；
Fig. 4 (a) is the data that are used of present system along the operating diagram that position is 0 position；
Fig. 4 (b) is the operating diagram that present system data edge moves 1 phase towards the direction of reduction；
If Fig. 4 (c) is the operating diagram that present system data edge is displaced to 2 positions；
Fig. 4 (d) is the operating diagram that present system data edge moves 2 phases towards the direction of reduction.
Embodiment
Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；
In order to more preferably illustrate the present embodiment, some parts of accompanying drawing have omission, zoomed in or out, and do not represent actual product
Size；
To those skilled in the art, it is to be appreciated that some known features and its explanation, which may be omitted, in accompanying drawing
's.
Technical scheme is described further with reference to the accompanying drawings and examples.
Embodiment 1
As shown in figure 1, system involved in the present invention, including a shared phaselocked loop that clock source is provided and more numbers
According to 1~N of passage.Rxp and Rxn is the differential signal receiving port of a data channel.Each data channel has respective difference
Receiver port.Receiver port connects one and the impedance of channel matched a to fixed voltage node.
Receiver port also serves as the input of balanced device simultaneously.Balanced device is used for thermal compensation signal in channel
Frequency component is lost.The output of balanced device is eqp and eqn.If the transmission rate of signal is than relatively low, or channel quality is good
Good, frequency loss is smaller, and balanced device can be substituted with buffer.Buffer effect is to provide the enough electricity of next stage module
Press driving force.
Eqp and eqn is also the input of deserializer simultaneously.Serial differential signals on eqp and eqn are pressed a timing clock by deserializer
Beat is converted into the output of parallel signal, and the parallel signal is data [N-1:0].Clks provides timeticks for deserializer.It is high
Fast serial signal needs to be changed into speed parallel signals by deserializer, to facilitate the subsequent treatment of system.In deserializer, at a high speed
Serial signal (input signal of deserializer) carries out over-sampling under timeticks clks control, with certain multiplying power OSR, such as
Shown in Fig. 2.The data that serial signal obtains after over-sampling, it is data [N-1 that parallel signal is converted into after frequency reducing:0].And
Row signal is the data synchronously crossed by cko.Cko is one with respect to the clock for clks compared with low speed.It is serial after over-sampling
Data, data [N-1 are successively placed on by the priority of sampling:0] in.Before and after deserializer processing, data transfer rate will not change.
It is a module that Data flipping edge indication signal is provided in systems along detection.Believe along the output of detection module
Number tr_position [N-1:0] characterize in input data data [N-1:0] overturn in the presence or absence of data edge.tr_
position[N-1:0] principle explanation can be provided by formula (1) and (2).By comparing parallel data data [N-1:0] it is front and rear
Whether two bit data are identical, to judge that whether data edge overturns.If front and rear two bit data are identicals, represent
The upset on data edge does not occur for this data moment.If front and rear two bit data are different, then it represents that are carved with number during this data
Occur according to the upset on edge.
Tr_position [X]=Data [X] ^Data [X-1] X=2~N-1 (1)
Tr_position [0]=Data [0] ^Data` [X-1] (2)
Wherein Data'[N-1] represent upper timeticks cko N-1bit data.
For the system that an over-sampling rate is OSR, N and OSR relation are：N=OSR*K.K is whole more than or equal to 1
Number.
The relatively conventional bang-bang phase detectors of almost linear phase detectors have faster loop response.Directrix
Property phase detectors provide almost linear weight according to probability of the data along upturned position and are weighted.
The probability of the position that data occur almost linear phase detectors along upset first counts within a certain period of time.
The probability that position of the data along upset occurs is designated as P according to the ratio OSR of over-sampling0, P1, P2……POSR-1。P0, P1, P2……
POSR-1It is shown as the following formula：
Pi=∑ tr_positioni+j*OSRI=0,1, OSR-1, j=0, K-1 (3)
Within certain timing statisticses cycle, present bit of the maximum position of Data flipping probability of happening as data edge
Put.Represent variable tr_po_update [OSR-1 of the data along position:0] it is " 1 " by correspondence position, remaining position is " 0 ".Such as
P1It is P0, P1, P2……POSR-1Middle the maximum, then it is assumed that the current location on data edge is phase 1.So tr_po_update [1]
It is set to " 1 ", tr_po_update [0] and tr_po_update [OSR-1:2] it is " 0 ".
And system has one " the data center position being used ".This " data center position being used of system
Put " picked up from over-sampling data and obtain effective data.And corresponding to " the data center position being used " has one " to be used
Data along position ".We remember that " the data center position being used " is dat_po_using [OSR-1:0].We remember " just
In the data used along position " it is tr_po_using [OSR-1:0].Their relation is as shown in Figure 3.In order to express easily, I
Give OSR=5 example." if the data center position being used " is the 2nd phase over-sampling clock position, i.e.,
Valid data are the data that the 2nd phase over-sampling clock position obtains.So " data being used along position " are crossed for the 0th phase and adopted
Sample clock position.Now, we remember that remaining bit in dat_po_using [2]=1, dat_po_using is designated as 0.We remember
Remaining bit in tr_po_using [0]=1, tr_po_using is designated as 0.Similarly, if " the data center position being used
Put " be the 1st phase over-sampling clock position, i.e., valid data are the data that the 1st phase over-sampling clock position obtains.So "
The data used are along position " it is the 4th phase over-sampling clock position.Now, now, we remember dat_po_using [1]=1,
Remaining bit in dat_po_using is designated as 0.We remember remaining bit notes in tr_po_using [4]=1, tr_po_using
For 0.OSR can be odd number, or even number.It is odd and even number according to OSR, provides dat_po_using [OSR- respectively
1:0] and tr_po_using [OSR-1:0] relation is as follows：
If OSR is even number, M and OSR relation are：OSR=2*M.Tr_po_using[OSR-1:0] and dat_po_
using[OSR-1:0] relation is following (% represents complementation)：
Tr_po_using [(i+M) %OSR]=dat_po_using [i]
I=0,1 ... OSR-1 (4)
If OSR is odd number, M and OSR relation are：OSR=2*M+1.Tr_po_using[OSR-1:0] and dat_po_
using[OSR-1:0] relation is as follows：
Tr_po_using [(i+M) %OSR]=dat_po_using [i]
I=0,1 ... OSR-1 (5)
According to tr_po_update [OSR-1:0] with [OSR-1:0] relation obtains lead and lag indication signal up_
Voter and dn_voter.For convenience of description, we are presented in Fig. 4 an OSR=5 example.As shown in Fig. 4 (a), it is
The data being used of uniting are 0 position along position, i.e., now system thinks data along generation in 0 position.When data are along because make an uproar
The influence of sound is offset, if data are displaced to 1 position along (we are referred to as current data along tr_po_update), number
Deviation according to edge is 1 over-sampling clock phase, and is that direction along position towards increase is moved, and we are designated as phase advanced 1
Individual phase, i.e. up_voter [0]=1.As shown in Fig. 4 (c), if data edge is displaced to 2 positions (relative to tr_po_using
Offset by 2 over-sampling phases), and be that direction along position towards increase is moved, we are designated as advanced 2 phases of phase, i.e.,
Up_voter [1]=1.As shown in Fig. 4 (b), for data along 1 phase is moved towards the direction of reduction, we are designated as delayed phase 1
Individual phase, i.e. dn_voter [0]=1.As shown in Fig. 4 (d), along 2 phases are moved towards the direction of reduction, we are designated as data
2 phases of delayed phase, i.e. dn_voter [1]=1.
For other OSR values, up_voter, dn_voter and tr_po_update and tr_po_ are we illustrated
Using relation is as follows：
If OSR is even number.
up_voter[M-1:0] can be represented by formula below (＆ represents step-by-step and % represents complementation)：
Up_voter [k]=(tr_po_update [(i+k+1) %OSR]s ＆tr_po_using [i])
K=0,1 ... M-1；I=0,1 ... OSR-1. (6)
dn_voter[M-1:0] can be represented by formula below (＆ represents step-by-step and % represents complementation)：
Dn_voter [k]=(tr_po_update [i]s ＆tr_po_using [(i+k) %OSR])
K=0,1 ... M-1；I=0,1 ... OSR-1. (7)
If OSR is odd number.
up_voter[M-1:0] can be represented by formula below (＆ represents step-by-step and % represents complementation)：
Up_voter [k]=(tr_po_update [(i+k+1) %OSR]s ＆tr_po_using [i])
K=0,1 ... M-1；I=0,1 ... OSR-1. (8)
dn_voter[M-1:Can 0] be represented by formula below (| represent step-by-step or, ＆ represents step-by-step and % represents to ask
It is remaining)：
Up_voter [k]=(tr_po_update [i]s ＆tr_po_using [(i+k+1) %OSR])
K=0,1 ... M-1；I=0,1 ... OSR-1. (9)
Up_voter [0]=1 represents that weighted value is 1 unit, and up_voter [1]=1 represents that weighted value is 2 units,
By that analogy.
Dn_voter [0]=1 represents that weighted value is 1 unit, and dn_voter [1]=1 represents that weighted value is 2 units,
By that analogy.
Each timeticks, integrator are directed to up_voter [M-1:0] and dn_voter [M-1:0] give respectively above-mentioned
Weight is added up.Integrator is divided into the advanced integrator of phase and delayed phase integrator.The advanced integrator of phase is to up_
voter[M-1:0] weight characterized is added up.Delayed phase integrator is to dn_voter [M-1:0] added up.If phase
The advanced integrator in position overflows, then " the data center position being used " dat_po_using moves a phase towards augment direction
Position.If delayed phase integrator overflows, then dat_po_using moves a phase towards direction is reduced.
Picked up from over-sampling data according to " the data center position being used " and obtain effective data.If dat_po_
Using [0]=1, then it is data [0], data [0+OSR] ... data [0+ (K-1) * OSR] to pick up the valid data obtained.They
Relation can be expressed as follows：
Dat_po_using if [i]=1, i=0,1,2 ... OSR-1. so picks up the valid data obtained by Port Multiplier
For data [i+j*OSR], j=0,1 ... K-1.The parallel data bit numbers N of K and deserializer relation is expressed as：N=OSR*K.
FIFO is a pushup storage.Because local recovery data clock is not same with sending data clock
Clock, will necessarily exist asynchronous.FIFO be for the nonsynchronous situation of this clock, and will recover data syn-chronization to it is local when
Zhong Shang.Therefore, FIFO input is the data of a variable-length, and FIFO output is fixed-length data.
According to FIFO loading condition, FIFO " half_empty " and half-full " half_full " signal in midair can be provided.
It is empty that " half_empty " represents that FIFO is soon read." half_full " represents that FIFO is soon fully written.
Phase-interpolation controller is a L bits accumulators acc1.In each timeticks, if half_empty
=1, acc1=acc1-1；If half_full=1, acc1=acc1+1.O bits are taken from acc1 as pi_ctl [O-
1:0]。
pi_ctl[O-1:0] input as phase interpolator controls clks [OSR-1:0] phase place change.Phase is inserted
The clock phase of value device is expressed as following relational expression with Pi_ctl_va and phaselocked loop output clock pll_clk.Wherein, Pi_
Ctl_va is pi_ctl [O-1:0] decimal value.F0 is the frequency that phaselocked loop exports clock pll_clk：
Same or analogous label corresponds to same or analogous part；
Position relationship is used for being given for example only property explanation described in accompanying drawing, it is impossible to is interpreted as the limitation to this patent；
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (7)
1. a kind of clock data recovery system, it is characterised in that including phaselocked loop and some circuit-switched data passages, each circuit-switched data is led to
Road includes differential signal receiving port, balanced device, the deserializer being sequentially connected with, along detection module, almost linear phase detectors, product
Divide device；The phaselocked loop provides clock for each circuit-switched data passage；Each circuit-switched data passage also includes Port Multiplier, memory
FIFO, phase difference value device and phase difference value controller, the output of the input of Port Multiplier and the output end of deserializer and integrator
End connection, the output of integrator also feed back to almost linear phase detectors, and memory FIFO output end and phase difference value control
Device, the input of phase difference value device are also connected with phase difference value controller and phaselocked loop respectively, the output end of phase difference value device with
Deserializer connects；Differential signal receiving port in each circuit-switched data passage is also associated with matching impedance.
2. clock data recovery system according to claim 1, it is characterised in that the treated serial differential of equalised device
Signal needs to be changed into speed parallel signals by deserializer to facilitate the subsequent treatment of system, and the process is：
Deserializer is believed the serial differential that equalised device treats under timeticks clks control with certain multiplying power OSR
Number over-sampling is carried out, the data that the treated serial differential signals of equalised device obtain after over-sampling, be converted into after frequency reducing
Parallel signal, the serial data after over-sampling, data [N-1 are successively placed on by the priority of sampling:0], parallel data data [N-1:
0] exported by a synchronous module cko all the time from deserializer.
3. clock data recovery system according to claim 2, it is characterised in that it is described along detection module to data [N-
1:0] data are carried out along whether upset occurs being monitored, the process is：
By comparing parallel data data [N-1:0] whether two bit data are identical before and after, overturn judging data edge
Whether；If front and rear two bit data are identicals, represent that the upset on data edge does not occur for this data moment；If front and rear two
Bit data are different, then it represents that the upset that data edge is carved with during this data occurs：
Tr_position [X]=Data [X] ^Data [X-1] X=2~N-1 (1)
Tr_position [0]=Data [0] ^Data` [X-1] (2)
Wherein, Data'[N-1] represent upper timeticks cko N-1bit data.
4. clock data recovery system according to claim 3, it is characterised in that the almost linear phase detectors logarithm
Counted within a certain period of time according to the probability of the position occurred along upset, the probability of position of the data along upset occurs according to mistake
The ratio OSR of sampling is designated as P0, P1, P2……POSR-1, P0, P1, P2……POSR-1It is shown as the following formula：
Pi=∑ tr-positioni+j*OSRI=0,1 ... OSR-1, j=0 ..., K-1 (3)
Wherein, N=OSR*K, K are the integer more than or equal to 1, within the timing statisticses cycle, Data flipping probability of happening maximum
Current location of the position as data edge, represent variable tr_po_update [OSR-1 of the data along position:0] by correspondence position
For " 1 ", remaining position is " 0 "；If P1It is P0, P1, P2……POSR-1Middle the maximum, then the current location on data edge is phase 1,
So tr_po_update [1] is set to " 1 ", tr_po_update [0] and tr_po_update [OSR-1:2] it is " 0 ".
5. clock data recovery system according to claim 4, it is characterised in that the system is with the data being used
Heart position dat_po_using [OSR-1:0], picked up from over-sampling data and obtain effective data, the data center being used
Position dat_po_using [OSR-1:0] with the data that are used along position tr_po_using [OSR-1:0], dat_po_
using[OSR-1:0] and tr_po_using [OSR-1:0] relation is as follows：
If OSR is even number：
Tr_po_using [(i+M) %OSR]=dat_po_using [i], i=0,1 ... OSR-1
If OSR is odd number：
Tr_po_using [(i+M) %OSR]=dat_po_using [i], i=0,1 ... OSR-1
According to tr_po_update [OSR-1:0] with [OSR-1:0] relation obtains lead and lag indication signal up_voter
And dn_voter；
If OSR is even number：
up_voter[M-1:0] represented by formula below：
Up_voter [k]=(tr_po_update [(i+k+1) %OSR]s ＆tr_po_using [i])
K=0,1 ... M-1；I=0,1 ... OSR-1
dn_voter[M-1:0] represented by formula below：
Dn_voter [k]=(tr_po_update [i]s ＆tr_po_using [(i+k) %OSR])
K=0,1 ... M-1；I=0,1 ... OSR-1
If OSR is odd number：
up_voter[M-1:0] represented by formula below：
Up_voter [k]=(tr_po_update [(i+k+1) %OSR]s ＆tr_po_using [i])
K=0,1 ... M-1；I=0,1 ... OSR-1
dn_voter[M-1:0] represented by formula below：
Up_voter [k]=(tr_po_update [i]s ＆tr_po_using [(i+k+1) %OSR])
K=0,1 ... M-1；I=0,1 ... OSR-1
Up_voter [0]=1 represents that weighted value is 1 unit, and up_voter [1]=1 represents that weighted value is 2 units, with this
Analogize；
Dn_voter [0]=1 represents that weighted value is 1 unit, and dn_voter [1]=1 represents that weighted value is 2 units, with this
Analogize；
Integrator is directed to up_voter [M-1:0] and dn_voter [M-1:0] give above-mentioned weight respectively to be added up, integrator
It is divided into the advanced integrator of phase and delayed phase integrator, the advanced integrator of phase is to up_voter [M-1:0] weight characterized
Added up, delayed phase integrator is to dn_voter [M-1:0] added up；If the advanced integrator of phase overflows, then
" the data center position being used " dat_po_using moves a phase towards augment direction；If delayed phase integrator
Overflow, then dat_po_using moves a phase towards direction is reduced；
Picked up from over-sampling data according to " the data center position being used " and obtain effective data, if dat_po_using
[0]=1, then it is data [0], data [0+OSR] ... data [0+ (K-1) * OSR] to pick up the valid data obtained.Their pass
System can be expressed as follows：
Dat_po_using if [i]=1, i=0,1,2 ... OSR-1. so picks up the valid data obtained by Port Multiplier and is
The parallel data bit numbers N of data [i+j*OSR], j=0,1 ... K-1, K and deserializer relation is expressed as：N=OSR*K.
6. clock data recovery system according to claim 5, it is characterised in that the memory FIFO is one and first entered
First go out memory, FIFO input is the data of a variable-length, and FIFO output is fixed-length data.
7. clock data recovery system according to claim 6, it is characterised in that the phase-interpolation controller is one
Accumulator.
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