CN107659392B - clock data recovery system - Google Patents

clock data recovery system Download PDF

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CN107659392B
CN107659392B CN201710146950.9A CN201710146950A CN107659392B CN 107659392 B CN107659392 B CN 107659392B CN 201710146950 A CN201710146950 A CN 201710146950A CN 107659392 B CN107659392 B CN 107659392B
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data
osr
phase
voter
integrator
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CN107659392A (en
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吴启明
王添平
林晓志
周垣
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

the invention provides a clock data recovery system, which comprises a phase-locked loop and a plurality of data channels, wherein each data channel comprises a differential signal receiving port, an equalizer, a deserializer, an edge detection module, a quasi-linear phase detector and an integrator which are connected in sequence; the phase-locked loop is connected with the differential signal receiving port of each data channel; each data channel further comprises a multiplexer, a memory FIFO, a phase interpolator and a phase interpolation controller, wherein the input end of the multiplexer is connected with the output end of the deserializer and the output end of the integrator, the output of the integrator is fed back to the quasi-linear phase detector, the output end of the memory FIFO is connected with the phase interpolation controller, the input end of the phase interpolator is respectively connected with the phase interpolation controller and the phase-locked loop, and the output end of the phase interpolator is connected with the deserializer; and the output end of the differential signal receiving port in each data channel is also connected with matching impedance.

Description

Clock data recovery system
Technical Field
the present invention relates to the field of data communication, and more particularly, to a clock data recovery system.
background
The clock data recovery system is an indispensable part in a high-speed communication system. The existing common clock recovery system comprises a clock recovery system based on a phase-locked loop structure and a blind oversampling clock data recovery system. The clock recovery system based on the phase-locked loop structure can achieve good frequency following when the transmitter and the receiver have frequency deviation. However, the phase-locked loop structure requires a larger chip area implementation and thus requires a larger cost. Blind oversampling clock data recovery systems require less chip area, however, in the presence of frequency offset between the transmitter and receiver, the system cannot recover the data correctly. It is common practice for the transmitter to transmit a reference frequency to the receiver at the same time as the data is being transmitted. And receiving according to the reference frequency, so that the frequencies of the transmitting end and the receiving end are consistent. This requires an additional channel for the reference frequency, which adds additional cost to the system.
Disclosure of Invention
The invention provides a clock data recovery system with good robustness and stability.
In order to achieve the technical effects, the technical scheme of the invention is as follows:
a clock data recovery system comprises a phase-locked loop and a plurality of data channels, wherein each data channel comprises a differential signal receiving port, an equalizer, a deserializer, an edge detection module, a quasi-linear phase detector and an integrator which are sequentially connected; the phase-locked loop is connected with a differential signal receiving port of each data channel; each data channel further comprises a multiplexer, a memory FIFO, a phase interpolator and a phase interpolation controller, wherein the input end of the multiplexer is connected with the output end of the deserializer and the output end of the integrator, the output of the integrator is fed back to the quasi-linear phase detector, the output end of the memory FIFO is connected with the phase interpolation controller, the input end of the phase interpolator is respectively connected with the phase interpolation controller and the phase-locked loop, and the output end of the phase interpolator is connected with the deserializer; and the output end of the differential signal receiving port in each data channel is also connected with matching impedance.
Further, the serial differential signal processed by the equalizer needs to be converted into a low-speed parallel signal by the deserializer to facilitate the subsequent processing of the system, and the process is as follows:
under the control of clock ticks, the deserializer oversamples the serial differential signal processed by the equalizer with a certain multiplying power OSR, and the data obtained after the oversampling of the serial differential signal processed by the equalizer is converted into parallel signals after frequency reduction: the oversampled serial data are sequentially put in data [ N-1:0] according to the sampling sequence, the parallel data [ N-1:0] are output from the deserializer through a synchronous clock module cko, and the data rate cannot be changed before and after the deserializer processes the data.
Further, the edge detection module performs data edge roll-over monitoring on the data [ N-1:0], and the process is as follows:
Judging whether the data edge is turned over or not by comparing whether the front and back two-bit data of the parallel data [ N-1:0] are the same or not; if the front and back bit data are the same, the data is indicated that the data edge is not turned over at the moment; if the front and back two bits of data are different, the data is indicated to have the data edge overturn at the moment:
tr_position[X]＝Data[X]^Data[X-1]X＝2～N-1 (1)
tr_position[0]＝Data[0]^Data'[N-1] (2)
wherein Data' N-1 represents the N-1bit Data of the last clock tick cko.
Further, the quasi-linear phase detector counts the probability of the position where the data edge flip occurs within a certain time, and the probability of the position where the data edge flip occurs is recorded as P according to the oversampling ratio OSR0，P1，P2……POSR-1，P0，P1，P2……POSR-1As shown in the following equation:
Pi＝∑tr-positioni+j*OSR i＝0,1,…OSR-1,j＝0,…,K-1 (3)
wherein, N is OSR K, K is an integer greater than or equal to 1, in the statistical time period, the position with the maximum data turnover occurrence probability is taken as the current position of the data edge, and a variable tr _ po _ update [ OSR-1:0] representing the position of the data edge]Setting the corresponding position as '1' and the rest positions as '0'; if P1Is P0，P1，P2……POSR-1the largest, then the current position of the data edge is phase 1, then Tr _ po _ update [1]]Set to "1", Tr _ po _ update [0]and Tr _ po _ update [ OSR-1:2]Is "0".
Further, the system uses the data center location in use, dat _ po _ using [ OSR-1:0], to retrieve valid data from the over-sampled data, and the data center location in use, dat _ po _ using [ OSR-1:0], corresponds to the data in use along the locations Tr _ po _ using [ OSR-1:0], dat _ po _ using [ OSR-1:0], and Tr _ po _ using [ OSR-1:0], as follows:
If OSR is even, i.e. OSR 2M, or if OSR is odd, i.e. OSR 2M +1, there are:
Tr_po_using[(i+M)％OSR]＝dat_po_using[i]，i＝0,1…OSR-1.
obtaining leading and lagging indication signals Up _ voter and dn _ voter according to the relation between Tr _ po _ update [ OSR-1:0] and Tr _ po _ using [ OSR-1:0 ];
if OSR is even:
up _ voter [ M-1:0] is represented by the following formula:
Up_voter[k]＝Σ(Tr_po_update[(i+k+1)％OSR]&Tr_po_using[i])
k＝0,1,……M-1；i＝0,1……OSR-1.
dn _ voter [ M-1:0] is represented by the following formula:
dn_voter[k]＝Σ(Tr_po_update[i]&Tr_po_using[(i+k)％OSR])
k＝0,1,……M-1；i＝0,1……OSR-1.
If OSR is odd:
Up _ voter [ M-1:0] is represented by the following formula:
Up_voter[k]＝Σ(Tr_po_update[(i+k+1)％OSR]&Tr_po_using[i])
k＝0,1,……M-1；i＝0,1……OSR-1.
dn _ voter [ M-1:0] is represented by the following formula:
dn_voter[k]＝Σ(Tr_po_update[i]&Tr_po_using[(i+k+1)％OSR])
k＝0,1,……M-1；i＝0,1……OSR-1.
Up _ voter [0] ═ 1 denotes a weight of 1 unit, Up _ voter [1] ═ 1 denotes a weight of 2 units, and so on;
dn _ voter [0] ═ 1 denotes a weight of 1 unit, dn _ voter [1] ═ 1 denotes a weight of 2 units, and so on;
the integrator respectively gives the weights to the Up _ voter [ M-1:0] and the dn _ voter [ M-1:0] for accumulation, the integrator is divided into a phase lead integrator and a phase lag integrator, the phase lead integrator accumulates the weight represented by the Up _ voter [ M-1:0], and the phase lag integrator accumulates the dn _ voter [ M-1:0 ]; if the phase lead integrator overflows, then the "data center location in use" dat _ po _ using is shifted one phase in the increasing direction; if the phase lag integrator overflows, dat _ po _ using is shifted in the decreasing direction by one phase;
Valid data is picked up from the oversampled data according to the "data center location in use", and if dat _ po _ using [0] is 1, the picked up valid data is data [0], data [0+ OSR ] … … data [0+ (K-1) × OSR ]. Their relationship can be expressed as follows:
if dat _ po _ using [ i ] ═ 1, i ═ 0,1,2 … … OSR-1, then the valid data picked up by the multiplexer is data [ i + j × OSR ], j ═ 0,1 … … K-1, and the relation between K and the number N of parallel data bits of the deserializer is expressed as: n ═ OSR × K.
further, the memory FIFO is a first-in first-out memory, the input of the FIFO is a variable length data, and the output of the FIFO is a fixed length data.
Preferably, the phase interpolation controller is an accumulator.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
the phase-locked loop comprises a phase-locked loop and a plurality of data channels, wherein each data channel comprises a differential signal receiving port, an equalizer, a deserializer, an edge detection module, a quasi-linear phase detector and an integrator which are connected in sequence; the phase-locked loop is connected with a differential signal receiving port of each data channel; each data channel further comprises a multiplexer, a memory FIFO, a phase interpolator and a phase interpolation controller, wherein the input end of the multiplexer is connected with the output end of the deserializer and the output end of the integrator, the output of the integrator is fed back to the quasi-linear phase detector, the output end of the memory FIFO is connected with the phase interpolation controller, the input end of the phase interpolator is respectively connected with the phase interpolation controller and the phase-locked loop, and the output end of the phase interpolator is connected with the deserializer; and the output end of the differential signal receiving port in each data channel is also connected with matching impedance. The invention improves the noise tolerance of the system well, so that the system has better robustness and stability in a severe noise environment.
Drawings
FIG. 1 is a block diagram of a data channel according to the present invention;
FIG. 2 is a schematic diagram of oversampling at a certain magnification OSR in the present invention;
FIG. 3 is a graph showing the relationship between Tr _ po _ using [ OSR-1:0] and dat _ po _ using [ OSR-1:0] in the present invention;
FIG. 4(a) is a schematic diagram of the operation of the system of the present invention in which the position of the data edge is 0;
FIG. 4(b) is a schematic diagram of the system of the present invention with data shifted by 1 phase in the decreasing direction;
FIG. 4(c) is a schematic diagram of the operation of the system of the present invention if the data edge is shifted to 2 positions;
FIG. 4(d) is an operational diagram of the system of the present invention with data shifted in the decreasing direction by 2 phases.
Detailed Description
the drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
It will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
example 1
as shown in fig. 1, the system of the present invention includes a common phase locked loop that provides a clock source and a plurality of data channels 1-N. Rxp and Rxn are differential signal receiving ports of one data lane. Each data lane has a respective differential signal receiving port. The signal receiving port connects an impedance matched to the channel to a fixed voltage node.
The signal receiving port also serves as an input of the equalizer. The equalizer is used to compensate for the loss of frequency components when the signal is transmitted over the channel. The output of the equalizer is eqp and eqn. If the transmission rate of the signal is low, or the channel quality is good and the frequency loss is small, the equalizer can be replaced by a buffer. The Buffer is used for providing enough voltage driving capability for the next-stage module.
eqp and eqn are also inputs to the deserializer. The deserializer converts the serial differential signals at eqp and eqn into the output of a parallel signal, which is data [ N-1:0], at a certain clock beat. Clks provides clock ticks for the deserializer. The high-speed serial signal needs to be converted into a low-speed parallel signal by the deserializer to facilitate the subsequent processing of the system. In the deserializer, the high speed serial signal (the input signal to the deserializer) is oversampled at a certain rate OSR under the control of the clock ticks, as shown in fig. 2. The data obtained by over-sampling the serial signal is converted into parallel signals after frequency reduction, namely the data [ N-1:0 ]. The parallel signal data [ N-1:0] is data that has been subjected to cko synchronization. Cko is a relatively slow speed clock relative to clks. The oversampled serial data are sequentially put in data [ N-1:0] according to the sampling sequence. The data rate does not change before and after the deserializer process.
edge detection is a module that provides a data flip edge indication signal in the system. The output signal tr _ position [ N-1:0] of the edge detection module represents whether the data edge is inverted in the input data [ N-1:0 ]. the tr _ position [ N-1:0] can be given a principle description by equations (1) and (2). Whether the data edge is overturned or not is judged by comparing whether the front and back two-bit data of the parallel data [ N-1:0] are the same or not. If the two previous and next bits of data are the same, it indicates that the data edge is not turned at the moment. If the two bit data before and after are different, it indicates that the data is turned over by the data edge at the moment.
tr_position[X]＝Data[X]^Data[X-1]X＝2～N-1 (1)
tr_position[0]＝Data[0]^Data'[N-1] (2)
Where Data' N-1 represents the N-1bit Data of the last clock tick cko.
for a system with an oversampling ratio of OSR, the relationship between N and OSR is: n ═ OSR × K. K is an integer of 1 or more.
The quasi-linear phase detector has a faster loop response than a conventional bang-bang phase detector. The quasi-linear phase detector gives a quasi-linear weight weighted according to the probability of the data along the flip position.
first, a quasi-linear phase detector counts the probability of the data along the position where the flip occurs within a certain time. The probability of the position where the data edge flip occurs is noted as P from the oversampled ratio OSR0，P1，P2……POSR-1。P0，P1，P2……POSR-1As shown in the following equation:
Pi＝∑tr-positioni+j*OSRi＝0,1,…OSR-1,j＝0,…,K-1 (3)
And in a certain statistical time period, the position with the maximum data turnover occurrence probability is used as the current position of the data edge. Variable Tr _ po _ update [ OSR-1:0] representing the location of the data edge]the corresponding position is set to "1", and the remaining positions are set to "0". Such as P1Is P0，P1，P2……POSR-1The largest one, then the current position of the data edge is considered to be phase 1. Then Tr _ po _ update [1]]Set to "1", Tr _ po _ update [0]And Tr _ po _ update [ OSR-1:2]is "0".
And the system has an "in-use data center location". The system uses this "in-use data center location" to pick up valid data from the over-sampled data. And there is a "data edge location in use" corresponding to the "data center location in use". We note the "data center location in use" as dat _ po _ using [ OSR-1:0 ]. Let us note that the "data edge position being used" is Tr _ po _ using [ OSR-1:0 ]. Their relationship is shown in fig. 3. For convenience of presentation, we give an example of OSR ═ 5. If the "in-use data center location" is the phase 2 oversampling clock location, the valid data is the data obtained from the phase 2 oversampling clock location. Then the "in-use data edge position" is the phase 0 oversampling clock position. At this time, let dat _ po _ using [2] be 1, and the rest bits in dat _ po _ using be 0. Let us remember Tr _ po _ using [0] as 1, and the remaining bits in Tr _ po _ using are noted as 0. Similarly, if the "data center location in use" is the phase 1 oversampling clock location, the valid data is the data obtained from the phase 1 oversampling clock location. Then the "in-use data edge position" is the phase 4 oversampling clock position. At this time, let us remember that dat _ po _ using [1] ═ 1, and the remaining bits in dat _ po _ using are 0. Let us remember Tr _ po _ using [4] ═ 1, and the remaining bits in Tr _ po _ using are noted as 0. The OSR may be either an odd number or an even number. According to the OSR being odd and even, the relationship of dat _ po _ using [ OSR-1:0] and Tr _ po _ using [ OSR-1:0] is given as follows:
If OSR is even, the relationship between M and OSR is: OSR 2 × M. Tr _ po _ using [ OSR-1:0] and dat _ po _ using [ OSR-1:0] are as follows (% represents a remainder):
Tr_po_using[(i+M)％OSR]＝dat_po_using[i]
i＝0,1……OSR-1……(4)
If OSR is odd, the relationship between M and OSR is: OSR 2 × M + 1. Tr _ po _ using [ OSR-1:0] and dat _ po _ using [ OSR-1:0] are as follows:
Tr_po_using[(i+M)％OSR]＝dat_po_using[i]
i＝0,1……OSR-1……(5)
the lead and lag indicating signals Up _ voter and dn _ voter are obtained from the relationship of Tr _ po _ update [ OSR-1:0] and [ OSR-1:0 ]. For convenience of explanation, we give an example of OSR ═ 5 in fig. 4. As shown in fig. 4(a), the position of the data edge being used by the system is 0 position, i.e. the system considers the data edge to occur at 0 position. When the data edge is shifted due to the influence of noise, if the data edge (we refer to the current data edge Tr _ po _ update) is shifted to 1 position, the data edge is shifted by 1 over-sampling clock phase and is shifted in the direction of increasing position, which is expressed as a phase advance by 1 phase, i.e., Up _ voter [0] is 1. As shown in fig. 4(c), if the data is shifted to 2 positions (shifted by 2 oversampling phases with respect to Tr _ po _ using) and is shifted in the direction of increasing position, we say that the phase is advanced by 2 phases, i.e., up _ voter [1] ═ 1. As shown in fig. 4(b), the data is shifted in the decreasing direction by 1 phase, which is expressed as a phase lag of 1 phase, i.e., dn _ voter [0] ═ 1. As shown in fig. 4(d), the data is shifted in the decreasing direction by 2 phases, which we denote as phase lag by 2 phases, i.e., dn _ voter [1] ═ 1.
For other OSR values, we give Up _ voter, dn _ voter relationships to Tr _ po _ update and Tr _ po _ using as follows:
If OSR is even:
up _ voter [ M-1:0] is represented by the following formula (& represents bitwise AND,% represents remainder):
Up_voter[k]＝Σ(Tr_po_update[(i+k+1)％OSR]&Tr_po_using[i])
k＝0,1,……M-1；i＝0,1……OSR-1.…(6)
dn _ voter [ M-1:0] is represented by the following formula:
dn_voter[k]＝Σ(Tr_po_update[i]&Tr_po_using[(i+k)％OSR])
k＝0,1,……M-1；i＝0,1……OSR-1.…(7)
If OSR is odd:
up _ voter [ M-1:0] is represented by the following formula:
Up_voter[k]＝Σ(Tr_po_update[(i+k+1)％OSR]&Tr_po_using[i])
k＝0,1,……M-1；i＝0,1……OSR-1…(8)
dn _ voter [ M-1:0] is represented by the following formula:
dn_voter[k]＝Σ(Tr_po_update[i]&Tr_po_using[(i+k+1)％OSR])
k＝0,1,……M-1；i＝0,1……OSR-1.…(9)
up _ voter [0] ═ 1 denotes a weight of 1 unit, Up _ voter [1] ═ 1 denotes a weight of 2 units, and so on.
dn _ voter [0] ═ 1 denotes a weight of 1 unit, dn _ voter [1] ═ 1 denotes a weight of 2 units, and so on.
For each clock beat, the integrator gives the weights for Up _ voter [ M-1:0] and dn _ voter [ M-1:0], respectively, to accumulate. The integrators are divided into a phase lead integrator and a phase lag integrator. The phase lead integrator accumulates the weights characterized by Up _ voter [ M-1:0 ]. The phase lag integrator accumulates dn _ voter M-1: 0. If the phase lead integrator overflows, the "data center position in use" dat _ po _ using is shifted in the increasing direction by one phase. If the phase lag integrator overflows, dat _ po _ using is shifted in the decreasing direction by one phase.
Valid data is picked up from the oversampled data according to the "in-use data centre location". If dat _ po _ using [0] ═ 1, the valid data picked up is data [0], data [0+ OSR ] … … data [0+ (K-1) × OSR ]. Their relationship can be expressed as follows:
if dat _ po _ using [ i ] ═ 1, i ═ 0,1,2 … … OSR-1, then the valid data picked up by the multiplexer is data [ i + j × OSR ], j ═ 0,1 … … K-1. The relation between K and the parallel data bit number N of the deserializer is expressed as follows: n ═ OSR × K.
the FIFO is a first-in first-out memory. Since the local recovered data clock is not the same clock as the transmitted data clock, there must be a lack of synchronization. The FIFO is for this clock-out-of-sync condition and synchronizes the recovered data to the local clock. Thus, the input to the FIFO is a variable length of data and the output of the FIFO is a fixed length of data.
according to the loading condition of the FIFO, signals of half empty 'half _ empty' and half full 'half _ full' of the FIFO can be given. "half _ empty" indicates that the FIFO is about to be read empty. "half _ full" indicates that the FIFO is about to be filled.
the phase interpolation controller is a Lbits accumulator acc 1. In each clock beat, if half _ empty is 1, acc1 is acc 1-1; if half _ full is 1, acc1 is acc1+ 1. Take the Obits from acc1 as pi _ ctl [ O-1:0 ].
pi _ ctl [ O-1:0] as the input to the phase interpolator controls the phase change of clks [ OSR-1:0 ]. The clock phases of the phase interpolator, Pi _ ctl _ va and the pll _ clk output are expressed as follows. Wherein Pi _ ctl _ va is the decimal value of Pi _ ctl [ O-1:0 ]. f0 is the frequency of the phase locked loop output clock pll _ clk:
The same or similar reference numerals correspond to the same or similar parts;
the positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the present patent;
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims (7)

1. a clock data recovery system is characterized by comprising a phase-locked loop and a plurality of data channels, wherein each data channel comprises a differential signal receiving port, an equalizer, a deserializer, an edge detection module, a quasi-linear phase detector and an integrator which are connected in sequence; the phase-locked loop is connected with a differential signal receiving port of each data channel; each data channel further comprises a multiplexer, a memory FIFO, a phase interpolator and a phase interpolation controller, wherein the input end of the multiplexer is connected with the output end of the deserializer and the output end of the integrator, the output of the integrator is fed back to the quasi-linear phase detector, the output end of the memory FIFO is connected with the phase interpolation controller, the input end of the phase interpolator is respectively connected with the phase interpolation controller and the phase-locked loop, and the output end of the phase interpolator is connected with the deserializer; and the output end of the differential signal receiving port in each data channel is also connected with matching impedance.
2. the clock data recovery system according to claim 1, wherein the serial differential signal processed by the equalizer needs to be converted into a low-speed parallel signal by the deserializer to facilitate subsequent processing of the system by:
under the control of clock ticks, the deserializer oversamples the serial differential signal processed by the equalizer with a certain multiplying power OSR, and the data obtained after the oversampling of the serial differential signal processed by the equalizer is converted into parallel signals after frequency reduction: the oversampled serial data are sequentially put in data [ N-1:0] according to the sampling sequence, the parallel data [ N-1:0] are output from the deserializer through a synchronous clock module cko, and the data rate cannot be changed before and after the deserializer processes the data.
3. the clock data recovery system according to claim 2, wherein the edge detection module monitors data [ N-1:0] for data edge roll-over, and the process is as follows:
Judging whether the data edge is turned over or not by comparing whether the front and back two-bit data of the parallel data [ N-1:0] are the same or not; if the front and back bit data are the same, the data is indicated that the data edge is not turned over at the moment; if the front and back two bits of data are different, the data is indicated to have the data edge overturn at the moment:
tr_position[X]＝Data[X]^Data[X-1] X＝2～N-1 (1)
tr_position[0]＝Data[0]^Data'[N-1] (2)
wherein Data' N-1 represents the N-1bit Data of the last clock tick cko.
4. the clock data recovery system according to claim 3, wherein the quasi-linear phase detector counts the probability of the position where the data edge flip occurs over a certain time, and the probability of the position where the data edge flip occurs is denoted as P according to the oversampling ratio OSR0，P1，P2……POSR-1，P0，P1，P2……POSR-1As shown in the following equation:
Pi＝∑tr-positioni+j*OSR i＝0,1,···OSR-1,j＝0,···,K-1 (3)
wherein, N is OSR K, K is an integer greater than or equal to 1, in the statistical time period, the position with the maximum data turnover occurrence probability is taken as the current position of the data edge, and a variable Tr _ po _ update [ OSR-1:0] representing the position of the data edge]setting the corresponding position as '1' and the rest positions as '0'; if P1is P0，P1，P2……POSR-1the largest, then the current position of the data edge is phase 1, then Tr _ po _ update [1]]set to "1", Tr _ po _ update [0]and Tr _ po _ update [ OSR-1:2]is "0".
5. The clock data recovery system according to claim 4, wherein the system is configured to retrieve valid data from the oversampled data using the in-use data center location dat _ po _ using [ OSR-1:0], the in-use data center location dat _ po _ using [ OSR-1:0] corresponding to the in-use data along the positions Tr _ po _ using [ OSR-1:0], dat _ po _ using [ OSR-1:0] and Tr _ po _ using [ OSR-1:0] as follows:
if OSR is even, i.e. OSR 2M, or if OSR is odd, i.e. OSR 2M +1, there are:
Tr_po_using[(i+M)％OSR]＝dat_po_using[i]，i＝0,1…OSR-1.
Obtaining leading and lagging indication signals Up _ voter and dn _ voter according to the relation between Tr _ po _ update [ OSR-1:0] and Tr _ po _ using [ OSR-1:0 ];
If OSR is even:
up _ voter [ M-1:0] is represented by the following formula:
Up_voter[k]＝Σ(Tr_po_update[(i+k+1)％OSR]&Tr_po_using[i])
k＝0,1,……M-1；i＝0,1……OSR-1.
dn _ voter [ M-1:0] is represented by the following formula:
dn_voter[k]＝Σ(Tr_po_update[i]&Tr_po_using[(i+k)％OSR])
k＝0,1,……M-1；i＝0,1……OSR-1.
if OSR is odd:
Up _ voter [ M-1:0] is represented by the following formula:
Up_voter[k]＝Σ(Tr_po_update[(i+k+1)％OSR]&Tr_po_using[i])
k＝0,1,……M-1；i＝0,1……OSR-1.
dn _ voter [ M-1:0] is represented by the following formula:
dn_voter[k]＝Σ(Tr_po_update[i]&Tr_po_using[(i+k+1)％OSR])
k＝0,1,……M-1；i＝0,1……OSR-1.
Up _ voter [0] ═ 1 denotes a weight of 1 unit, Up _ voter [1] ═ 1 denotes a weight of 2 units, and so on;
dn _ voter [0] ═ 1 denotes a weight of 1 unit, dn _ voter [1] ═ 1 denotes a weight of 2 units, and so on;
The integrator respectively gives the weights to the Up _ voter [ M-1:0] and the dn _ voter [ M-1:0] for accumulation, the integrator is divided into a phase lead integrator and a phase lag integrator, the phase lead integrator accumulates the weight represented by the Up _ voter [ M-1:0], and the phase lag integrator accumulates the dn _ voter [ M-1:0 ]; if the phase lead integrator overflows, then the "data center location in use" dat _ po _ using is shifted one phase in the increasing direction; if the phase lag integrator overflows, dat _ po _ using is shifted in the decreasing direction by one phase;
According to the data center position in use, effective data is picked up from the over-sampled data, if dat _ po _ using [0] is 1, the picked-up effective data is data [0], data [0+ OSR ] … … data [0+ (K-1) × OSR ], and the relationship can be expressed as follows:
if dat _ po _ using [ i ] ═ 1, i ═ 0,1,2 … … OSR-1, then the valid data picked up by the multiplexer is data [ i + j × OSR ], j ═ 0,1 … … K-1, and the relation between K and the number N of parallel data bits of the deserializer is expressed as: n ═ OSR × K.
6. the clock data recovery system according to claim 5, wherein said memory FIFO is a first-in-first-out memory, the input of the FIFO is a variable length data, and the output of the FIFO is a fixed length data.
7. The clock data recovery system according to claim 6, wherein said phase interpolation controller is an accumulator.
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