CN116527038A - Digital clock frequency tracker and high-speed serial interface chip - Google Patents

Digital clock frequency tracker and high-speed serial interface chip Download PDF

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Publication number
CN116527038A
CN116527038A CN202310199151.3A CN202310199151A CN116527038A CN 116527038 A CN116527038 A CN 116527038A CN 202310199151 A CN202310199151 A CN 202310199151A CN 116527038 A CN116527038 A CN 116527038A
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China
Prior art keywords
clock signal
frequency
phase
recovered
local clock
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CN202310199151.3A
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Chinese (zh)
Inventor
冯飞
王浩南
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Jiyiwei Semiconductor Shanghai Co ltd
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Jiyiwei Semiconductor Shanghai Co ltd
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Priority to CN202310199151.3A priority Critical patent/CN116527038A/en
Publication of CN116527038A publication Critical patent/CN116527038A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The application relates to the technical field of integrated circuits and discloses a digital clock frequency tracker and a high-speed serial interface chip. The tracker includes: the counting frequency discriminator is used for acquiring the frequency-divided recovered clock signal recovered by the receiving end clock-data recovery circuit and the frequency-divided local clock signal generated by the sending end phase-locked loop, setting a corresponding target value, sampling the count value of the recovered clock signal after the count value of the local clock signal reaches the target value, and obtaining frequency offset information; the phase discriminator is used for setting a frequency division coefficient according to the frequency division ratio of the recovered clock signal and the local clock signal, and oversampling the recovered clock signal by using the local clock signal according to the frequency division coefficient to obtain phase information; and the digital low-pass filter is used for obtaining the frequency control word according to the frequency offset information, the phase information and the respective gains. The invention realizes the scheme of frequency tracking of receiving end data receiving frequency of transmitting end serial data transmission with high performance and low power consumption.

Description

Digital clock frequency tracker and high-speed serial interface chip
Technical Field
The present disclosure relates to integrated circuit technology, and in particular, to a digital clock frequency tracker and a high-speed serial interface chip.
Background
This section is intended to provide a background or context for embodiments of the present application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
The function of the high-speed serial interface chip applied to the re-timer is to strengthen the signal received by the receiving end and then send the strengthened signal to the next-stage equipment through the sending end at the other side. Because the local receiving end/transmitting end and the peripheral equipment use different reference clocks generated by crystal oscillators as clock sources, the local receiving end/transmitting end needs to adopt an extra clock frequency tracking scheme on the basis of generating a high-speed clock by using a phase-locked loop so as to ensure that the high-speed clock frequency of the received/transmitted data is consistent with that of the peripheral equipment of the opposite end, thereby realizing correct receiving, reinforcing and transmitting of the data. On the receiving side of the high-speed serial interface chip, CDR (clock data recovery) technology is generally adopted to directly recover the clock information in the received serial signal as a high-speed clock for locally receiving data. Since the transmitting side also needs to use the clock of the same frequency for serial data transmission, this high-speed clock needs to be transferred from the receiving side to the transmitting side for serial data transmission. In a high-speed serial interface chip, transferring such a high-speed clock requires a great deal of power consumption, and the performance is easily affected by factors such as crosstalk, noise, and the like. At present, the following two schemes are adopted for transmission:
1. and directly transmitting the high-speed clock recovered by the receiving end clock-data recovery circuit from the received data to the transmitting end to transmit the high-speed serial data. This solution requires the transfer of a high-speed clock signal, and as the data transfer rate of the chip increases, the frequency of this clock signal increases, and is therefore more difficult to implement in applications with higher transfer rates. Since the physical locations of the receiving end and the transmitting end in the chip may be far away, a multi-stage buffer is required to transmit the high-speed clock signal to ensure the quality of clock transmission, which means that high power consumption is required. In addition, in order to ensure the performance of high-speed clock transmission, the clock routing channel needs to be well designed and shielded, which also increases the design difficulty and the area consumption of the clock channel.
2. Dividing the frequency of a high-speed clock recovered by a receiving end clock-data recovery circuit from received data, and then transmitting the high-speed clock to a transmitting end; the phase-locked loop of the transmitting end locks the clock as a reference clock, and the transmitting end uses the output clock locked by the phase-locked loop as a high-speed clock for data transmission. The scheme reduces the frequency of the recovered clock transmitted from the receiving end to the transmitting end, so that the power consumption consumed by clock transmission can be reduced to a certain extent, but the clock transmitted to the transmitting end is used as a reference clock of a phase-locked loop, so that the quality of clock transmission is still a key factor for determining the data transmission performance of the transmitting end, and the design difficulty of a clock transmission channel is still great.
The invention provides a scheme for realizing the frequency tracking of the receiving end data receiving frequency of the transmitting end serial data transmission with high performance and low power consumption.
Disclosure of Invention
The purpose of the present application is to provide a digital clock frequency tracker, which greatly reduces the design difficulty of clock transmission, and can suppress the high-frequency noise in the recovered clock through a low-pass filter implemented in a digital circuit, thereby improving the performance of a transmitting end.
The application discloses a digital clock frequency tracker, including:
the counting frequency discriminator is used for acquiring a recovered clock signal obtained by frequency division of a clock signal recovered by the clock-data recovery circuit in the receiving end and a local clock signal obtained by frequency division of a clock signal generated by the phase-locked loop in the sending end, setting a corresponding target value according to the frequency division ratio of the recovered clock signal and the local clock signal, sampling the count value of the recovered clock signal after the count value of the local clock signal reaches the target value, and comparing the count value of the recovered clock signal with the count value of the local clock signal to obtain frequency offset information;
the phase discriminator is used for receiving the recovered clock signal after frequency division and the local clock signal after frequency division, setting a frequency division coefficient according to the frequency division ratio of the recovered clock signal and the local clock signal, oversampling the recovered clock signal according to the frequency division coefficient by using the local clock signal, and obtaining phase information according to an adopted result; and
and the digital low-pass filter is used for obtaining a frequency control word according to the frequency offset information, the phase information and the respective gains and outputting the frequency control word to the phase-locked loop of the transmitting end.
In a preferred embodiment, the method further comprises:
the frequency anomaly monitoring module is used for receiving the frequency-divided recovered clock signal and the frequency-divided local clock signal, setting corresponding target values according to the frequency division ratio of the recovered clock signal and the local clock signal, sampling the count value of the recovered clock signal after the count value of the local clock signal reaches the target value, closing the digital low-pass filter when the difference value between the count value of the recovered clock signal and the target value exceeds a preset range, and enabling the digital low-pass filter when the difference value between the count value of the recovered clock signal and the target value is within the preset range.
In a preferred embodiment, the target value of the recovered clock signal is four, six or eight times the target value of the local clock signal, and the target values of the recovered clock signal and the local clock signal set in the frequency anomaly monitoring module are smaller than the target values of the recovered clock signal and the local clock signal set in the count discriminator.
In a preferred embodiment, the count discriminator is further configured to reset the count value of the recovered clock signal and the count value of the local clock signal after sampling the count value of the recovered clock signal.
In a preferred embodiment, the target value of the recovered clock signal is four, six or eight times the target value of the local clock signal.
In a preferred embodiment, the phase detector performs over-sampling of the recovered clock signal by an integer multiple of four according to a frequency division coefficient using the local clock signal, the phase discrimination result is 0 when the sampling result is 000, 010, 101 or 111, the phase discrimination result is-1 when the sampling result is 001 or 110, the phase discriminator result is 1 when the sampling result is 011 or 100, and the phase discriminator sequentially outputs the phase discrimination result.
In a preferred embodiment, the phase discriminator uses the local clock signal to oversample the recovered clock signal by an integer multiple of non-four according to a frequency division coefficient, the phase discrimination result is 0 when the sampling result is 000, 010, 101 or 111, the phase discrimination result is-1 when the sampling result is 001 or 110, the phase discriminator result is 1 when the sampling result is 011 or 100, and the phase discriminator outputs from the first phase discrimination result sequentially with the integer multiple of non-four being spaced apart, and the other phase discrimination results are discarded.
In a preferred embodiment, the phase detector over-sampling the recovered clock signal by an integer multiple other than four according to a frequency division factor using the local clock signal further comprises: six-fold oversampling was performed.
The application also discloses a high-speed serial interface chip, including:
the clock-data recovery circuit is positioned at the receiving end and is used for recovering a high-speed clock of the receiving end;
the first frequency divider is used for dividing the frequency of the recovered high-speed clock to obtain a recovered clock signal after frequency division;
the phase-locked loop is positioned at the transmitting end and is used for generating a high-speed clock of the transmitting end;
the second frequency divider is used for dividing the frequency of the high-speed clock of the transmitting end to obtain a local clock signal after frequency division; and
a digital clock frequency tracker as hereinbefore described.
The embodiment of the application has the following beneficial effects:
1. the digital signal of the frequency control word is directly transmitted to the transmitting end, so that an analog signal transmission clock is not required to be used between the receiving end and the transmitting end, the design difficulty of clock transmission is reduced, and the power consumption of a clock transmission path is reduced.
2. The high frequency noise in the recovered clock can be suppressed by a low pass filter implemented in the digital circuit, thereby improving the transmission end performance.
3. The output frequency of the phase-locked loop of the transmitting end under the abnormal state can be maintained through the frequency abnormality monitoring module in the digital circuit, so that the phase-locked loop of the transmitting end is prevented from losing lock, and the transmitting end can quickly recover data transmission after the receiving end is recovered to be normal.
4. The digital circuit is used for carrying out frequency discrimination on the recovery clock of the receiving end and the local clock of the transmitting end, frequency information can be read out through software, and then converted into a frequency control word to directly configure the output frequency of the phase-locked loop of the transmitting end, so that software taking over is realized.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a schematic diagram of a digital clock frequency tracker in accordance with one embodiment of the present application.
Fig. 2 is a schematic diagram of the operational timing of a counting discriminator according to an embodiment of the application.
Fig. 3 is a schematic diagram of the phase detector operating principle in accordance with one embodiment of the present application.
Fig. 4 is a schematic diagram of the operating principle of the phase detector according to another embodiment of the present application.
Reference numerals illustrate:
100: digital clock frequency tracker
101: counting frequency discriminator
102: phase discriminator
103: digital low pass filter
104: frequency anomaly monitoring module
105: clock-data recovery circuit
106: first frequency divider
107: phase locked loop
108: second frequency divider
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
The following outline describes some of the innovative points of the embodiments of the present application:
the invention provides a method for extracting frequency information in a clock recovered by a receiving end clock-data recovery circuit by using a digital circuit, and adjusting the output frequency of a transmitting end phase-locked loop by changing a frequency control word of the transmitting end phase-locked loop, thereby realizing the purpose of tracking the data receiving frequency of the receiving end by the data transmitting frequency of the transmitting end. The scheme of extracting frequency information by adopting the digital circuit can directly transmit the digital signal to the transmitting end, so that an analog signal transmission clock is not required to be used between the receiving end and the transmitting end, the design difficulty of clock transmission is greatly reduced, and high-frequency noise in a recovered clock can be restrained through a low-pass filter realized in the digital circuit, thereby improving the performance of the transmitting end.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
One embodiment of the present application relates to a digital clock frequency tracker having a structure as shown in fig. 1, and the digital clock frequency tracker 100 includes: the counting frequency discriminator 101, the phase discriminator 102, the digital low pass filter 103, the counting frequency discriminator 101 and the phase discriminator 102 are coupled to the digital low pass filter 103, respectively. The count discriminator 101 is configured to obtain a recovered clock signal obtained by dividing a clock signal recovered by the clock-data recovery circuit 105 in the receiving end by the first frequency divider 106 and a local clock signal obtained by dividing a clock signal generated by the phase-locked loop 107 in the transmitting end by the second frequency divider 108, set a corresponding target value according to a division ratio of the recovered clock signal and the local clock signal, sample a count value of the recovered clock signal after the count value of the local clock signal reaches the target value, and obtain frequency offset information according to a comparison between the count value of the recovered clock signal and the count value of the local clock signal. The phase discriminator 102 acquires a recovered clock signal obtained by dividing the clock signal recovered by the clock-data recovery circuit 105 in the receiving end by the first frequency divider 106 and a local clock signal obtained by dividing the clock signal generated by the phase-locked loop 107 in the transmitting end by the second frequency divider 108, sets a division coefficient according to the division ratio of the recovered clock signal and the local clock signal, oversamples the recovered clock signal according to the division coefficient by using the local clock signal, and obtains phase information according to the adoption result. The digital low-pass filter 103 is used to obtain a frequency control word according to the frequency offset information, the phase information and the respective gains, and output the frequency control word to the phase-locked loop 107 at the transmitting end.
The clock-data recovery circuit 105 divides the recovered clock from the received serial data at the receiving end using the frequency divider 106 and transmits the divided clock to the digital clock frequency tracker 100 implemented by the digital circuit as a reference clock input. The high-speed clock generated by the transmitter pll 107 is divided by the frequency divider 108 at the transmitter and then transmitted to the digital clock frequency tracker 100 as well, and is used as a local clock to be adjusted. The digital clock frequency tracker 100 generates a frequency control word after frequency discrimination and phase discrimination of the two input clocks, and transmits the frequency control word to the transmitting-side phase-locked loop 107 to control the frequency of the output clock of the transmitting-side phase-locked loop 107.
In the digital clock frequency tracker 100, the frequency information extraction function is implemented by two sub-modules, namely a counting discriminator 101 and a bang-bang phase discriminator 102. In the implementation of the counting discriminator 101, first, the counting target values of the recovery clock of the receiving end and the local clock of the transmitting end are configured according to the data transmission rates of the receiving end and the transmitting end and the frequency division ratio of the frequency divider on the two paths of the high-speed clocks. And then, simultaneously releasing reset signals of two paths of counters driven by the recovery clock of the receiving end and the local clock of the sending end, so as to ensure that the two paths of counters start working simultaneously. And finally, generating a pulse signal after the count value of the local clock counter of the transmitting end reaches the target value, sampling the count value of the recovery clock counter of the receiving end, and comparing the sampled count value with the corresponding target value, thereby obtaining the frequency offset information. The frequency offset information is fed into the digital low pass filter 103 after multiplying the configurable gain, after which a frequency control word for the transmit side phase locked loop 107 is generated. The complete value of the frequency offset information may be used by configuration selection or only its sign may be used as an increment of the frequency control word.
The operation sequence of the counting discriminator 101 is shown in fig. 2. Since the receiver recovery clock is affected by the receiver data and has uncertainty, the sender local clock is used as the master clock for the count discriminator logic to generate the sampling signal and the counter reset signal. In one embodiment, the count discriminator 101 is further configured to reset the count value of the recovered clock signal and the count value of the local clock signal after sampling the count value of the recovered clock signal. In one embodiment, the target value of the recovered clock signal is four times, six times, eight times, or the like the target value of the local clock signal. It should be understood that in other embodiments of the present application, other multiples are also possible, e.g., two times, five times, etc.
The principle of operation of the bang-bang phase detector 102 is shown in fig. 3. Similar to the counting discriminator 101, the bang-bang phase discriminator 102 also uses the transmit-side local clock as the master clock for the digital logic. Different frequency division coefficients are configured by utilizing a frequency divider, so that the frequency of a local clock of a transmitting end used by the bang-bang phase discriminator 102 is four times of that of a recovered clock of a receiving end, the recovered clock of the receiving end is subjected to four times oversampling by using the local clock of the transmitting end in the bang-bang phase discriminator 102, and the relative phase relation of the two clocks is judged according to a sampling result. The relationship between the sampling result, the phase relationship and the bang-bang phase detector output is shown in table 1. When the sampling result of the bang-bang phase discriminator is 000, 010, 101 or 111, the phase relation is wrong, the phase discrimination result is 0, the bang-bang phase discriminator outputs 0, when the sampling result of the bang-bang phase discriminator is 001 or 110, the receiving end recovery clock advances the local clock of the transmitting end, the phase discrimination result is-1, the bang-bang phase discriminator outputs-1, when the sampling result is 011 or 100, the receiving end recovery clock lags the local clock of the transmitting end, and the phase discrimination result is 1, and the bang-bang phase discriminator outputs 1. The phase information of the two clocks, multiplied by a configurable gain, is fed into a digital low-pass filter 103, after which a frequency control word of the transmit-side phase-locked loop 107 is generated.
TABLE 1 sample results, phase relationship and relationship between phase discrimination results
Other arrangements may also be employed in other embodiments of the present application, but it is desirable to ensure that the multiple of oversampling the receive-side recovered clock in the bang-bang phase detector 102 using the transmit-side local clock is greater than two times, e.g., four times, six times, eight times, etc. If the oversampling multiple is an integer multiple of 4, the sampling result (phase discrimination result) does not need to be screened, and the bang-bang phase discriminator sequentially outputs the phase discrimination result. If the sampling result (phase discrimination result) is not an integer multiple of 4, the sampling result (phase discrimination result) needs to be used after screening, the screening principle is to convert the frequencies of the receiving end recovered clock and the transmitting end local clock into fractional forms, such as A/B, wherein A and B are integers, the first phase discrimination result in every N phase discrimination results is effective data, the rest N-1 phase discrimination results are invalid, and N is the least common multiple of A and B.
In the following, the working principle of the bang-bang phase discriminator 102 is illustrated in fig. 4, when the sampling result of the bang-bang phase discriminator is 000, 010, 101 or 111, the phase relation is wrong, the phase discrimination result is 0, when the sampling result of the bang-bang phase discriminator is 001 or 110, the receiving end recovers the clock to advance the local clock of the transmitting end, the phase discrimination result is-1, when the sampling result is 011 or 100, the receiving end recovers the clock to retard the local clock of the transmitting end, and the phase discrimination result is 1. When the ratio of the frequencies of the receiving end recovered clock and the sending end local clock is 1/6 in the six-time oversampling process, a=1, b=6, n is the least common multiple of 1 and 6, namely 6, the phase discriminator 102 outputs six phase discrimination results sequentially from the first phase discrimination result, and other phase discrimination results are discarded, namely the first of every 6 numbers in the phase discrimination results is valid data, and the rest data are discarded.
In the invention, the frequency and phase discrimination results output by the two sub-modules of the counting phase discriminator 101 and the bang-bang phase discriminator 102 are multiplied by the gains which are respectively and independently configured and then enter the digital low-pass filter 103 with configurable parameters, and the digital low-pass filter 103 generates the frequency control word of the transmitting-end phase-locked loop 107 and outputs the frequency control word to the transmitting-end phase-locked loop 107.
Since the recovery clock of the receiving end is affected by the data of the receiving end and has uncertainty, the present invention needs to include a frequency anomaly monitoring module 104 for detecting whether the recovery clock frequency of the receiving end is abnormal. The frequency anomaly monitoring module 104 is configured to obtain a recovered clock signal obtained by the clock-data recovery circuit 105 in the receiving end after the clock signal is divided by the first frequency divider 106 and a local clock signal obtained by the clock signal generated by the phase-locked loop 107 in the transmitting end after the clock signal is divided by the second frequency divider 108, set a corresponding target value according to the frequency division ratio of the recovered clock signal and the local clock signal, sample the count value of the recovered clock signal after the count value of the local clock signal reaches the target value, close the digital low-pass filter 103 when the difference value between the count value of the recovered clock signal and the target value exceeds a predetermined range, and enable the data low-pass filter 103 when the difference value between the count value of the recovered clock signal and the target value is within the predetermined range. In one embodiment, the target value of the receiver recovered clock signal in the frequency anomaly monitoring module 104 may be four times, six times, eight times, or the like the target value of the sender local clock signal. It should be understood that in other embodiments of the present application, other multiples are also possible, e.g., two times, five times, etc.
The frequency anomaly monitoring module 104 operates on the same principle as the counting discriminator 101, but with lower accuracy and higher bandwidth. The target value of the recovery clock signal at the receiving end and the target value of the local clock signal at the transmitting end in the frequency anomaly monitoring module 104 are smaller relative to the target value of the recovery clock signal at the counting frequency discriminator 101 and the target value of the local clock signal at the transmitting end, so that the counting period is shortened, the offset is calculated more quickly through the counting result, and therefore whether the recovery clock frequency at the receiving end is larger than the expected value or not can be detected quickly, and high bandwidth is realized. If the clock frequency recovered by the receiving end is abnormal, the frequency abnormality monitoring module turns off the enabling signal of the digital filter, and the frequency control word output by the digital filter is kept unchanged until the clock frequency recovered by the receiving end is normal.
In summary, the invention does not directly transmit the analog clock of the receiving end to the transmitting end to realize frequency tracking, but uses a digital circuit to extract the frequency information in the recovered clock of the receiving end, and transmits the digital signal to the transmitting end to complete frequency tracking. The output frequency of the phase-locked loop of the transmitting end under the abnormal state can be maintained through the frequency abnormality monitoring module in the digital circuit, so that the phase-locked loop of the transmitting end is prevented from losing lock, and the transmitting end can quickly recover data transmission after the receiving end is recovered to be normal.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between elements that are referred to as being coupled to each other.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

Claims (9)

1. A digital clock frequency tracker, comprising:
the counting frequency discriminator is used for acquiring a recovered clock signal obtained by frequency division of a clock signal recovered by the clock-data recovery circuit in the receiving end and a local clock signal obtained by frequency division of a clock signal generated by the phase-locked loop in the sending end, setting a corresponding target value according to the frequency division ratio of the recovered clock signal and the local clock signal, sampling the count value of the recovered clock signal after the count value of the local clock signal reaches the target value, and comparing the count value of the recovered clock signal with the count value of the local clock signal to obtain frequency offset information;
the phase discriminator is used for receiving the recovered clock signal after frequency division and the local clock signal after frequency division, setting a frequency division coefficient according to the frequency division ratio of the recovered clock signal and the local clock signal, oversampling the recovered clock signal according to the frequency division coefficient by using the local clock signal, and obtaining phase information according to an adopted result; and
and the digital low-pass filter is used for obtaining a frequency control word according to the frequency offset information, the phase information and the respective gains and outputting the frequency control word to the phase-locked loop of the transmitting end.
2. The digital clock frequency tracker of claim 1, further comprising:
the frequency anomaly monitoring module is used for receiving the frequency-divided recovered clock signal and the frequency-divided local clock signal, setting corresponding target values according to the frequency division ratio of the recovered clock signal and the local clock signal, sampling the count value of the recovered clock signal after the count value of the local clock signal reaches the target value, closing the digital low-pass filter when the difference value between the count value of the recovered clock signal and the target value exceeds a preset range, and enabling the digital low-pass filter when the difference value between the count value of the recovered clock signal and the target value is within the preset range.
3. The digital clock frequency tracker of claim 2, wherein the target value of the recovered clock signal is four, six, or eight times the target value of the local clock signal, and wherein the target values of the recovered clock signal and the local clock signal set in the frequency anomaly monitoring module are less than the target values of the recovered clock signal and the local clock signal set in the count discriminator.
4. The digital clock frequency tracker of claim 1, wherein the count discriminator is further configured to reset the count value of the recovered clock signal and the count value of the local clock signal after sampling the count value of the recovered clock signal.
5. The digital clock frequency tracker of claim 1, wherein the target value of the recovered clock signal is four, six, or eight times the target value of the local clock signal.
6. The digital clock frequency tracker of claim 1, wherein the phase detector uses the local clock signal to oversample the recovered clock signal by an integer multiple of four according to a frequency division factor, the phase discrimination result is 0 when the sampling result is 000, 010, 101 or 111, the phase discrimination result is-1 when the sampling result is 001 or 110, the phase discriminator result is 1 when the sampling result is 011 or 100, and the phase discriminator sequentially outputs the phase discrimination results.
7. The digital clock frequency tracker of claim 1, wherein the phase detector uses the local clock signal to oversample the recovered clock signal by a non-four integer multiple according to a frequency division factor, the phase discrimination result is 0 when the sampling result is 000, 010, 101 or 111, the phase discrimination result is-1 when the sampling result is 001 or 110, the phase discriminator result is 1 when the sampling result is 011 or 100, and the phase discriminator outputs from the first phase discrimination result sequentially at intervals of the non-four integer, discarding the other phase discrimination results.
8. The digital clock frequency tracker of claim 7, wherein the phase detector oversampling the recovered clock signal by a non-four integer multiple according to a division factor using the local clock signal further comprises: six-fold oversampling was performed.
9. A high-speed serial interface chip, comprising:
the clock-data recovery circuit is positioned at the receiving end and is used for recovering a high-speed clock of the receiving end;
the first frequency divider is used for dividing the frequency of the recovered high-speed clock to obtain a recovered clock signal after frequency division;
the phase-locked loop is positioned at the transmitting end and is used for generating a high-speed clock of the transmitting end;
the second frequency divider is used for dividing the frequency of the high-speed clock of the transmitting end to obtain a local clock signal after frequency division; and
a digital clock frequency tracker as claimed in any of claims 1 to 8.
CN202310199151.3A 2023-03-03 2023-03-03 Digital clock frequency tracker and high-speed serial interface chip Pending CN116527038A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116795172A (en) * 2023-08-29 2023-09-22 芯耀辉科技有限公司 Cross-clock domain processing method, medium and device for high-speed digital transmission

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116795172A (en) * 2023-08-29 2023-09-22 芯耀辉科技有限公司 Cross-clock domain processing method, medium and device for high-speed digital transmission
CN116795172B (en) * 2023-08-29 2023-12-12 芯耀辉科技有限公司 Cross-clock domain processing method, medium and device for high-speed digital transmission

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