CN107658315B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN107658315B CN107658315B CN201710716657.1A CN201710716657A CN107658315B CN 107658315 B CN107658315 B CN 107658315B CN 201710716657 A CN201710716657 A CN 201710716657A CN 107658315 B CN107658315 B CN 107658315B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The present invention relates to a kind of nand memory and preparation method thereof, nand memory includes: silicon substrate；Multiple peripheral components；The multiple NAND strings being formed in above the peripheral components；The monocrystalline silicon layer being formed in above the multiple NAND string, the monocrystalline silicon layer and the multiple NAND string connect, and the first interconnection layer of one or more being formed between the multiple peripheral components and multiple NAND strings.The present invention is by separating the production of array device and peripheral components, it can be avoided the manufacturing process for the other side that interacts when two device manufactures, therefore the production of subsequent layer in the prior art temperature limiting after by the layer production of front is solved the problems, such as, to obtain good peripheral components performance.It is superimposed upon on peripheral components additionally, due to array device, realizes high device density.
Description
Technical field
The present invention relates to a kind of nand memory and preparation method thereof more particularly to a kind of form 3D nand flash memory
Nand memory and preparation method thereof.
Background technique
With the continuing emphasis to highly integrated electronic device, to higher speed and lower Power operation and having
There are lasting demands for the semiconductor memory of the device density of increase.To reach this purpose, having been developed has
Smaller size of device and multilayer device with the transistor unit arranged with horizontal and vertical array.3D NAND is industry
The emerging flash type of the one kind researched and developed, 2D or plane nand flash memory band are solved by the way that memory grain is stacked
The limitation come.
The nand flash memory of planar structure has been approached its practical extended limit, brings sternness to choose to semiconductor memory industry
War.New 3D NAND technology, vertical stacking multi-layer data storage unit have brilliant precision.Based on the technology, can beat
Produce the storage equipment that memory capacity is up to several times than similar NAND technology.The technology can be supported to receive more in smaller space content
High storage capacity, so bring very big cost savings, energy consumption reduce, and significantly performance boost to meet numerous disappear comprehensively
Take class mobile device and requires the demand of most harsh enterprise's deployment.
In one approach, planar memory cell (such as nand memory unit) is formed in conventional horizontal array
In.Then multiple horizontal arrays stack in vertical direction.Due to being required in realizing minimum feature size for each layer
Critical photolithographic steps, therefore limitation relevant to the method includes that reliability is low in obtained device and is difficult to pass through light
It carves and realizes 16nm manufacture, to be difficult to further increase memory capacity.In addition, in such configuration, being used to drive control and selecting
The size of the driving transistor of door is the function of the number of plies；Therefore, drive the scale of transistor for the multiple of the number of plies.This will lead to collection
The problem of at the problem of change and in terms of heat dissipation.In another approach, the multilayer with vertically oriented channel has been developed
Memory.In a construction, multiple selection gate layer are formed on substrate, and vertical-channel passes through multiple selection gate layer.Every
In a vertical-channel, lower selection gate layer is configured to function as lower selection door (lower select gate), multiple intermediate grid layer structures
It makes as control grid, upper selection gate layer is configured to function as selection door (upper select gate).It is connected to the first water
Square upwards upper selection door adjacent to each other for use as device row select line.It is connected in the second horizontal direction adjacent to each other
Vertical-channel for use as device bit line (bit line).The achievement that other methods for attempting vertically oriented channel have been achieved with has
Limit.
Currently, at home and abroad having extensive patent application about 3D nand flash memory technology.Such as Chinese invention patent
Application publication number CN101483194A discloses a kind of vertical-type non-volatile memory device and its manufacturing method.It partly leads at this
In body device and its manufacturing method, device includes the substrate of horizontally extending single-crystal semiconductor material and in the substrate
On multiple interlevel dielectric layers.Multiple selection door patterns are provided, each selection door pattern dielectric layer between adjacent lower
Between adjacent upper between dielectric layer.The vertical-channel of semiconductor material is extended in the vertical direction across multiple interlayer dielectrics
Layer and selection door pattern, select door insulating layer between each selection door pattern and vertical-channel and make selection door pattern with it is vertical
Channel insulation.It as shown in Fig. 1, is the sectional view of the vertical channel transistor structure device.The vertical channel transistor structure device is under
To above sequentially forming Si substrate layer 300, peripheral circuit region 302 and array device layer.
However the shortcomings that above-mentioned patented technology, is, above-mentioned vertical channel transistor structure device is due to only on a Si substrate layer
Sequentially built causes subsequent device (such as NAND string) temperature in production that must be limited, otherwise can be because of temperature mistake
Ion (such as the NMOS and PMOS device manufactured on a silicon substrate in high and the device that causes front to be made ion implanted layer
Part) ion diffusion is generated, so that the combination depth between device is difficult to control, to influence properties of product.That is
The requirement manufactured between each layer can be limited from each other.
In addition, forming NAND at the top of peripheral components 302 after manufacturing peripheral components 302 on a silicon substrate in above-mentioned patent
Device.In this way, NAND device is isolated with silicon substrate.NAND device needs to substitute silicon substrate using an active layer in this way, from
And device performance is caused to decline.
Interacting for each interlayer in manufacturing process how is avoided, guarantees that the performance of product is current to need to solve
Problem.
Summary of the invention
The purpose of the present invention is what is be achieved through the following technical solutions.
In view of the above problems, the invention discloses a kind of semiconductor devices, from bottom to top successively include: silicon substrate
Plate, the peripheral components being formed on the silicon substrate, one or more interconnection layers and the formation being formed on the peripheral components
Array device on one or more interconnection layers.In some embodiments, the array device further comprises being formed in institute
State the monocrystalline silicon layer of array device upper end.
In some embodiments, the semiconductor device further comprises the multiple back segment systems being formed in above array device
Journey (back-end-of-line, BEOL) interconnection layer and laying.
In some embodiments, peripheral components include multiple gold oxygen semiconductor field effect transistors (MOSFETs).Some
In embodiment, the peripheral components are formed on a silicon substrate.In some embodiments, the silicon substrate has doped region and isolation
Area.In some embodiments, the gold oxygen semiconductor field effect transistor (MOSFETs) of the peripheral components is used as memory not
Congenerous device, such as page buffer, sensor amplifier, column decoder or line decoder.
In some embodiments, one or more interconnection layers include periphery interconnection；In some embodiments, the periphery is mutual
It even include multiple interconnection layers and contact layer.In some embodiments, the interconnection layer includes multiple metal layers.The metal layer can
To be made of tungsten, copper, aluminium or other suitable materials.In some embodiments, the contact layer can by tungsten, copper, aluminium or other
Suitable material is made.In some embodiments, one or more of interconnection layers are formed in different periphery transistors
Between transmit electric signal, or electric signal is transmitted between periphery transistor and array device.
In some embodiments, one or more interconnection layers include array interconnection.In some embodiments, the array is mutual
Connection includes multiple interconnection layers and contact layer.In some embodiments, the interconnection layer includes multiple metal layers.The metal layer can
To be made of tungsten, copper, aluminium or other suitable materials.In some embodiments, the contact layer can by tungsten, copper, aluminium or other
Suitable material is made.In some embodiments, the periphery is interconnected and form for transmitting between the different zones of array device
Electric signal, or electric signal is transmitted between periphery transistor and array device.
In some embodiments, the array device includes multiple NAND strings.In some embodiments, the array device
It further comprise multiple interconnection layers being formed in below the multiple NAND string.In some embodiments, the array device into
One step includes the monocrystalline silicon layer being formed in above the NAND string.In some embodiments, the monocrystalline silicon layer is silicon substrate
A part is simultaneously thinned by suitable technology in the subsequent process, such as backgrind, wet/dry ecthing and/or chemical machinery
Polishing technology.In some embodiments, the monocrystalline silicon layer is contacted with the multiple NAND string.In some embodiments, described
The thickness of monocrystalline silicon layer is between 200 nanometers to 50 microns.In some embodiments, the thickness of the monocrystalline silicon layer between
Between 500 nanometers to 10 microns.In some embodiments, the thickness of the monocrystalline silicon layer is between 500 nanometers to 5 microns.
In some embodiments, the monocrystalline silicon layer is partly or entirely adulterated using N-shaped and/or p-type dopant.
In some embodiments, each NAND string include: vertical direction extend across the multiple conductor/absolutely
The channel semiconductor (such as silicon channel) of edge body lamination.Each such conductor layer or insulator layer can be referred to as a grade
Layer.Multiple conductor/insulation body laminations may also be referred to as grade layer stack.Conductor layer may be used as wordline (or control door).It is multiple
Layer can be between conductor layer and channel semiconductor.In some embodiments, the multiple layer includes tunnel layer, for example, tunnel
Road oxide skin(coating), it is single that electronics or hole in channel semiconductor can pass through the charging of this layer of tunnel layer tunnelling to NAND string storage
In first layer.In some embodiments, the multiple layer includes the memory cell layers that can store charge.Electricity in memory cell layers
The storage or removal of lotus determine the open/close state of channel semiconductor.In some embodiments, memory cell layers can be by polycrystalline
Silicon layer or silicon nitride layer are made.In some embodiments, the multiple layer further comprises barrier layer, such as a silicon oxide layer
Or one by three layers of composite layer constituted of silicon oxide/silicon nitride/silicon oxide (ONO).In some embodiments, the barrier layer can
To further comprise a high k dielectric layer (such as aluminium oxide).
In some embodiments, the NAND string further comprises a silicon epitaxial layers, and it is logical to be formed in the semiconductor
The upper end in road.In some embodiments, the silicon epitaxial layers are from the monocrystalline silicon layer epitaxial growth above the NAND string.
In some embodiments, the NAND string further comprises selection door, by one or more in grade layer stack
A upper conductor layer is formed.In some embodiments, the selection door controls the ON/OFF shape of the channel semiconductor of the NAND string
State.In some embodiments, the selection door of the NAND string is formed by an independent conductor layer above grade layer stack.One
In a little embodiments, the NAND string further comprises that selection door is formed by one or more lower conductor layers in grade layer stack.
In some embodiments, the selection door of the NAND string is formed by an independent conductor layer below grade layer stack.
In some embodiments, the NAND string connects source by being formed in the doped region of the monocrystalline silicon layer above NAND string
Contact.In some embodiments, the doped region of the monocrystalline silicon layer is adulterated by p-type dopant.In some embodiments, the source
Contact extends vertically through grade layer stack and contacts in upper end with monocrystalline silicon layer.In some embodiments, the source contact
Bottom end is contacted with the contact that one or more is formed in below the contact of source.
In some embodiments, array device further comprises multiple wordline contacts.In some embodiments, the multiple
Wordline contact extends vertically and each of the multiple wordline contact has one and the end of word line contact, as a result, array
The wordline of device can be addressed respectively by wordline contact.In some embodiments, each wordline contact is formed in wordline
Under and connect with the wordline.In some embodiments, multiple wordline contacts are by using wet etching or dry etching shape
At contact hole or contact trench, the contact hole hole or contact trench then are filled using conductor (such as tungsten).Some
In embodiment, filling contact hole or contact trench are included in deposition barrier layer and/or adhesive layer before the deposition conductor.Some
In embodiment, the wordline contact is initially formed above wordline, then by wafer turned upside down so that wordline contact position
Below wordline.
In some embodiments, the interconnection layer formed below the NAND string includes multiple bit line contacts, and described
The bottom of NAND string contacts.In some embodiments, the contact hole of multiple institute's bit line contacts is independent mutually.In some embodiments
In, institute's bit line contact connects each NAND string so that each NAND string can be addressed individually by contact.In some realities
It applies in example, the generation type of institute's bit line contact is as follows: contact hole or contact ditch being formed by wet etching or dry etching first
Then slot fills the contact hole or contact trench using conductor (such as tungsten).In some embodiments, using chemical vapor deposition
Area method (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD) complete the filling of contact hole or contact trench.
In some embodiments, institute's bit line contact is initially formed above NAND string, then by wafer turned upside down so that position
Line contact is located at below NAND string.
In some embodiments, one or more interconnection layers further comprise bonding interface.In some embodiments, described
Bonding interface can be formed between two insulating layers, such as between silicon nitride layer and silicon oxide layer.The bonding interface can also
To be formed between the two metal layers, such as between a layers of copper and another layers of copper.In some embodiments, bonding circle
Face both may include interface between insulating layer or may include interface between metal layer.In some embodiments, boundary is bonded
Chemical bonding between insulating layer and/or conductor layer of the face by being located at bonding interface two sides is formed.In some embodiments, it bonds
Physical interaction (such as counterdiffusion) between insulating layer and/or conductor layer of the interface by being located at bonding interface two sides is formed.
In some embodiments, it before combined process, is formed after carrying out corona treatment by the surface to bonding interface two sides
The bonding interface.In some embodiments, it before combined process, is heat-treated by the surface to bonding interface two sides
After form the bonding interface.
In some embodiments, the memory further comprises multiple grades layer stack.In some embodiments, in phase
Intermediate depot layer can be formed between adjacent grade layer stack.In some embodiments, intermediate depot layer connection upside grading layer
The NAND string of storehouse and the NAND string of downside grade layer stack.In some embodiments, the sum of the NAND string of upside grade storehouse
The NAND string of downside grade layer stack is electrically connected to form longer NAND string by the conductor part of intermediate depot layer.
In some embodiments, described device further comprises the multiple through array contacts, described to implement array touching
Point extends vertically through the grade storehouse or multiple grades storehouse.In some embodiments, multiple both to connect through array contacts
The multiple interconnection layers formed below the NAND string of grade layer stack are connect, the more of the NAND string top formation of grade layer stack are also connected
A interconnection layer.In some embodiments, the multiple generation type through array contacts is as follows: being formed first by dry etching
Then contact hole and/or contact trench fill the contact hole or contact ditch using conductor material (such as tungsten, copper or silicide)
Slot.
In some embodiments, the BEOL interconnection layer of formation is used for transmission the electric signal of semiconductor device, including battle array
The electric signal of column device and peripheral components.In some embodiments, the laying of formation is used for transmission semiconductor device
Electric signal is to external electric signal channel.In some embodiments, the BEOL interconnection layer includes interconnection conductors layer and contact layer.Institute
It states interconnection conductors layer and contact layer includes conductive material, such as tungsten, copper, aluminium, silicide, and/or other suitable conductive materials.?
In some embodiments, substrate layer includes conductor, such as tungsten, copper, aluminium, silicide and/or other suitable conductive materials.
In view of the above problems, the invention also discloses a kind of preparation methods of semiconductor device.Wherein, preparation half
Conductor installation method includes the following steps:
Form peripheral components；
Form array device；
By the peripheral components and array device it is positioned opposite and by bonding interface in conjunction with the peripheral components and array
Device.
Preferably, wherein prepare peripheral components and specifically comprise the following steps:
Form the first silicon substrate；
Peripheral components are formed on the first silicon substrate, wherein the peripheral components include MOS transistor；
Periphery interconnection is formed above the peripheral components.
Preferably, wherein prepare array device and specifically comprise the following steps:
Form the second silicon substrate；
Doped region and isolated area are formed in second silicon substrate；
One or more NAND strings are formed on second silicon substrate；Wherein, each NAND string includes: multiple leads
Body/insulator lamination extends across the channel semiconductor of the multiple conductor/insulation body lamination, multiple shapes in vertical direction
At the storage unit between the channel semiconductor and conductor layer, it is formed between the storage unit and channel semiconductor
Tunnel layer, the barrier layer being formed between storage unit and conductor layer, and it is formed in the monocrystalline silicon of the channel semiconductor bottom end
Epitaxial layer；Wherein, one or more of NAND strings are contacted with second silicon substrate.In some embodiments, the monocrystalline
Silicon epitaxy layer is from the second silicon substrate epitaxial growth；Wherein, one or more of NAND strings further comprise being formed in
The selection door of NAND string one end.
Array interconnection layer is formed in NAND string, wherein including being formed and one or more in the step of forming array interconnection layer
The bit line contact of a NAND string contact.Forming array interconnection layer further comprises forming one or more interconnection layers and contact layer,
Wherein the interconnection layer and contact layer include conductive material, such as tungsten, aluminium, copper, and/or other suitable materials.
According to some embodiments, forming array interconnection layer further comprises the source contact to form one or more NAND strings.
In some embodiments, the source contact extends through multiple conductor/insulation body laminations vertically.In some embodiments, institute
The one end for stating source contact is contacted with second silicon substrate, and the other end is contacted with the interconnection layer of array contacts.In some implementations
In example, the source contact is electrically connected one or more NAND strings by the second silicon substrate.
Adhesion step specifically includes: the peripheral components and the array device are positioned opposite and glued by bonding interface
Junction is closed, and the back side of the second silicon substrate layer is then thinned, and Pad layers are formed on the back side, and BEOL Jie is formed on PAD layers
Matter layer.
Peripheral components and array device are combined in bonding interface, wherein the step of combining peripheral components and array device is wrapped
It includes: the array device is inverted, array interconnection layer of the alignment surface to peripheral components and the peripheral interconnection layer in face of array device,
Array device is placed on peripheral components, so that the surface of array interconnection layer contacts the surface of peripheral interconnection layer, is held
Row combination processing is to form bonding interface.In some embodiments, combination processing includes plasma-treating technology, wet processing
And/or heat treatment process, so that in face of the surface of the array interconnection layer of bonding interface and the surface formation of peripheral interconnection layer
Reason or chemical bonding.In some embodiments, the surface of array interconnection layer includes a silicon nitride layer and the table of peripheral interconnection layer
Face includes a silicon oxide layer.In some embodiments, the surface of array interconnection layer includes a silicon oxide layer and periphery interconnects
The surface of layer includes a silicon nitride layer.In some embodiments, the table of the surface conductor of array interconnection layer and peripheral interconnection layer
Face conductor includes copper.
In some embodiments, the combination of array interconnection layer and periphery interconnection layer surface is by the insulating layer in two sides
Physical interaction (such as counterdiffusion) completion is formed between (such as silicon nitride layer or silicon oxide layer) and/or conductor layer.Battle array
Interface between column interconnection layer and periphery interconnection layer surface is combination interface.In some embodiments, right before combined process
The corona treatment of array interconnection layer and periphery interconnection layer surface can reinforce the binding force between two surfaces.In some realities
It applies in example, before combined process, two can be reinforced to the wet processing processing of array interconnection layer and periphery interconnection layer surface
Binding force between surface.In some embodiments, array interconnection layer is placed in includes aligned array on peripheral interconnection layer
The contact region of interconnection layer and peripheral interconnection layer, so that the contact region of two interconnection layers can connect when two sides are combined together
Touching.In some embodiments, when the surface contact of array interconnection layer and peripheral interconnection layer, heat treatment operation is executed.Some
In embodiment, this heat treatment promotes the mutual expansion between array interconnection layer and the conductive material (such as copper) of peripheral interconnection layer
It dissipates.
In some embodiments, one or more bonding interfaces can be formed in a manufacturing method.In some embodiments,
Multiple array devices are in conjunction with a peripheral components.In some embodiments, an array device can be with multiple peripheral components
In conjunction with.In some embodiments, multiple array devices are in conjunction with multiple peripheral components.
In some embodiments, array device includes multiple grades layer stack.Each grade layer stack include multiple conductors/
Insulating layer.In some embodiments, intermediate depot layer can be formed between adjacent rank layer stack.In some embodiments, institute
State the intermediate depot layer connection upside NAND string of grade layer stack and the NAND string of downside grade layer stack.
After associative array device and peripheral components, the second silicon substrate of the array device is thinned.In some implementations
In example, the technique that the second silicon substrate is thinned is completed by chemical-mechanical planarization (CMP) technique.In some embodiments, it is thinned the
The technique of two silicon substrates can also be completed by other appropriate process, for example, wet etching and/or dry etching.
Since array device and peripheral components are independently formed, formed array device/array interconnection layer and peripheral components/
The process sequence of peripheral interconnection layer can exchange.
The present invention has the advantages that
The present invention is completed on two silicon wafers by separating the production of array device and peripheral components, can be avoided two
Device interacts the manufacturing process of other side when manufacturing, therefore solves layer of the production by front of subsequent layer in the prior art
After production the problem of temperature limiting.
Semiconductor device disclosed by the invention, by the way that array device layer to be arranged in the top of peripheral circuit layer, to increase
The density of device is added.And the preparation method of peripheral circuit layer and array device layer is simplified, to obtain preferably outer
Enclose circuit layer performance (for example, CMOS performance).The raising of CMOS performance is made since peripheral circuit and array device are prepared respectively
The high-temperature technology for obtaining back segment array device does not influence leading portion peripheral components, and the performance of back end device is available to promote (ratio
As dopant does not have additional diffusion, such as the control, etc. that the junction depth that is formed of ion implanting can be relatively good.)
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 is the sectional view of traditional vertical channel transistor structure device.
Fig. 2 is the structural schematic diagram of the nand memory of embodiment according to the present invention；
Fig. 3 A-3D is the preparation step schematic diagram of the peripheral components of the nand memory of embodiment according to the present invention；
Fig. 4 A-4D is the preparation step schematic diagram of the array device of the nand memory of embodiment according to the present invention；
Fig. 5 A-5C is that the array device Yu peripheral components of embodiment according to the present invention bond to obtain the system of nand memory
Standby step schematic diagram.
Fig. 6 is the flow chart to form peripheral components and peripheral interconnection layer exemplary method 600.
Fig. 7 is the flow chart to form array device and array interconnection layer exemplary method 700.
Fig. 8 is the flow chart of the exemplary method 800 of associative array device and peripheral components.
Specific embodiment
Below in reference to the attached drawing embodiment that the present invention is more fully described, the preferred embodiment of the present invention is shown in the accompanying drawings
Out.However, the present invention can be implemented in different ways, and it should not be construed as limited to embodiments described herein.Whole
Identical appended drawing reference refers to identical element always in a specification.
Although should be appreciated that term first, second etc. can be used to describe various elements here, these elements should not be limited
In these terms.These terms are for making an element be different from another element.For example, first element is properly termed as second yuan
Part, similarly, second element are properly termed as first element, without departing from the scope of the present invention.As used herein, term " and/
Or " include relevant item listed by one or more any and all combination.
It should be appreciated that when claiming an element, in another element "upper", " being connected to " or " being coupled to " another element, it can
To be directly perhaps connected or coupled to another element on another element or there may also be the elements of insertion.On the contrary, working as
Claim on an another element of element " directly existing " or when " being directly connected to " or " being directly coupled to " another element, there is no insert
The element entered.Words of the others for describing relationship between element should explain in a similar way (for example, " ... it
Between " relative to " between directly existing ... ", " adjacent " relative to " direct neighbor " etc.).Here when one element of title is in another element
When upper, it can be directly coupled to another element, or there may be the element of insertion, Huo Zheyuan in another element up or down
Part can be separated by gap or gap.
Terminology used here is not intended to limit the present invention just for the sake of description specific embodiment.As used herein,
It clearly states unless the context otherwise, otherwise singular " one " and "the" are intended to include plural form simultaneously.It should also manage
Solution, term " includes ", " comprising ", " comprising " and/or " comprising ", when here in use, specifying the feature, entirety, step
Suddenly, operation, the presence of element and/or component, but one or more other features, entirety, step, operation, member are not precluded
The presence or addition of part, component and/or combination thereof.
As shown in Fig. 2, for according to the schematic device junction composition of the preferred embodiment of the present invention.Including first silicon substrate
Plate 202.In some embodiments, the first silicon substrate 202 can be made of monocrystalline silicon.In some embodiments, the first silicon substrate 202
It can be made of other suitable materials, such as, but not limited to, SiGe, germanium, silicon on insulator (SOI).Peripheral components are formed in
On first silicon substrate 202.The peripheral components include multiple transistors 206.In some embodiments, on the first silicon substrate 202
It is formed with isolated area 204 and doped region 208.Peripheral 222 covering transistor 206 of interconnection layer is to carry out electric signal conduction.Interconnection layer
222 include one or more contacts, such as contact 207 and contact 214, one or more interconnection conductors layers, such as 216 He of layer
220.Interconnection layer 222 further comprises one or more layer insulations (ILD) layer, such as insulating layer 210,212 and 218.Contact
It is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium, and/or silicide.Conductive layer is made of an electrically conducting material, including
But it is not limited to tungsten, cobalt, copper, aluminium, and/or silicide.Interlayer insulating film is made of insulating material, including but not limited to silica,
Silicon nitride, silicon oxynitride, and/or doped silicon oxide.
Array device is formed on peripheral components.Array device includes multiple NAND strings 230, extends through multiple lead
236 lamination 242 of body 234 and insulator.Multiple conductor/insulation body laminations 242 are also referred to as grade layer stack.In some embodiments
In, grade layer stack 242 may include more being made from a different material than multiple conductor/insulation body laminations and/or different thick
The conductor layer or insulating layer of degree.In some embodiments, conductor layer 234 is made of an electrically conducting material, including but not limited to tungsten, cobalt,
Copper, aluminium, doped silicon and/or silicide.Insulating layer 236 is made of insulating material, including but not limited to silica, silicon nitride, nitrogen
The combination of silica or the above material.Multiple NAND strings 230 include channel semiconductor 228 and dielectric layer 229.In some embodiments
In, channel semiconductor 228 is made of noncrystalline, polycrystalline or monocrystalline silicon.In some embodiments, dielectric layer 229 includes one
Tunnel layer, a memory cell layers and a barrier layer.The tunnel layer is made of silica, silicon nitride or a combination thereof.Institute
Barrier layer is stated to be made of silica, silicon nitride, high dielectric constant insulating materials or a combination thereof.Memory cell layers by silicon nitride,
The combination of silicon oxynitride, silicon or the above material is made.
In some embodiments, multiple NAND strings 230 include multiple control doors (or wordline).In some embodiments, it leads
Body layer 234 is used as the control door of NAND string.In some embodiments, multiple NAND strings 230 further comprise selection door 238,
It is formed adjacent to the upper end of NAND string.In some embodiments, multiple NAND strings 230 further comprise selection door 240, are formed
In the lower end close to NAND string.In some embodiments, selection door 238 and 240 is made of an electrically conducting material, including but not limited to
Tungsten, cobalt, copper, aluminium, doped silicon and/or silicide.
In some embodiments, multiple NAND strings 230 further comprise silicon epitaxial layers 251, and covering is formed in NAND string
The upper end of 230 channel semiconductor 228.In some embodiments, silicon epitaxial layers 251 from the epitaxial growth of monocrystalline silicon layer 244 and
It is formed.
In some embodiments, array device further comprises one or more source contacts 232, extends through grading layer
Storehouse 242.In some embodiments, source contact 232 is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium, and/or
Silicide.
In some embodiments, array device further comprises one or more wordline contacts 258.In some embodiments
In, multiple wordline contacts extend vertically in insulating layer 259.In some embodiments, each of multiple wordline contacts has
One with the end of word line contact, each wordline of array device can be addressed respectively by wordline contact as a result,.One
In a little embodiments, each wordline contact is formed under wordline and connect with the wordline.In some embodiments, multiple wordline
Contact forms contact hole or contact trench by using wet etching or dry etching, then fills institute using conductor (such as tungsten)
State contact hole or contact trench.In some embodiments, filling contact hole or contact trench sink before being included in the deposition conductor
Product barrier layer and/or adhesive layer.
In some embodiments, array device further comprises monocrystalline silicon layer 244, and covering is formed in NAND string 230
Upper end.In some embodiments, monocrystalline silicon layer 244 is made of monocrystalline silicon.In some embodiments, monocrystalline silicon layer 244 can also be with
It is made of other materials, including but not limited to SiGe or germanium.In some embodiments, monocrystalline silicon layer 244 has doped region 250
With isolated area 246.
In some embodiments, source contact 232 and NAND string 230 are contacted with the monocrystalline silicon layer 244, therefore work as monocrystalline
Silicon layer 244 conduct electric signal when, source contact 232 can be electrically connected with NAND string 230 (such as when monocrystalline silicon layer 244 formed lead
When the inversion layer of electricity).
In some embodiments, array device further comprises one or more through array contacts 241, vertical to extend
And run through grade layer stack 242.In some embodiments, it is the multiple through array contacts 241 by electric signal from peripheral components
It is transferred to back-end process (BEOL) layer 254 or laying 256.
In some embodiments, array interconnection layer 223 is formed in the top of peripheral interconnection layer 222.In some embodiments,
Array interconnection layer 223 includes bit line contact 226, wordline through-hole contact 257, one or more conductor layers (such as layer 224) and one
A or multiple insulating layers (such as insulating layer 225 and insulating layer 221).The conductor layer can be made of an electrically conducting material, including but
It is not limited to tungsten, cobalt, copper, aluminium and/or silicide.The insulating layer is made of insulating material, including but not limited to silica, nitridation
Silicon, high dielectric constant insulating materials or a combination thereof.
Bonding interface 219 be formed in peripheral interconnection layer 222 insulating layer 218 and array interconnection layer 223 insulating layer 221 it
Between.In some embodiments, bonding interface 219 can also be formed between conductor layer 224 and conductor layer 220.In some implementations
In example, insulating layer 218 is silicon nitride layer and insulating layer 221 is silicon oxide layer.In some embodiments, insulating layer 218 is oxidation
Silicon layer and insulating layer 221 is silicon nitride layer.
In some embodiments, bit line contact 226 contacts the bottom end of multiple NAND strings 230.In some embodiments, each
Bit line contact 226 is contacted with a NAND string 230 respectively, so that bit line contact independently addresses each NAND string.
In some embodiments, the wordline through-hole contact 257 is contacted with the low side of the multiple wordline contact 258.?
In some embodiments, each wordline through-hole contact 257 is contacted with each wordline contact 258, and wordline through-hole can divide as a result,
It is not addressed respectively in each NAND string.
Preferred embodiment shown in Fig. 2 further comprises one or more back-end process interconnection insulating layers and conductor layer (example
Such as conductor layer 248, conductor layer 254 and insulating layer 252) and laying (such as laying 256).The back-end process interconnection layer and
Laying transmits electric signal between the device and external circuit of the embodiment.Back-end process conductor layer can be by conductive material
It is made, including but not limited to tungsten, cobalt, copper, aluminium and/or silicide.The back-end process insulating layer is made of insulating material, including
But be not limited to silica, silicon nitride, high dielectric constant insulating materials or a combination thereof.Laying is made of an electrically conducting material, including
But it is not limited to tungsten, cobalt, copper, aluminium and/or silicide.
Fig. 3 A-3D is the preparation step of the peripheral components of the nand memory of embodiment and peripheral interconnection layer according to the present invention
Rapid schematic diagram；Fig. 6 is the flow chart to form peripheral components and peripheral interconnection layer exemplary method 600.
Exemplary method 600 starts from operation 602, as shown in fig. 6, forming peripheral components on the first silicon substrate.Such as figure
Shown in 3A, the first silicon substrate 302 is provided firstly, to form peripheral components in some embodiments, peripheral components include more
A transistor device 304.The multiple transistor device 304 is formed on the first silicon substrate 302.In some embodiments, shape
Include multiple steps, including but not limited to photoetching, dry/wet etching, thin film deposition, thermally grown, note at transistor device 304
Enter, chemical-mechanical planarization (CMP), and/or above combination.In some embodiments, doped region 308 is also formed in the first silicon
On substrate 302.In some embodiments, isolated area 306 is also formed on the first silicon substrate 302.
Exemplary method 600 continues at operation 604, as shown in fig. 6, formed on peripheral components one or more insulating layers and
Conductor layer.One or more of insulating layers and conductor layer are a part of peripheral interconnection layer, can transmit the electricity of peripheral components
Signal.As shown in Figure 3B, the first layer insulating 310 is formed on the first silicon substrate 302, and contact layer 308 is formed and is electrically connected
Peripheral components.As shown in Figure 3 C, second insulating layer 316 is formed on the first insulating layer 310.In some embodiments, second absolutely
Edge layer 316 can be multiple layers of combination and be formed by independent process.Conductor layer 312 and contact layer 314 are formed in second absolutely
In edge layer 316.In some embodiments, conductor layer 312, contact layer 308 and conductor layer 314 are made of an electrically conducting material.Formation is led
Thin film deposition technique, including but not limited to chemical vapour deposition technique (CVD), physics gas can be used in the technique of body layer and contact layer
Phase sedimentation (PVD) or atomic layer deposition method (ALD) and electroplating technology.The technique for forming conductor layer and contact layer can also make
With photoetching, chemical-mechanical planarization, dry/wet etching.Thin film deposition technique can be used in the technique for forming insulating layer, including
But it is not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD).
Exemplary method 600 continues at operation 606, as shown in fig. 6, forming a top layer and one for peripheral interconnection layer
A top conductor layer.As shown in Figure 3D, third insulating layer 318 is formed in second insulating layer 316, and conductor layer 320 is formed in
In three insulating layers 318.It has been thusly-formed peripheral interconnection layer 322.Thin film deposition technique can be used in the technique for forming conductor layer, wraps
Include but be not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD) and galvanizer
Skill.Photoetching, chemical-mechanical planarization, dry/wet etching also can be used in the technique for forming conductor layer and contact layer.It is formed exhausted
Thin film deposition technique, including but not limited to chemical vapour deposition technique (CVD), physical vaporous deposition can be used in the technique of edge layer
(PVD) or atomic layer deposition method (ALD).
Fig. 4 A-4D is the preparation step of the array device of the nand memory of embodiment and array interconnection layer according to the present invention
Rapid schematic diagram；Fig. 7 is the flow chart to form array device and array interconnection layer exemplary method 700.
Exemplary method 700 starts from operation 702, as shown in fig. 7, forming doped region and isolated area on the second silicon substrate.
As shown in Figure 4 A, the second silicon substrate 402 is used to form array device.In some embodiments, doped region 404 is formed in the second silicon
On substrate 402.In some embodiments, isolated area 406 is formed on the second silicon substrate 402.Forming doped region 404 can be used
Injection and/or diffusion technique.The technique for forming isolated area 406 can use thermally grown or thin film deposition.Photoetching and dry/wet
Etching technics can be used to form isolated area pattern.
Exemplary method 700 continues at operation 704, as shown in fig. 7, forming multiple insulating layers pair on the second silicon substrate.Such as
Shown in Fig. 4 B, multiple insulating layers are formed on the second silicon substrate 402 410 and 412.In some embodiments, multiple insulating layers
To formation grade layer stack 408.In some embodiments, insulating layer is to including silicon nitride layer 410 and silicon oxide layer 412.One
In a little embodiments, there are more insulating layers pair in grade layer stack 408, the insulating layer is to being made from a different material and have
Different-thickness.In some embodiments, thin film deposition technique can be used in the technique for forming multiple insulating layers pair, including but unlimited
In chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD).
Exemplary method 700 continues at operation 706, as shown in fig. 7, forming multiple array devices on the second silicon substrate
NAND string.As shown in Figure 4 C, multiple NAND strings 418 are formed on the second silicon substrate 402.In some embodiments, grade layer heap
The insulating layer 410 of the insulating layer centering of stack 408 could alternatively be conductor layer 416, to be formed in grade layer stack 414 multiple
Conductor/insulation layer is right.It in some embodiments, can be using for insulation using the technique that conductor layer 416 replaces insulating layer 410
412 selective wet etching method etching insulating layer 410 of layer, it is this to etch or micro etching insulating layer 412, so
In the structure formed after the filling insulating layer 410 of conductor layer 416 is etched afterwards.In some embodiments, filling conductor layer 416 can
To use CVD, ALD and other suitable methods.In some embodiments, conductor layer 416 is made of an electrically conducting material, including but not
It is limited to tungsten, cobalt, copper, aluminium and/or silicide.In some embodiments, forming NAND string further comprises forming channel semiconductor
420, the grade layer stack 414 is extended across in vertical direction.In some embodiments, NAND string is formed further to wrap
Dielectric layer 422 is included, is located at channel semiconductor 420 and multiple conductor/insulation layers between.In some embodiments, dielectric layer
422 be multiple layers of combination, including but not limited to tunnel layer, memory cell layers and barrier layer.In some embodiments, described
Tunnel layer includes insulating materials, including but not limited to the combination of silica, silicon nitride, silicon oxynitride or above-mentioned material.Some
In embodiment, the material that memory cell layers include can be used for storing the charge of operation NAND.The material of memory cell layers includes
But it is not limited to the combination of silicon nitride, silicon oxynitride or silica and silicon nitride or the combination of above-mentioned material.In some embodiments
In, the barrier layer includes insulating materials, such as a silicon oxide layer or one include silicon oxide/silicon nitride/silicon oxide (ONO)
Composite layer.In some embodiments, the barrier layer may further include a high k dielectric layer (such as aluminium oxide).?
In some embodiments, ALD, CVD, PVD and other suitable methods can be used by forming dielectric layer 422.
In some embodiments, forming NAND string further comprises the epitaxial layer for being formed in described NAND string one end.Such as figure
Shown in 4C, epitaxial layer 426 is formed in the bottom end of NAND string 418.In some embodiments, epitaxial layer 426 is silicon layer, with second
Silicon substrate 402 directly contacts and from epitaxial growth on the second silicon substrate 402.In some embodiments, epitaxial layer 426 is further
It is doped to desired doped level.
In some embodiments, operation 706 further comprises forming one or more source contacts.As shown in Figure 4 C, vertically
The source contact 424 for extending through grade layer stack 414 is formed on the second silicon substrate 402.In some embodiments, source contact
424 one end directly contacts the doped region 404 of the second silicon substrate 402.In some embodiments, source contact 424 passes through the second silicon
The contact doping area 404 of substrate 402 is electrically connected multiple NAND strings 418.In some embodiments, selection door 428 is formed in
The bottom end of grade layer stack 414, and by the contact doping area 404 of the second silicon substrate of switch 402 come voltage input contact 424 and multiple
Conduction between NAND string 418.In some embodiments, source contact 424 is made of an electrically conducting material, including but not limited to tungsten, cobalt,
The combination of copper, aluminium, doped silicon, silicide or the above material.In some embodiments, forming source contact 424 can be by using
Dry/wet etching technics extends vertically through the opening of grade layer stack 414 to be formed, then by conductor material or other materials
Such as insulating materials fills the opening.The packing material can use ALD, CVD, PVD and other suitable methods.
In some embodiments, operation 706 further comprises forming one or more through array contacts.Such as Fig. 4 C institute
Show, is formed on the second silicon substrate 402 through array contacts 431.It is extended vertically through array contacts 431 and through grade layer heap
Stack 414.In some embodiments, the isolated area 406 of the second silicon substrate 402 is entered through one end of array contacts 431.Some
In embodiment, grading layer can be extended vertically through by using dry/wet etching technics through array contacts 431 to be formed by being formed
The opening of storehouse 414, then by conductor material fills openings.In some embodiments, other materials such as insulating materials 433
Divide the filling opening to reach isolation purpose.It in some embodiments, include conductive material through array contacts 431, it is conductive
Material includes but is not limited to the combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or the above material.In some embodiments, it uses
Conductor material or other materials, which fill the opening, can use ALD, CVD, PVD and/or other suitable methods.
In some embodiments, operation 706 further comprises forming one or more word line contact points.As shown in Figure 4 C,
Word line contact point 425 is formed on the second silicon substrate 402.Word line contact point 425 extends vertically and through insulating layer 423.One
In a little embodiments, one end of word line contact point 425 is located in the wordline of NAND string.For example, a conductor layer 416 can be used as
One wordline of NAND string.Word line contact point 425 is electrically connected to conductor layer 416 as a result,.In some embodiments, each word
Line contact point 425 is connect with a conductor layer 416, and conductor layer 416 is addressable by word line contact point as a result,.One
In a little embodiments, word line contact point 425 can be further disposed on silicon substrate 402 or NAND string (for example, selection door 428 and/
Or selection door 430) selection door on.In some embodiments, forming word line contact point 425 includes being etched using dry/wet
Technique is formed through the vertical openings of insulating layer 423, then by conductor material or other materials, such as it is conductor filled,
Bonding and/or other purpose barrier materials fill the opening.In some embodiments, leading through array contact point 425
Body material is made of conductor material, including but not limited to the combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or the above material.?
In some embodiments, using conductor material or other materials fill the opening can using ALD, CVD, PVD and/or other
Suitable method.
Exemplary method 700 continues at operation 708, as shown in fig. 7, forming array interconnection layer in multiple NAND strings.Such as figure
Shown in 4D, array interconnection layer 438 is formed in multiple NAND strings 418.Array interconnection layer is used for transmission NAND string and other circuits
Between electric signal.In some embodiments, forming array interconnection layer 438 includes forming insulating layer 434, then forms multiple positions
Line contact 432 contacts in insulating layer 434 and with NAND string 418.In some embodiments, insulating layer 434 is one layer or more
Layer insulating materials, such as silica, silicon nitride, silicon oxynitride or a combination thereof.In some embodiments, bit line contact 432
Forming process are as follows: form opening first in insulating layer 434, then fill the opening using conductor material or insulating materials.
In some embodiments, the conductor material for manufacturing bit line contact 432 includes but is not limited to tungsten, cobalt, copper, aluminium, doped silicon, silicide
Or the combination of the above material.In some embodiments, filling the opening using conductor material or other materials can use
ALD, CVD, PVD and/or other suitable methods.
In some embodiments, forming array interconnection layer 438 further comprises forming multiple wordline on insulating layer 437 to lead to
Hole contact 437.In some embodiments, each wordline through-hole contact 437 and the end thereof contacts of word line contact point 425 are with can
It is electrically connected.In some embodiments, wordline through-hole contact 437 is open by being formed in insulating layer 434, then using leading
Body material is filled to be formed.In some embodiments, before filling conductor material, material is for example isolated using other materials
Material is partially filled with the opening to enhance the viscosity or filling capacity of the conductor material.In some embodiments, wordline is formed
Through-hole contact conductor material include but is not limited to tungsten, cobalt, copper, aluminium, doped silicon, silicide or or the above material combination.?
In some embodiments, fill the opening using conductor material and isolated material, can using ALD, CVD, PVD and/or other
Suitable method.
In some embodiments, forming array interconnection layer 438 further comprises forming other conductive layers, such as in insulating layer
Conductor layer 440 and conductor contact layer 444 in 434.In some embodiments, there are one or more conductor layers 440 and/or lead
Body contact layer 444.In some embodiments, it manufactures conductor layer 440 and the conductor material of conductor contact layer 444 includes but is not limited to
The combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or the above material.The technique for forming conductor layer and conductor contact layer can adopt
With well known back-end process method.
In some embodiments, forming array interconnection layer 438 further comprises forming top conductive layer 442 and top insulation
Layer 436.In some embodiments, the conductor material for manufacturing top conductive layer 442 includes but is not limited to tungsten, cobalt, copper, aluminium, doping
The combination of silicon, silicide or the above material.In some embodiments, the insulating materials for manufacturing top layer 436 includes but not
It is limited to the combination of silica, silicon nitride, silicon oxynitride or above-mentioned material.
Fig. 5 A-5C is the above-mentioned array device of combination of embodiment according to the present invention and the step schematic diagram of peripheral components；
Fig. 8 is the flow chart of the exemplary method 800 in conjunction with above-mentioned array device and peripheral components.
Illustrative methods 800 start from step 802, as shown in figure 8, by the array device turned upside down on the second silicon substrate
So that array interconnection layer is located at below the second silicon substrate, and array interconnection layer and peripheral interconnection layer are aligned.Such as Fig. 5 A institute
Show, array interconnection layer 438 is placed in 402 lower section of the second silicon substrate.In some embodiments, aligned array interconnection layer 438 and outer
The method for enclosing interconnection layer 322 is the conductor layer 442 of aligned array interconnection layer 438 and the conductor layer 320 of peripheral interconnection layer 322.Such as
This, when array device and peripheral components combination, conductor layer 442 is contacted with 320.
Illustrative methods 800 continue at step 804, as shown in figure 8, associative array interconnection layer and peripheral interconnection layer.Such as figure
Shown in 5B, array interconnection layer 438 and peripheral interconnection layer 322 combine and form bonding interface 503.In some embodiments, as schemed
Shown in 5A, when before two interconnection layers combine or combining, treatment process 502 can be used for reinforcing array interconnection layer and periphery interconnection
Binding force between layer.In some embodiments, insulating layer 436 is silicon oxide layer and insulating layer 318 is silicon nitride layer.Some
In embodiment, insulating layer 436 is silicon nitride layer and insulating layer 318 is silicon oxide layer.In some embodiments, treatment process 502
Including plasma-treating technology, the surface of array interconnection layer and the surface of peripheral interconnection layer are handled to enhance in two insulating layers
The chemical bonding formed between 436 and 318.In some embodiments, treatment process 502 includes wet chemical process technique, place
The surface of array interconnection layer and the surface of peripheral interconnection layer are managed to enhance the chemistry formed between two insulating layers 436 and 318
In conjunction with.
In some embodiments, treatment process 502 is heat treatment process, is carried out in combined process.In some embodiments
In, the operation temperature of heat treatment is 250 DEG C to 600 DEG C.In some embodiments, heat treatment process makes conductor layer 442 and 320
Between generate counterdiffusion.Conductor 442 and 320 is mutually mixed after combination processing as a result,.In some embodiments, conductor layer 442
It is all made of copper with 320.
Illustrative methods 800 continue at step 806, as shown in figure 8, the second silicon substrate is thinned to form a monocrystalline silicon
Layer.As shown in Figure 5 B, according to an embodiment of the invention, the second silicon substrate 402 is thinned to form monocrystalline silicon layer 504.In some realities
It applies in example, by being thinned, the thickness of monocrystalline silicon layer 504 is between 200nm to 5000nm.In some embodiments, monocrystalline silicon
The thickness of layer 504 is between 150nm to 50 μm.In some embodiments, the technique that second silicon substrate 402 is thinned includes
But it is not limited to grinding wafer, dry etching, wet etching, chemically mechanical polishing or the combination of above-mentioned technique.
Illustrative methods 800 continue at step 808, as shown in figure 8, on monocrystalline silicon layer formed back-end process interconnection layer and
Laying.As shown in Figure 5 C, back-end process interconnection layer and laying 512 are formed on monocrystalline silicon layer 504.In some embodiments,
Back-end process interconnection layer includes one or more insulating layers 506, one or more contacts 508 and one or more conductor layers 510.
In some embodiments, insulating layer 506 is the combination of multiple insulating layers, and the multiple insulating layer can pass through independent step system
Make.In some embodiments, contact 508, conductor layer 510 and laying 512 can be made of an electrically conducting material, including but not limited to
The combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or the above material.In some embodiments, the insulation of insulating layer 506 is manufactured
Material includes but is not limited to the combination of silica, silicon nitride, silicon oxynitride or above-mentioned material.In some embodiments, insulating layer
506 can further comprise high K insulating materials.In some embodiments, laying 512 is connect in the battle array of combination with external circuit
Column/electric signal is transmitted between peripheral components and external circuit.
In short, the present invention is avoided mutual when two device manufactures by separating the production of array device and peripheral components
The manufacturing process for mutually influencing other side solves the production of subsequent layer in the prior art temperature limiting after by the layer production of front
Problem obtains high device density and good peripheral components performance.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (10)
1. a kind of nand memory, comprising:
Silicon substrate；
One or more peripheral components；
The one or more NAND strings being formed in above the peripheral components；Wherein, each NAND string include: multiple conductors/
Insulator lamination；
The monocrystalline silicon layer being formed in above one or more of NAND strings, the monocrystalline silicon layer is as silicon substrate and with described one
A or multiple NAND strings connect, and
The first interconnection layer of one or more being formed between one or more of peripheral components and one or more NAND strings；
The memory further comprises:
The second interconnection layer being formed in above the multiple NAND string；
Through array contacts, the multiple conductor/insulation body lamination and the monocrystalline silicon layer are passed vertically through, connects described first mutually
Join layer and second interconnection layer.
2. a kind of nand memory as described in claim 1, wherein each NAND string further include:
Extend vertically through the channel semiconductor of the multiple conductor/insulation body lamination；
The tunnel layer being formed between the multiple conductor/insulation body lamination and the channel semiconductor；
And the memory cell layers being formed between the tunnel layer and multiple conductor/insulation body laminations.
3. a kind of nand memory as claimed in claim 2 further comprises one or more first contacts, wherein each
First contact extends vertically and has and contacts with the conductor layer of the multiple conductor/insulation body lamination of the NAND string
Upper end, and wherein, each the first contact is formed in the lower end of the conductor layer, and connects with conductor layer.
4. a kind of nand memory as claimed in claim 2 further comprises one or more second contacts, wherein described the
Two contacts pass vertically through the multiple conductor/insulation body lamination, and the upper end of second contact connects with the monocrystalline silicon layer
Touching connection.
5. a kind of nand memory as claimed in claim 2, wherein second interconnection layer is formed in comprising one or more
Conductor layer in one or more insulating layers.
6. a kind of nand memory as described in claim 1, wherein the multiple NAND string includes being formed in another NAND
A NAND string on string.
7. a kind of nand memory as claimed in claim 6, wherein the NAND string being formed in another NAND string
It is connect by the conductor part being formed between the NAND string and another NAND string with another NAND string.
8. a kind of method for manufacturing nand memory, comprising:
One or more peripheral components are formed on the first silicon substrate；One or more NAND strings are formed on the second silicon substrate；
Form one or more first contacts, wherein each NAND string includes: multiple conductor/insulation body laminations；Each described first
Contact extends vertically and the contact jaw with one with the conductor layer of multiple conductor/insulation body laminations of the NAND string；
One or more of NAND strings are placed on above one or more of peripheral components, so that the second silicon substrate
Above one or more of NAND strings；
One or more of NAND strings and one or more of peripheral components are combined together by combination processing；And
Second silicon substrate is thinned to form it into the monocrystalline silicon layer above one or more of NAND strings, the monocrystalline silicon
Layer is used as silicon substrate.
9. method according to claim 8, wherein forming the NAND string includes: to form multiple lead on the second silicon substrate
Body/insulator lamination.
10. method according to claim 8, further comprise be formed in it is one or more above second silicon substrate
First interconnection layer of a NAND string, to connect the NAND string and one or more of peripheral components.
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| CN201710716657.1A CN107658315B (en) | 2017-08-21 | 2017-08-21 | Semiconductor device and preparation method thereof |
| JP2020502283A JP7304335B2 (en) | 2017-08-21 | 2018-03-01 | NAND memory device and method for forming NAND memory device |
| EP18849168.2A EP3580782A4 (en) | 2017-08-21 | 2018-03-01 | Three-dimensional memory devices and methods for forming the same |
| PCT/CN2018/077750 WO2019037403A1 (en) | 2017-08-21 | 2018-03-01 | Three-dimensional memory devices and methods for forming the same |
| CN201880005615.XA CN110121779B (en) | 2017-08-21 | 2018-03-01 | Three-dimensional memory device and method for forming the same |
| KR1020197037473A KR102369603B1 (en) | 2017-08-21 | 2018-03-01 | 3D memory device and method for forming the same |
| TW110114393A TW202129923A (en) | 2017-08-21 | 2018-03-15 | Three-dimensional memory devices and methods for forming the same |
| TW107108765A TWI722275B (en) | 2017-08-21 | 2018-03-15 | Three-dimensional memory devices and methods for forming the same |
| US16/047,251 US11211397B2 (en) | 2017-08-21 | 2018-07-27 | Three-dimensional memory devices and methods for forming the same |
| US17/102,625 US11805646B2 (en) | 2017-08-21 | 2020-11-24 | Three-dimensional memory devices and methods for forming the same |
| JP2022141341A JP2022172300A (en) | 2017-08-21 | 2022-09-06 | NAND memory device and method for forming NAND memory device |
| US18/244,688 US20230422504A1 (en) | 2017-08-21 | 2023-09-11 | Three-dimensional memory devices and methods for forming the same |
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| JP2019160833A (en) * | 2018-03-07 | 2019-09-19 | 東芝メモリ株式会社 | Semiconductor device |
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| CN108598084B (en) * | 2018-04-27 | 2019-08-30 | 长江存储科技有限责任公司 | Semiconductor devices and its manufacturing method |
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