CN107658315A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN107658315A CN107658315A CN201710716657.1A CN201710716657A CN107658315A CN 107658315 A CN107658315 A CN 107658315A CN 201710716657 A CN201710716657 A CN 201710716657A CN 107658315 A CN107658315 A CN 107658315A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The present invention relates to a kind of nand memory and preparation method thereof, nand memory includes：Silicon substrate；Multiple peripheral components；The multiple NAND strings formed above the peripheral components；The monocrystalline silicon layer formed above the multiple NAND string, the monocrystalline silicon layer contact connection, and the interconnection layer of one or more first formed between the multiple peripheral components and multiple NAND strings with the multiple NAND string.The present invention is by the way that the making of array device and peripheral components is separated, can be avoided interacting during the manufacture of two devices the manufacturing process of other side, therefore solve the problems, such as the making of layer behind in the prior art made by layer above after temperature limiting, so as to obtain good peripheral components performance.It is superimposed upon additionally, due to array device on peripheral components, realizes high device density.
Description
Technical field
The present invention relates to a kind of nand memory and preparation method thereof, more particularly to a kind of formation 3D nand flash memories
Nand memory and preparation method thereof.
Background technology
With the continuing emphasis to highly integrated electronic installation, to higher speed and lower Power operation and having
Lasting demand be present in the semiconductor memory of the device density of increase.To reach this purpose, having been developed has
Smaller size of device and the multilayer device with the transistor unit arranged with horizontal and vertical array.3D NAND are industries
A kind of emerging flash type researched and developed, solve 2D or plane nand flash memory band by the way that memory grain is stacked
The limitation come.
The nand flash memory of planar structure close to its actual extended limit, brings sternness to choose to semiconductor memory industry
War.New 3D NAND technologies, vertical stacking multi-layer data memory cell, possesses the precision of brilliance.Based on the technology, can beat
Produce the storage device that memory capacity is up to several times than similar NAND technology.The technology can be supported to receive more in smaller space content
High storage capacity, and then bring very big cost savings, energy consumption to reduce, and significantly performance boost to meet numerous disappear comprehensively
Take class mobile device and require the demand of most harsh enterprise's deployment.
In one approach, planar memory cell (such as nand memory unit) forms the horizontal array in routine
In.Then multiple horizontal arrays stack in vertical direction.Due to being required in minimum feature size is realized for each layer
Critical photolithographic steps, thus the limitation related to the method include resulting device in reliability it is low and be difficult pass through light
Realize that 16nm is manufactured quarter, so as to be difficult further to improve memory capacity.In addition, in such configuration, selected for drive control
The size of the driving transistor of door is the function of the number of plies；Therefore, the scale of driving transistor is the multiple of the number of plies.This can cause to collect
The problem of into the problem of change and in terms of radiating.In another approach, the multilayer with vertical orientated raceway groove has been developed
Memory.In a construction, multiple selection gate layer are formed on substrate, and vertical-channel passes through the plurality of selection gate layer.Every
In individual vertical-channel, lower selection gate layer is configured to function as lower selection door (lower select gate), multiple middle grid layer structures
Make to be configured to function as selecting door (upper select gate) as control gate, upper selection gate layer.It is connected to the first water
Square upwards upper selection door adjacent to each other for use as device row select line.It is connected in the second horizontal direction adjacent to each other
Vertical-channel for use as device bit line (bit line).The achievement that other methods for attempting vertical orientated raceway groove have been achieved with has
Limit.
At present, on 3D nand flash memory technologies, at home and abroad existing extensive patent application.Such as Chinese invention patent
Application publication number CN101483194A, a kind of vertical-type non-volatile memory device and its manufacture method are disclosed.Partly led at this
In body device and its manufacture method, device includes the substrate of horizontally extending single-crystal semiconductor material and in the substrate
On multiple interlevel dielectric layers.Multiple selection door patterns are provided, each to select door pattern dielectric layer between adjacent lower
Between adjacent upper between dielectric layer.The vertical-channel of semi-conducting material is extends in the vertical direction through multiple interlayer dielectrics
Layer and selection door pattern, select door insulating barrier it is each selection door pattern and vertical-channel between and make selection door pattern with it is vertical
Raceway groove insulate.As shown in Figure 1, it is the profile of the vertical channel transistor structure device.The vertical channel transistor structure device is under
To above sequentially forming Si substrate layers 300, peripheral circuit region 302 and array device layer.
But the shortcomings that above-mentioned patented technology is, above-mentioned vertical channel transistor structure device is due to only on a Si substrate layer
Sequentially built, the temperature when making of device (such as NAND string) below is caused to have limited, otherwise can be because of temperature mistake
High and ion (such as NMOS and PMOS devices manufactured on a silicon substrate in the ion implanted layer of device that causes above to make
Part) ion diffusion is produced, so that the combination depth between device is difficult control, so as to influence properties of product.That is
The requirement manufactured between each layer can limit from each other.
In addition, after manufacturing peripheral components 302 on a silicon substrate in above-mentioned patent, NAND is formed at the top of peripheral components 302
Device.In this way, NAND device is isolated with silicon substrate.So NAND device needs to use an active layer to substitute silicon substrate, from
And device performance is caused to decline.
How the interacting of in manufacturing process each interlayer is avoided, and the performance for ensureing product is current to need to solve
Problem.
The content of the invention
The purpose of the present invention is achieved through the following technical solutions.
For above-mentioned problem, the invention discloses a kind of semiconductor device, include successively from down to up：Silicon substrate
Plate, the peripheral components formed on the silicon substrate, one or more interconnection layers and the formation formed on the peripheral components
Array device on one or more interconnection layers.In certain embodiments, the array device further comprises being formed in institute
State the monocrystalline silicon layer of array device upper end.
In certain embodiments, the semiconductor device further comprises being formed multiple back segment systems above array device
Journey (back-end-of-line, BEOL) interconnection layer and laying.
In certain embodiments, peripheral components include multiple gold oxygen semiconductor field effect transistors (MOSFETs).At some
In embodiment, the peripheral components are formed on a silicon substrate.In certain embodiments, the silicon substrate has doped region and isolation
Area.In certain embodiments, the gold oxygen semiconductor field effect transistor (MOSFETs) of the peripheral components is used as memory not
Congenerous device, such as page buffer, sensor amplifier, column decoder or line decoder.
In certain embodiments, one or more interconnection layers include periphery interconnection；In certain embodiments, the periphery is mutual
Company includes multiple interconnection layers and contact layer.In certain embodiments, the interconnection layer includes multiple metal levels.The metal level can
To be made up of tungsten, copper, aluminium or other suitable materials.In certain embodiments, the contact layer can by tungsten, copper, aluminium or other
Suitable material is made.In certain embodiments, one or more of interconnection layers are formed in different periphery transistors
Between transmit electric signal, or electric signal is transmitted between periphery transistor and array device.
In certain embodiments, one or more interconnection layers include array interconnection.In certain embodiments, the array is mutual
Connection includes multiple interconnection layers and contact layer.In certain embodiments, the interconnection layer includes multiple metal levels.The metal level can
To be made up of tungsten, copper, aluminium or other suitable materials.In certain embodiments, the contact layer can by tungsten, copper, aluminium or other
Suitable material is made.In certain embodiments, the periphery is interconnected and form for being transmitted between the different zones of array device
Electric signal, or electric signal is transmitted between periphery transistor and array device.
In certain embodiments, the array device includes multiple NAND strings.In certain embodiments, the array device
Further comprise interconnection layer of multiple formation below the multiple NAND string.In certain embodiments, the array device enters
One step includes the monocrystalline silicon layer formed above the NAND string.In certain embodiments, the monocrystalline silicon layer is silicon substrate
A part is simultaneously thinned in subsequent technique by suitable technology, such as backgrind, wet/dry ecthing, and/or chemical machinery
Polishing technology.In certain embodiments, the monocrystalline silicon layer contacts with the multiple NAND string.In certain embodiments, it is described
The thickness of monocrystalline silicon layer is between 200 nanometers to 50 microns.In certain embodiments, the thickness of the monocrystalline silicon layer between
Between 500 nanometers to 10 microns.In certain embodiments, the thickness of the monocrystalline silicon layer is between 500 nanometers to 5 microns.
In certain embodiments, the monocrystalline silicon layer is partly or entirely adulterated using n-type and/or p-type dopant.
In certain embodiments, each NAND string includes：Vertical direction extend across the multiple conductor/absolutely
The channel semiconductor (such as silicon passage) of edge body lamination.Each such conductor layer or insulator layer can be referred to as a grade
Layer.Multiple conductor/insulation body laminations may also be referred to as grade layer stack.Conductor layer may be used as wordline (or control door).It is multiple
Layer can be between conductor layer and channel semiconductor.In certain embodiments, the multiple layer includes tunnel layer, for example, tunnel
Road oxide skin(coating), the charging storage that electronics or hole in channel semiconductor can pass through this layer of tunnel layer tunnelling to NAND string are single
In first layer.In certain embodiments, the multiple layer includes that the memory cell layers of electric charge can be stored.Electricity in memory cell layers
The storage or removal of lotus determine the open/close state of channel semiconductor.In certain embodiments, memory cell layers can be by polycrystalline
Silicon layer or silicon nitride layer are made.In certain embodiments, the multiple layer further comprises barrier layer, such as a silicon oxide layer
Or one by three layers of composite bed formed of silicon oxide/silicon nitride/silicon oxide (ONO).In certain embodiments, the barrier layer can
To further comprise a high k dielectric layer (such as aluminum oxide).
In certain embodiments, the NAND string further comprises a silicon epitaxial layers, and its formation is led in the semiconductor
The upper end in road.In certain embodiments, monocrystalline silicon layer epitaxial growth of the silicon epitaxial layers above the NAND string.
In certain embodiments, the NAND string further comprises selecting door, and it is by one in grade layer stack or more
Individual upper conductor layer is formed.In certain embodiments, the ON/OFF shape of the channel semiconductor of NAND string described in the selection gate control
State.In certain embodiments, the selection door of the NAND string is formed by an independent conductor layer above grade layer stack.One
In a little embodiments, the NAND string further comprises forming selection door by one or more of grade layer stack lower conductor layer.
In certain embodiments, the selection door of the NAND string is formed by an independent conductor layer below grade layer stack.
In certain embodiments, the NAND string connects source by forming the doped region of the monocrystalline silicon layer above NAND string
Contact.In certain embodiments, the doped region of the monocrystalline silicon layer is adulterated by p-type dopant.In certain embodiments, the source
Contact extends vertically through grade layer stack and contacted in upper end with monocrystalline silicon layer.In certain embodiments, the source contact
Bottom and one or more contacts formed below the contact of source.
In certain embodiments, array device further comprises multiple wordline contacts.In certain embodiments, it is the multiple
Wordline contact extends vertically and each end with one with word line contact of the multiple wordline contact, thus, array
The wordline of device can be addressed respectively by wordline contact.In certain embodiments, each wordline contact is formed in wordline
Under and be connected with the wordline.In certain embodiments, multiple wordline contacts are by using wet etching or dry etching shape
Into contact hole or contact trench, then the contact hole hole or contact trench are filled using conductor (such as tungsten).At some
In embodiment, filling contact hole or contact trench are included in deposition barrier layer and/or tack coat before the deposition conductor.At some
In embodiment, the wordline contact is initially formed above wordline, then by wafer turned upside down so that wordline contact position
Below wordline.
In certain embodiments, NAND string interconnection layer formed below includes multiple bit line contacts, its with it is described
The bottom contact of NAND string.In certain embodiments, the contact hole of multiple institute's bit line contacts is independent mutually.In some embodiments
In, institute's bit line contact connects each NAND string so that each NAND string can address individually by contact.In some realities
Apply in example, the generation type of institute's bit line contact is as follows：Contact hole or contact ditch are formed by wet etching or dry etching first
Groove, then fill the contact hole or contact trench using conductor (such as tungsten).In certain embodiments, using chemical vapor deposition
Area method (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD) complete the filling of contact hole or contact trench.
In certain embodiments, institute's bit line contact is initially formed above NAND string, then by wafer turned upside down so that position
Line contact is located at below NAND string.
In certain embodiments, one or more interconnection layers further comprise bonding interface.In certain embodiments, it is described
Bonding interface can be formed between two insulating barriers, such as between silicon nitride layer and silicon oxide layer.The bonding interface also may be used
To be formed between the two metal layers, such as between a layers of copper and another layers of copper.In certain embodiments, the cohesive boundary
Face can be including the interface between insulating barrier or including the interface between metal level.In certain embodiments, boundary is bonded
Face is formed by the chemical bonding between the insulating barrier of bonding interface both sides and/or conductor layer.In certain embodiments, bond
Interface is formed by the Physical interaction (such as counterdiffusion) between the insulating barrier of bonding interface both sides and/or conductor layer.
In certain embodiments, before combined process, by being formed after carrying out corona treatment to the surface of bonding interface both sides
The bonding interface.In certain embodiments, before combined process, by being heat-treated to the surface of bonding interface both sides
After form the bonding interface.
In certain embodiments, the memory further comprises multiple grades layer stack.In certain embodiments, in phase
Intermediate depot layer can be formed between adjacent grade layer stack.In certain embodiments, the intermediate depot layer connection upside grading layer
The NAND string of storehouse and the NAND string of downside grade layer stack.In certain embodiments, the sum of the NAND string of upside grade storehouse
The NAND string of downside grade layer stack is electrically connected by the conductor part of intermediate depot layer to form longer NAND string.
In certain embodiments, described device further comprise it is the multiple run through array contacts, the array of implementing touches
Point extends vertically through the grade storehouse or multiple grades storehouse.In certain embodiments, it is multiple both to connect through array contacts
The NAND string of grade layer stack multiple interconnection layers formed below are connect, are also formed above the NAND string of connection grade layer stack more
Individual interconnection layer.In certain embodiments, the multiple generation type through array contacts is as follows：Formed first by dry etching
Contact hole and/or contact trench, then fill the contact hole or contact ditch using conductor material (such as tungsten, copper or silicide)
Groove.
In certain embodiments, the BEOL interconnection layers of formation are used for the electric signal of transferring semiconductor device, including battle array
The electric signal of row device and peripheral components.In certain embodiments, the laying of formation is used for transferring semiconductor device
Electric signal is to external electric signal passage.In certain embodiments, the BEOL interconnection layers include interconnection conductors layer and contact layer.Institute
Stating interconnection conductors layer and contact layer includes conductive material, such as tungsten, copper, aluminium, silicide, and/or other suitable conductive materials.
In some embodiments, substrate layer includes conductor, such as tungsten, copper, aluminium, silicide and/or other suitable conductive materials.
For above-mentioned problem, the invention also discloses a kind of preparation method of semiconductor device.Wherein, half is prepared
Conductor installation method comprises the following steps:
Form peripheral components；
Form array device；
By the peripheral components and array device it is positioned opposite and by bonding interface with reference to the peripheral components and array
Device.
Preferably, wherein, peripheral components is prepared and are specifically comprised the following steps：
Form the first silicon substrate；
Peripheral components are formed on the first silicon substrate, wherein the peripheral components include MOS transistor；
Periphery interconnection is formed above the peripheral components.
Preferably, wherein, prepare array device and specifically comprise the following steps：
Form the second silicon substrate；
Doped region and isolated area are formed in second silicon substrate；
One or more NAND strings are formed on second silicon substrate；Wherein, each NAND string includes：It is multiple to lead
Body/insulator lamination, the channel semiconductor of the multiple conductor/insulation body lamination, multiple shapes are extended across in vertical direction
Into the memory cell between the channel semiconductor and conductor layer, formed between the memory cell and channel semiconductor
Tunnel layer, the barrier layer formed between memory cell and conductor layer, and form the monocrystalline silicon in the channel semiconductor bottom
Epitaxial layer；Wherein, one or more of NAND strings contact with second silicon substrate.In certain embodiments, the monocrystalline
Silicon epitaxy layer is from the second silicon substrate epitaxial growth；Wherein, one or more of NAND strings further comprise being formed
The selection door of NAND string one end.
Array interconnection layer is formed in NAND string, wherein the step of forming array interconnection layer includes being formed and one or more
The bit line contact of individual NAND string contact.Array interconnection layer is formed to further comprise forming one or more interconnection layers and contact layer,
Wherein described interconnection layer and contact layer include conductive material, such as tungsten, aluminium, copper, and/or other suitable materials.
According to some embodiments, the source contact that array interconnection layer further comprises forming one or more NAND strings is formed.
In certain embodiments, the source contact extends through multiple conductor/insulation body laminations vertically.In certain embodiments, institute
The one end for stating source contact contacts with second silicon substrate, and the other end contacts with the interconnection layer of array contacts.In some implementations
In example, the source contact is electrically connected with one or more NAND strings by the second silicon substrate.
Adhesion step specifically includes：The peripheral components and the array device are positioned opposite and glued by bonding interface
Knot is combined, and the dorsal part of the second layer-of-substrate silicon is then thinned, and Pad layers are formed on the dorsal part, and is formed BEOL on PAD layers and be situated between
Matter layer.
Peripheral components and array device are combined in bonding interface, wherein being wrapped with reference to the step of peripheral components and array device
Include：The array device is inverted, array interconnection layer of the alignment surface to peripheral components and the peripheral interconnection layer in face of array device,
Array device is positioned on peripheral components, so that the surface of array interconnection layer contacts the surface of peripheral interconnection layer, held
Row combines processing to form bonding interface.In certain embodiments, plasma-treating technology, wet processing are included with reference to processing
And/or Technology for Heating Processing, to cause in face of the surface of array interconnection layer of bonding interface and the surface formation of peripheral interconnection layer
Reason or chemical bond.In certain embodiments, the surface of array interconnection layer includes the table of a silicon nitride layer and peripheral interconnection layer
Face includes a silicon oxide layer.In certain embodiments, the surface of array interconnection layer includes a silicon oxide layer and periphery interconnects
The surface of layer includes a silicon nitride layer.In certain embodiments, the table of the surface conductor of array interconnection layer and peripheral interconnection layer
Face conductor includes copper.
In certain embodiments, the combination of array interconnection layer and periphery interconnection layer surface is by the insulating barrier in both sides
Form what Physical interaction (such as counterdiffusion) was completed between (such as silicon nitride layer or silicon oxide layer) and/or conductor layer.Battle array
Interface between row interconnection layer and periphery interconnection layer surface is combination interface.In certain embodiments, it is right before combined process
The corona treatment of array interconnection layer and periphery interconnection layer surface can strengthen the adhesion between two surfaces.In some realities
Apply in example, before combined process, the wet processing processing of layer surface is interconnected to array interconnection layer and periphery can strengthen two
Adhesion between surface.In certain embodiments, array interconnection layer is positioned on peripheral interconnection layer includes aligned array
The contact region of interconnection layer and peripheral interconnection layer, it can be connect so as to the contact region of two interconnection layers when both sides are combined together
Touch.In certain embodiments, when the surface of array interconnection layer and peripheral interconnection layer contacts, heat treatment operation is performed.At some
In embodiment, this heat treatment promotes the mutual expansion between array interconnection layer and the conductive material (such as copper) of peripheral interconnection layer
Dissipate.
In certain embodiments, one or more bonding interfaces can be formed in a manufacturing method.In certain embodiments,
Multiple array devices are combined with a peripheral components.In certain embodiments, an array device can be with multiple peripheral components
With reference to.In certain embodiments, multiple array devices are combined with multiple peripheral components.
In certain embodiments, array device includes multiple grades layer stack.Each grade layer stack include multiple conductors/
Insulating barrier.In certain embodiments, intermediate depot layer can be formed between adjacent rank layer stack.In certain embodiments, institute
State the intermediate depot layer connection upside NAND string of grade layer stack and the NAND string of downside grade layer stack.
After associative array device and peripheral components, the second silicon substrate of the array device is thinned.In some implementations
In example, the technique that the second silicon substrate is thinned is completed by chemical-mechanical planarization (CMP) technique.In certain embodiments, it is thinned the
The technique of two silicon substrates can also be completed by other appropriate process, for example, wet etching and/or dry etching.
Because array device and peripheral components are independently formed, formed array device/array interconnection layer and peripheral components/
The process sequence of peripheral interconnection layer can exchange.
The advantage of the invention is that：
The present invention is completed by the way that the making of array device and peripheral components is divided among on two silicon chips, can avoid two
Device interacts the manufacturing process of other side when manufacturing, therefore solves the making of the layer behind in the prior art by layer above
After making the problem of temperature limiting.
Semiconductor device disclosed by the invention, by the way that array device layer to be arranged on to the top of peripheral circuit layer, so as to increase
The density of device is added.And the preparation method of peripheral circuit layer and array device layer is simplified, it is preferably outer so as to obtain
Enclose circuit layer performance (for example, CMOS performances).The raising of CMOS performances is due to that peripheral circuit and array device are prepared respectively, is made
Obtain the high-temperature technology of back segment array device is not influenceed on leading portion peripheral components, and the performance of back end device, which can get a promotion, (to be compared
As dopant does not have extra diffusion, for example the junction depth that ion implanting is formed can be with relatively good control, etc..)
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 is the profile of traditional vertical channel transistor structure device.
Fig. 2 is the structural representation according to the nand memory of embodiment of the present invention；
Fig. 3 A-3D are the preparation process schematic diagrames according to the peripheral components of the nand memory of embodiment of the present invention；
Fig. 4 A-4D are the preparation process schematic diagrames according to the array device of the nand memory of embodiment of the present invention；
Fig. 5 A-5C are to bond to obtain the system of nand memory with peripheral components according to the array device of embodiment of the present invention
Standby step schematic diagram.
Fig. 6 is the flow chart to form peripheral components and peripheral interconnection layer exemplary method 600.
Fig. 7 is the flow chart to form array device and array interconnection layer exemplary method 700.
Fig. 8 is the flow chart of the exemplary method 800 of associative array device and peripheral components.
Embodiment
Embodiments of the invention are more fully described below in reference to accompanying drawing, the preferred embodiments of the present invention are shown in the accompanying drawings
Go out.However, the present invention can be implemented in a different manner, and it should not be construed as limited to embodiments described herein.Whole
Identical reference refers to identical element all the time in individual specification.
Although it should be appreciated that the grade of term first, second can be used to describe various elements here, these elements should not be limited
In these terms.These terms are used to make an element be different from another element.For example, the first element is properly termed as second yuan
Part, similarly, the second element are properly termed as the first element, without departing from the scope of the present invention.As used herein, term " and/
Or " include one or more listed by relevant item any and all combination.
It should be appreciated that when claim an element another element " on ", " being connected to " or during " being coupled to " another element, it can
With the element that another element is directly either connected or coupled on another element or can also have insertion.On the contrary, work as
Claim on an another element of element " directly existing " or during " being directly connected to " or " being directly coupled to " another element, in the absence of inserting
The element entered.Others be used to describe relation between element word should explain in a similar way (for example, " ... it
Between " relative to " between directly existing ... ", " adjacent " relative to " direct neighbor " etc.).Here when one element of title is in another element
When upper, it can be directly coupled to another element, or there may be the element of insertion, Huo Zheyuan in another element up or down
Part can be separated by space or gap.
Terminology used here is not intended to limit the present invention just for the sake of description specific embodiment.As used herein,
Clearly state unless the context otherwise, otherwise singulative " one " and "the" are intended to include plural form simultaneously.It should also manage
Solution, term " comprising ", " comprising ", " comprising " and/or " comprising ", when here in use, specifying the feature, entirety, step
Suddenly, the presence of operation, element and/or component, but it is not precluded from one or more other features, entirety, step, operation, member
The presence or addition of part, component and/or its combination.
As shown in Fig. 2 it is the schematic device junction composition according to the preferred embodiments of the present invention.Including first silicon substrate
Plate 202.In certain embodiments, the first silicon substrate 202 can be made up of monocrystalline silicon.In certain embodiments, the first silicon substrate 202
It can be made up of other suitable materials, such as, but not limited to, SiGe, germanium, silicon on insulator (SOI).Peripheral components are formed
On first silicon substrate 202.The peripheral components include multiple transistors 206.In certain embodiments, on the first silicon substrate 202
Formed with isolated area 204 and doped region 208.The peripheral covering transistor 206 of interconnection layer 222 is conducted with entering horizontal electrical signal.Interconnection layer
222 include one or more contacts, such as contact 207 and contact 214, one or more interconnection conductors layers, such as the He of layer 216
220.Interconnection layer 222 further comprises one or more layer insulations (ILD) layer, such as insulating barrier 210,212 and 218.Contact
It is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium, and/or silicide.Conductive layer is made of an electrically conducting material, including
But it is not limited to tungsten, cobalt, copper, aluminium, and/or silicide.Interlayer insulating film is made up of insulating materials, including but not limited to silica,
Silicon nitride, silicon oxynitride, and/or doped silicon oxide.
Array device is formed on peripheral components.Array device includes multiple NAND strings 230, and it extends through multiple lead
Body 234 and the lamination 242 of insulator 236.Multiple conductor/insulation body laminations 242 are also referred to as grade layer stack.In some embodiments
In, grade layer stack 242 can include more being made from a different material than multiple conductor/insulation body laminations and/or difference is thick
The conductor layer or insulating barrier of degree.In certain embodiments, conductor layer 234 is made of an electrically conducting material, including but not limited to tungsten, cobalt,
Copper, aluminium, doped silicon and/or silicide.Insulating barrier 236 is made up of insulating materials, including but not limited to silica, silicon nitride, nitrogen
The combination of silica or more material.Multiple NAND strings 230 include channel semiconductor 228 and dielectric layer 229.In some embodiments
In, channel semiconductor 228 is made up of noncrystalline, polycrystalline or monocrystalline silicon.In certain embodiments, dielectric layer 229 includes one
Tunnel layer, a memory cell layers and a barrier layer.The tunnel layer is made up of silica, silicon nitride or its combination.Institute
Barrier layer is stated to be made up of silica, silicon nitride, high dielectric constant insulating materials or its combination.Memory cell layers by silicon nitride,
The combination of silicon oxynitride, silicon or more material is made.
In certain embodiments, multiple NAND strings 230 include multiple control doors (or wordline).In certain embodiments, lead
Body layer 234 is used as the control door of NAND string.In certain embodiments, multiple NAND strings 230 further comprise selecting door 238, its
It is formed adjacent to the upper end of NAND string.In certain embodiments, multiple NAND strings 230 further comprise selecting door 240, and it is formed
Close to the lower end of NAND string.In certain embodiments, selection door 238 and 240 is made of an electrically conducting material, and is included but is not limited to
Tungsten, cobalt, copper, aluminium, doped silicon and/or silicide.
In certain embodiments, multiple NAND strings 230 further comprise silicon epitaxial layers 251, and it, which is covered, forms in NAND string
The upper end of 230 channel semiconductor 228.In certain embodiments, silicon epitaxial layers 251 from the epitaxial growth of monocrystalline silicon layer 244 and
Formed.
In certain embodiments, array device further comprises one or more source contacts 232, and it extends through grading layer
Storehouse 242.In certain embodiments, source contact 232 is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium, and/or
Silicide.
In certain embodiments, array device further comprises one or more wordline contacts 258.In some embodiments
In, multiple wordline contacts extend vertically in insulating barrier 259.In certain embodiments, each of multiple wordline contacts has
One with the end of word line contact, thus, each wordline of array device can be addressed respectively by wordline contact.One
In a little embodiments, each wordline contact forms under wordline and is connected with the wordline.In certain embodiments, multiple wordline
Contact forms contact hole or contact trench by using wet etching or dry etching, then fills institute using conductor (such as tungsten)
State contact hole or contact trench.In certain embodiments, filling contact hole or contact trench sink before being included in the deposition conductor
Product barrier layer and/or tack coat.
In certain embodiments, array device further comprises monocrystalline silicon layer 244, and it, which is covered, forms in NAND string 230
Upper end.In certain embodiments, monocrystalline silicon layer 244 is made up of monocrystalline silicon.In certain embodiments, monocrystalline silicon layer 244 can also
It is made up of other materials, including but not limited to SiGe or germanium.In certain embodiments, monocrystalline silicon layer 244 has doped region 250
With isolated area 246.
In certain embodiments, source contact 232 and NAND string 230 contact with the monocrystalline silicon layer 244, therefore work as monocrystalline
Silicon layer 244 conduct electric signal when, source contact 232 can be electrically connected with NAND string 230 (such as when monocrystalline silicon layer 244 formed lead
During the inversion layer of electricity).
In certain embodiments, array device further comprises that one or more runs through array contacts 241, its vertical extension
And run through grade layer stack 242.In certain embodiments, it is the multiple through array contacts 241 by electric signal from peripheral components
It is transferred to back-end process (BEOL) layer 254 or laying 256.
In certain embodiments, array interconnection layer 223 is formed in the top of peripheral interconnection layer 222.In certain embodiments,
Array interconnection layer 223 includes bit line contact 226, wordline through hole contact 257, one or more conductor layers (such as layer 224), and one
Individual or multiple insulating barriers (such as insulating barrier 225 and insulating barrier 221).The conductor layer can be made of an electrically conducting material, including but
It is not limited to tungsten, cobalt, copper, aluminium and/or silicide.The insulating barrier is made up of insulating materials, including but not limited to silica, nitridation
Silicon, high dielectric constant insulating materials or its combination.
Bonding interface 219 formed peripheral interconnection layer 222 insulating barrier 218 and array interconnection layer 223 insulating barrier 221 it
Between.In certain embodiments, bonding interface 219 can also be formed between conductor layer 224 and conductor layer 220.In some implementations
In example, insulating barrier 218 is silicon nitride layer and insulating barrier 221 is silicon oxide layer.In certain embodiments, insulating barrier 218 is oxidation
Silicon layer and insulating barrier 221 is silicon nitride layer.
In certain embodiments, bit line contact 226 contacts the bottom of multiple NAND strings 230.In certain embodiments, each
Bit line contact 226 contacts with a NAND string 230 respectively, so as to which bit line contact independently addresses each NAND string.
In certain embodiments, the wordline through hole contact 257 contacts with the low side of the multiple wordline contact 258.
In some embodiments, each wordline through hole contact 257 contacts with each wordline contact 258, and thus, wordline through hole can divide
Do not addressed respectively in each NAND string.
Preferred embodiment shown in Fig. 2 further comprises one or more back-end process interconnection insulating barriers and conductor layer (example
Such as conductor layer 248, conductor layer 254 and insulating barrier 252) and laying (such as laying 256).The back-end process interconnection layer and
Laying transmits electric signal between the device and external circuit of the embodiment.Back-end process conductor layer can be by conductive material
It is made, including but not limited to tungsten, cobalt, copper, aluminium and/or silicide.The back-end process insulating barrier is made up of insulating materials, including
But it is not limited to silica, silicon nitride, high dielectric constant insulating materials or its combination.Laying is made of an electrically conducting material, including
But it is not limited to tungsten, cobalt, copper, aluminium and/or silicide.
Fig. 3 A-3D are walked according to the preparation of the peripheral components and peripheral interconnection layer of the nand memory of embodiment of the present invention
Rapid schematic diagram；Fig. 6 is the flow chart to form peripheral components and peripheral interconnection layer exemplary method 600.
Exemplary method 600 starts from operation 602, as shown in fig. 6, forming peripheral components on the first silicon substrate.Such as figure
Shown in 3A, the first silicon substrate 302 is provide firstly, to form peripheral components in certain embodiments, peripheral components include more
Individual transistor device 304.The multiple transistor device 304 is formed on the first silicon substrate 302.In certain embodiments, shape
Include multiple steps, including but not limited to photoetching, dry/wet etching, thin film deposition, thermally grown, note into transistor device 304
Enter, the combination of chemical-mechanical planarization (CMP), and/or the above.In certain embodiments, doped region 308 is also formed in the first silicon
On substrate 302.In certain embodiments, isolated area 306 is also formed on the first silicon substrate 302.
Exemplary method 600 continues at operation 604, as shown in fig. 6, formed on peripheral components one or more insulating barriers and
Conductor layer.One or more of insulating barriers and conductor layer are a parts for peripheral interconnection layer, can transmit the electricity of peripheral components
Signal.As shown in Figure 3 B, the first layer insulating 310 is formed on the first silicon substrate 302, and contact layer 308 is formed and is electrically connected with
Peripheral components.As shown in Figure 3 C, the second insulating barrier 316 is formed on the first insulating barrier 310.In certain embodiments, second is exhausted
Edge layer 316 can be multiple layers of combination and be formed by independent process.Conductor layer 312 and contact layer 314 form exhausted second
In edge layer 316.In certain embodiments, conductor layer 312, contact layer 308 and conductor layer 314 are made of an electrically conducting material.Formation is led
The technique of body layer and contact layer can use thin film deposition technique, including but not limited to chemical vapour deposition technique (CVD), physics gas
Phase sedimentation (PVD) or atomic layer deposition method (ALD) and electroplating technology.Forming the technique of conductor layer and contact layer can also make
Etched with photoetching, chemical-mechanical planarization, dry/wet.Thin film deposition technique can be used by forming the technique of insulating barrier, including
But it is not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD).
Exemplary method 600 continues at operation 606, as shown in fig. 6, forming a top layer and one for peripheral interconnection layer
Individual top conductor layer.As shown in Figure 3 D, the 3rd insulating barrier 318 is formed on the second insulating barrier 316, and conductor layer 320 is formed
In three insulating barriers 318.It has been thusly-formed peripheral interconnection layer 322.Thin film deposition technique can be used by forming the technique of conductor layer, be wrapped
Include but be not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD) and galvanizer
Skill.Forming the technique of conductor layer and contact layer can also use photoetching, chemical-mechanical planarization, dry/wet to etch.Formed exhausted
The technique of edge layer can use thin film deposition technique, including but not limited to chemical vapour deposition technique (CVD), physical vaporous deposition
Or atomic layer deposition method (ALD) (PVD).
Fig. 4 A-4D are walked according to the preparation of the array device and array interconnection layer of the nand memory of embodiment of the present invention
Rapid schematic diagram；Fig. 7 is the flow chart to form array device and array interconnection layer exemplary method 700.
Exemplary method 700 starts from operation 702, as shown in fig. 7, forming doped region and isolated area on the second silicon substrate.
As shown in Figure 4 A, the second silicon substrate 402 is used to form array device.In certain embodiments, doped region 404 is formed in the second silicon
On substrate 402.In certain embodiments, isolated area 406 is formed on the second silicon substrate 402.Forming doped region 404 can use
Injection and/or diffusion technique.Thermally grown or thin film deposition can be used by forming the technique of isolated area 406.Photoetching and dry/wet
Etching technics can be used for forming isolated area pattern.
Exemplary method 700 continues at operation 704, as shown in fig. 7, forming multiple insulating barriers pair on the second silicon substrate.Such as
Shown in Fig. 4 B, multiple insulating barriers are formed on the second silicon substrate 402 to 410 and 412.In certain embodiments, multiple insulating barriers
To forming grade layer stack 408.In certain embodiments, insulating barrier is to including silicon nitride layer 410 and silicon oxide layer 412.One
In a little embodiments, there are more insulating barriers pair, the insulating barrier is to being made from a different material and having in grade layer stack 408
Different-thickness.In certain embodiments, thin film deposition technique can be used by forming the technique of multiple insulating barriers pair, including but unlimited
In chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD).
Exemplary method 700 continues at operation 706, as shown in fig. 7, forming multiple array devices on the second silicon substrate
NAND string.As shown in Figure 4 C, multiple NAND strings 418 are formed on the second silicon substrate 402.In certain embodiments, grading layer heap
The insulating barrier 410 of the insulating barrier centering of stack 408 could alternatively be conductor layer 416, multiple so as to be formed in grade layer stack 414
Conductor/insulation layer is right.In certain embodiments, the technique of insulating barrier 410 is replaced using conductor layer 416 can use for insulation
412 selective wet etching method etching insulating layer 410 of layer, it is this to etch or micro etching insulating layer 412, so
Conductor layer 416 is inserted after insulating barrier 410 is etched afterwards in the structure formed.In certain embodiments, filling conductor layer 416 can
To use CVD, ALD and other suitable methods.In certain embodiments, conductor layer 416 is made of an electrically conducting material, including but not
It is limited to tungsten, cobalt, copper, aluminium and/or silicide.In certain embodiments, NAND string is formed to further comprise forming channel semiconductor
420, it extends across the grade layer stack 414 in vertical direction.In certain embodiments, NAND string is formed further to wrap
Dielectric layer 422 is included, it is located at channel semiconductor 420 and multiple conductor/insulation layers between.In certain embodiments, dielectric layer
422 be multiple layers of combination, including but not limited to tunnel layer, memory cell layers and barrier layer.In certain embodiments, it is described
Tunnel layer includes the combination of insulating materials, including but not limited to silica, silicon nitride, silicon oxynitride or above-mentioned material.At some
In embodiment, the material that memory cell layers include can be used for storage operation NAND electric charge.The material of memory cell layers includes
But it is not limited to the combination of silicon nitride, silicon oxynitride or silica and silicon nitride or the combination of above-mentioned material.In some embodiments
In, the barrier layer includes insulating materials, such as a silicon oxide layer or one include silicon oxide/silicon nitride/silicon oxide (ONO)
Composite bed.In certain embodiments, the barrier layer may further include a high k dielectric layer (such as aluminum oxide).
In some embodiments, ALD, CVD, PVD and other suitable methods can be used by forming dielectric layer 422.
In certain embodiments, NAND string is formed to further comprise forming the epitaxial layer in described NAND string one end.Such as figure
Shown in 4C, epitaxial layer 426 is formed in the bottom of NAND string 418.In certain embodiments, epitaxial layer 426 is silicon layer, and it is with second
Silicon substrate 402 directly contacts and from the Epitaxial growth of the second silicon substrate 402.In certain embodiments, epitaxial layer 426 is further
It is doped to desired doped level.
In certain embodiments, operation 706 further comprises forming one or more source contacts.As shown in Figure 4 C, vertically
The source contact 424 for extending through grade layer stack 414 is formed on the second silicon substrate 402.In certain embodiments, source contact
424 one end directly contacts the doped region 404 of the second silicon substrate 402.In certain embodiments, source contact 424 passes through the second silicon
The contact doping area 404 of substrate 402 is electrically connected with multiple NAND strings 418.In certain embodiments, selection door 428, which is formed, is waiting
The bottom of level layer stack 414, and by switching the contact doping area 404 of the second silicon substrate 402 come voltage input contact 424 and multiple
Conduction between NAND string 418.In certain embodiments, source contact 424 is made of an electrically conducting material, including but not limited to tungsten, cobalt,
The combination of copper, aluminium, doped silicon, silicide or more material.In certain embodiments, forming source contact 424 can be by using
Dry/wet etching technics extends vertically through the opening of grade layer stack 414 to be formed, then by conductor material or other materials
Such as insulating materials fills the opening.The packing material can use ALD, CVD, PVD and other suitable methods.
In certain embodiments, operation 706 further comprises that to form one or more runs through array contacts.Such as Fig. 4 C institutes
Show, formed through array contacts 431 on the second silicon substrate 402.Extended vertically through array contacts 431 and run through grading layer heap
Stack 414.In certain embodiments, the isolated area 406 of the second silicon substrate 402 is entered through one end of array contacts 431.At some
In embodiment, grading layer can be extended vertically through by using dry/wet etching technics through array contacts 431 to be formed by being formed
The opening of storehouse 414, then by conductor material fills openings.In certain embodiments, other materials such as insulating materials 433
The filling opening is divided to reach isolation purpose.In certain embodiments, conductive material is included through array contacts 431, it is conductive
Material includes but is not limited to the combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or more material.In certain embodiments, use
Conductor material or other materials, which fill the opening, can use ALD, CVD, PVD and/or other suitable methods.
In certain embodiments, operation 706 further comprises forming one or more word line contact points.As shown in Figure 4 C,
Word line contact point 425 is formed on the second silicon substrate 402.Word line contact point 425 extends vertically and runs through insulating barrier 423.One
In a little embodiments, one end of word line contact point 425 is located in the wordline of NAND string.For example, a conductor layer 416 can conduct
One wordline of NAND string.Thus, word line contact point 425 is electrically connected to conductor layer 416.In certain embodiments, each word
Linear contact lay point 425 is connected with a conductor layer 416, and thus, conductor layer 416 is addressable by word line contact point.One
In a little embodiments, word line contact point 425 can be further disposed on silicon substrate 402 or NAND string (for example, selection door 428 and/
Or selection door 430) selection door on.In certain embodiments, word line contact point 425 is formed to etch including the use of dry/wet
Technique is formed by the vertical openings of insulating barrier 423, then by conductor material or other materials, such as it is conductor filled,
Cohesive and/or other purpose barrier materials fill the opening.In certain embodiments, leading through array contact point 425
Body material is made up of conductor material, including but not limited to the combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or more material.
In some embodiments, using conductor material or other materials fill the opening can use ALD, CVD, PVD and/or other
Suitable method.
Exemplary method 700 continues at operation 708, as shown in fig. 7, forming array interconnection layer in multiple NAND strings.Such as figure
Shown in 4D, array interconnection layer 438 is formed in multiple NAND strings 418.Array interconnection layer is used to transmit NAND string and other circuits
Between electric signal.In certain embodiments, forming array interconnection layer 438 includes forming insulating barrier 434, then forms multiple positions
Line contact 432, it is contacted in insulating barrier 434 and with NAND string 418.In certain embodiments, insulating barrier 434 is one layer or more
Layer insulating materials, such as silica, silicon nitride, silicon oxynitride or its combination.In certain embodiments, bit line contact 432
Forming process is：Opening is formed first in insulating barrier 434, then fills the opening using conductor material or insulating materials.
In certain embodiments, the conductor material for manufacturing bit line contact 432 includes but is not limited to tungsten, cobalt, copper, aluminium, doped silicon, silicide
Or more material combination.In certain embodiments, filling the opening using conductor material or other materials can use
ALD, CVD, PVD and/or other suitable methods.
In certain embodiments, form array interconnection layer 438 and further comprise that multiple wordline are formed on insulating barrier 437 leads to
Hole contact 437.In certain embodiments, each wordline through hole contact 437 and the end thereof contacts of word line contact point 425 are with can
It is electrically connected.In certain embodiments, wordline through hole contact 437 is open by being formed in insulating barrier 434, then using leading
Body material is filled to be formed.In certain embodiments, before conductor material is filled, material is for example isolated using other materials
Material is partially filled with the opening to strengthen the viscosity or filling capacity of the conductor material.In certain embodiments, wordline is formed
Through hole contact conductor material include but is not limited to tungsten, cobalt, copper, aluminium, doped silicon, silicide or or more material combination.
In some embodiments, the opening is filled using conductor material and isolated material, can use ALD, CVD, PVD and/or other
Suitable method.
In certain embodiments, array interconnection layer 438 is formed to further comprise forming other conductive layers, such as in insulating barrier
Conductor layer 440 and conductor contact layer 444 in 434.In certain embodiments, there are one or more conductor layers 440 and/or lead
Body contact layer 444.In certain embodiments, manufacture conductor layer 440 and the conductor material of conductor contact layer 444 includes but is not limited to
The combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or more material.Forming the technique of conductor layer and conductor contact layer can adopt
With known back-end process method.
In certain embodiments, array interconnection layer 438 is formed to further comprise forming top conductive layer 442 and top insulation
Layer 436.In certain embodiments, the conductor material for manufacturing top conductive layer 442 includes but is not limited to tungsten, cobalt, copper, aluminium, doping
The combination of silicon, silicide or more material.In certain embodiments, manufacturing the insulating materials of top layer 436 is included but not
It is limited to the combination of silica, silicon nitride, silicon oxynitride or above-mentioned material.
Fig. 5 A-5C are according to the above-mentioned array device of combination of embodiment of the present invention and the step schematic diagram of peripheral components；
Fig. 8 is the flow chart of the exemplary method 800 with reference to above-mentioned array device and peripheral components.
Illustrative methods 800 start from step 802, as shown in figure 8, by the array device turned upside down on the second silicon substrate
So that array interconnection layer is located at below the second silicon substrate, and array interconnection layer and peripheral interconnection layer are alignd.Such as Fig. 5 A institutes
Show, array interconnection layer 438 is placed in the lower section of the second silicon substrate 402.In certain embodiments, aligned array interconnection layer 438 and outer
The method for enclosing interconnection layer 322 is the conductor layer 442 of aligned array interconnection layer 438 and the conductor layer 320 of peripheral interconnection layer 322.Such as
This, when array device and peripheral components combination, conductor layer 442 contacts with 320.
Illustrative methods 800 continue at step 804, as shown in figure 8, associative array interconnection layer and peripheral interconnection layer.Such as figure
Shown in 5B, array interconnection layer 438 and peripheral interconnection layer 322 combine and form bonding interface 503.In certain embodiments, as schemed
Shown in 5A, when before two interconnection layers combine or combining, handling process 502 can be used for strengthening array interconnection layer and periphery interconnects
Adhesion between layer.In certain embodiments, insulating barrier 436 is silicon oxide layer and insulating barrier 318 is silicon nitride layer.At some
In embodiment, insulating barrier 436 is silicon nitride layer and insulating barrier 318 is silicon oxide layer.In certain embodiments, handling process 502
Including plasma-treating technology, the surface of array interconnection layer and the surface of peripheral interconnection layer are handled to strengthen in two insulating barriers
The chemical bond formed between 436 and 318.In certain embodiments, handling process 502 includes wet chemical process technique, place
The surface of array interconnection layer and the surface of peripheral interconnection layer are managed to strengthen the chemistry formed between two insulating barriers 436 and 318
With reference to.
In certain embodiments, handling process 502 is Technology for Heating Processing, is carried out in combined process.In some embodiments
In, the operation temperature of heat treatment is 250 DEG C to 600 DEG C.In certain embodiments, Technology for Heating Processing causes conductor layer 442 and 320
Between produce counterdiffusion.Thus, conductor 442 and 320 is mutually mixed after processing is combined.In certain embodiments, conductor layer 442
All it is made of copper with 320.
Illustrative methods 800 continue at step 806, as shown in figure 8, the second silicon substrate is thinned to form a monocrystalline silicon
Layer.As shown in Figure 5 B, according to an embodiment of the invention, the second silicon substrate 402 is thinned to form monocrystalline silicon layer 504.In some realities
Apply in example, by being thinned, the thickness of monocrystalline silicon layer 504 is between 200nm to 5000nm.In certain embodiments, monocrystalline silicon
The thickness of layer 504 is between 150nm to 50 μm.In certain embodiments, the technique of second silicon substrate 402, which is thinned, to be included
But it is not limited to grinding wafer, dry etching, wet etching, chemically mechanical polishing or the combination of above-mentioned technique.
Illustrative methods 800 continue at step 808, as shown in figure 8, on monocrystalline silicon layer formed back-end process interconnection layer and
Laying.As shown in Figure 5 C, back-end process interconnection layer and laying 512 are formed on monocrystalline silicon layer 504.In certain embodiments,
Back-end process interconnection layer includes one or more insulating barriers 506, one or more contacts 508 and one or more conductor layers 510.
In certain embodiments, insulating barrier 506 is the combination of multiple insulating barriers, and the multiple insulating barrier can pass through independent step system
Make.In certain embodiments, contact 508, conductor layer 510 and laying 512 can be made of an electrically conducting material, and be included but is not limited to
The combination of tungsten, cobalt, copper, aluminium, doped silicon, silicide or more material.In certain embodiments, the insulation of insulating barrier 506 is manufactured
Material includes but is not limited to the combination of silica, silicon nitride, silicon oxynitride or above-mentioned material.In certain embodiments, insulating barrier
506 can further comprise high K insulating materials.In certain embodiments, laying 512 is connected with external circuit with the battle array of combination
Row/electric signal is transmitted between peripheral components and external circuit.
In a word, the present invention is avoided mutual during two device manufactures by the way that the making of array device and peripheral components is separated
Mutually influence the manufacturing process of other side, solve layer behind in the prior art making made by layer above after temperature limiting
Problem, obtain high device density and good peripheral components performance.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (11)
1. a kind of nand memory, including：
Silicon substrate；
One or more peripheral components；
The one or more NAND strings formed above the peripheral components；
The monocrystalline silicon layer formed above one or more of NAND strings, the monocrystalline silicon layer and one or more of NAND
Concatenation touches connection, and
The interconnection layer of one or more first formed between one or more of peripheral components and one or more NAND strings.
2. a kind of nand memory as claimed in claim 1, wherein, each NAND string includes：
Multiple conductor/insulation body laminations；
Extend vertically through the channel semiconductor of the multiple conductor/insulation body lamination；
The tunnel layer formed between the multiple conductor/insulation body lamination and the channel semiconductor；
And the memory cell layers formed between the tunnel layer and multiple conductor/insulation body laminations.
3. a kind of nand memory as claimed in claim 1, further comprise one or more first contacts, wherein, each
First contact extends vertically and had and contacted with the conductor layer of the multiple conductor/insulation body lamination of the NAND string
Upper end, and wherein, each first contact is formed in the lower end of the conductor layer, and connection is contacted with conductor layer.
4. a kind of nand memory as claimed in claim 1, further comprise one or more second contacts, wherein described the
Two contacts pass vertically through the multiple conductor/insulation body lamination, and the upper end of second contact connects with the monocrystalline silicon layer
Touch connection.
5. a kind of nand memory as claimed in claim 1, further comprise being formed the above the multiple NAND string
Two interconnection layers, wherein, second interconnection layer includes conductor layer of one or more formation in one or more insulating barriers.
6. a kind of nand memory as claimed in claim 1, wherein, the multiple NAND string includes being formed in another NAND
A NAND string on string.
7. a kind of nand memory as claimed in claim 6, wherein, the NAND string of the formation in another NAND string
It is connected by forming the conductor part between the NAND string and another NAND string with another NAND string.
8. a kind of method for manufacturing nand memory, including：
One or more peripheral components are formed on the first silicon substrate；
One or more NAND strings are formed on the second silicon substrate；
One or more of NAND strings are placed on above one or more of peripheral components, so that the second silicon substrate
Above one or more of NAND strings；
One or more of NAND strings and one or more of peripheral components are combined together by combining processing；And
Second silicon substrate is thinned to form it into the monocrystalline silicon layer above one or more of NAND strings.
9. method as claimed in claim 8, wherein, forming the NAND string includes：Multiple lead is formed on the second silicon substrate
Body/insulator lamination.
10. method as claimed in claim 8, further comprise forming one or more first contacts, wherein, each described the
One contact extends vertically and has a contact with the conductor layer of the multiple conductor/insulation body lamination of the NAND string
End.
11. method as claimed in claim 8, further comprise being formed one or more above second silicon substrate
First interconnection layer of individual NAND string, to connect the NAND string and one or more of peripheral components.
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|---|---|---|---|
| CN201710716657.1A CN107658315B (en) | 2017-08-21 | 2017-08-21 | Semiconductor device and preparation method thereof |
| JP2020502283A JP7304335B2 (en) | 2017-08-21 | 2018-03-01 | NAND memory device and method for forming NAND memory device |
| EP18849168.2A EP3580782A4 (en) | 2017-08-21 | 2018-03-01 | Three-dimensional memory devices and methods for forming the same |
| PCT/CN2018/077750 WO2019037403A1 (en) | 2017-08-21 | 2018-03-01 | Three-dimensional memory devices and methods for forming the same |
| CN201880005615.XA CN110121779B (en) | 2017-08-21 | 2018-03-01 | Three-dimensional memory device and method for forming the same |
| KR1020197037473A KR102369603B1 (en) | 2017-08-21 | 2018-03-01 | 3D memory device and method for forming the same |
| TW107108765A TWI722275B (en) | 2017-08-21 | 2018-03-15 | Three-dimensional memory devices and methods for forming the same |
| TW110114393A TW202129923A (en) | 2017-08-21 | 2018-03-15 | Three-dimensional memory devices and methods for forming the same |
| US16/047,251 US11211397B2 (en) | 2017-08-21 | 2018-07-27 | Three-dimensional memory devices and methods for forming the same |
| US17/102,625 US11805646B2 (en) | 2017-08-21 | 2020-11-24 | Three-dimensional memory devices and methods for forming the same |
| JP2022141341A JP2022172300A (en) | 2017-08-21 | 2022-09-06 | NAND memory device and method for forming NAND memory device |
| US18/244,688 US20230422504A1 (en) | 2017-08-21 | 2023-09-11 | Three-dimensional memory devices and methods for forming the same |
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