CN107658306B - 一种使用波浪上选择门剪切的3d-nand存储器 - Google Patents

一种使用波浪上选择门剪切的3d-nand存储器 Download PDF

Info

Publication number
CN107658306B
CN107658306B CN201710775885.6A CN201710775885A CN107658306B CN 107658306 B CN107658306 B CN 107658306B CN 201710775885 A CN201710775885 A CN 201710775885A CN 107658306 B CN107658306 B CN 107658306B
Authority
CN
China
Prior art keywords
column
wave
void structure
shearing
nand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710775885.6A
Other languages
English (en)
Other versions
CN107658306A (zh
Inventor
陶谦
胡禺石
吕震宇
陈俊
戴晓望
肖莉红
朱继锋
姚兰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN201710775885.6A priority Critical patent/CN107658306B/zh
Publication of CN107658306A publication Critical patent/CN107658306A/zh
Application granted granted Critical
Publication of CN107658306B publication Critical patent/CN107658306B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

一种使用波浪上选择门剪切的3D‑NAND存储器,所述3D‑NAND存储器的通道空穴结构为九孔空穴阵列,所述波浪上选择门剪切有两条,分别分布在所述阵列的第三列和第四列之间、第六列和第七列之间。所述波浪上选择门剪切呈波浪形,分布在空穴之间。所述3D‑NAND存储器通道空穴结构的线位距离为52nm。本发明的优点是降低了成本,由于线位距离增大而提高了制造的便利性和可行性。

Description

一种使用波浪上选择门剪切的3D-NAND存储器
技术领域
本发明涉及一种使用波浪上选择门剪切的NAND存储器通道空穴结构,属于3DNAND存储器制造领域。
背景技术
如图1所示,目前3D NAND存储器的通道空穴结构为9单元结构,其中线宽(BL)为22nm,间距为17nm,所以线位距离(BL total pitch)为39nm。在这种结构中,为了进行上选择门剪切步骤(TSG cut,top selective gate cut),中间的第五列单元在剪切的过程中由于位于剪切的路径上,被直接破坏而无法使用,只留下其余8列单元可以有效使用。
如此,由于有一列单元被浪费掉,最终增加了整个存储器制造的成本。
再者,现有技术的3D NAND存储器,存在着需要通过多次光照来实现极小线位及其可控性的难题。
发明内容
本发明的目的是通过以下技术方案实现的。
本发明的目的是获得高器件密度(提高约11%)和降低成本(降低约10%),将线宽/间距由22/17扩展到26/26(线位距离由39-43nm提高到52-55nm),从而显著提高了边缘区使用率;根据不同的产品应用设计更长和更扁的平面/晶粒布局。
具体的,根据本发明的一个方面,提供了一种使用波浪上选择门剪切的3D-NAND存储器通道空穴结构,所述3D-NAND存储器的通道空穴结构为九孔空穴阵列,所述波浪上选择门剪切有两条,分别分布在所述阵列的第三列和第四列之间、第六列和第七列之间。
优选的,所述3D-NAND存储器通道空穴结构的线位距离为52-55nm。
具体的,根据本发明的另一个方面,还提供了一种如上所述的3D-NAND存储器通道空穴结构的制备方法,所述方法包括如下步骤:
形成九孔空穴阵列;
在所述九孔空穴阵列的第三列和第四列之间、在第六列和第七列之间形成上选择门剪切,从而沿着所述上选择门剪切将通道空穴结构分隔为三个部分。
本发明的优点是降低了成本,由于线位距离增大而提高了制造的便利性和可行性。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考符号表示相同的部件。在附图中:
附图1是现有技术中TSG剪切方法示意图。
附图2是本发明使用波浪上选择门剪切的NAND存储器通道空穴结构示意图。
附图3是形成本本发明使用波浪上选择门剪切的NAND存储器通道空穴结构的方法步骤一示意图。
附图4是形成本本发明使用波浪上选择门剪切的NAND存储器通道空穴结构的方法步骤二示意图。
附图5是现有技术和本发明使用波浪上选择门剪切的NAND存储器通道空穴结构的区块单元大小对比示意图。
附图6是现有技术和本发明使用波浪上选择门剪切的NAND存储器通道空穴结构的整体区块大小对比示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
如图2所示,为本发明使用波浪上选择门剪切NAND存储器通道空穴结构的原理示意图。其中,在第三列和第四列之间、在第六列和第七列之间,分别使用了两个波浪形上选择门剪切路径,将9单元结构分割为3个不同的子区域。如此,由于上选择门剪切形成过程中没有任何的单元结构的损失,提高了最后生成的器件密度(提高11%左右),并降低了成本(降低10%左右)。
图3、图4为本发明为本发明使用波浪上选择门剪切NAND存储器通道空穴结构的方法示意图。如图3所示,第一步,首先形成九孔空穴阵列。如图4所示,第二步,在第三列和第四列之间、在第六列和第七列之间形成波浪形上选择门剪切,其沿着所述波浪形上选择门剪切将通道空穴结构分隔为三个部分。
图5为本发明和现有技术中区块大小的比较。例如,本发明采用线宽(BL)为26nm,间距为26nm,所以线位距离(BL total pitch)为52nm(本发明的线位距离不限于52nm,可以在52-55nm之间)。因此总的NAND串长度为16*210*8*52nm=6.82mm。相比之下,现有技术的NAND串长度为16*210*8*39nm=5.11mm。因此,如图6所示,由原来的二分区,变为三分区可以让线位距离也得到了放大,每一根BL要连接一个分区的空穴单元,所以线位距离会由原来的156nm/4变成156nm/3(156nm是空穴单元的中心距离),由于线位距离增大而提高了制造的便利性和可行性,并且显著提高了边缘区使用率。
器件密度是由最终的空穴数目决定的,所以相同的空穴数目会增加1/9的实际密度(大约10%的成本节约),但作为NAND产品模块,要求区块的X方向有16000根线位,所以本发明区块的X方向要变长大约1/3,因为线位的间距变大1/3,从而Y方向可以减小1/3来保持相同的面积或者1.1倍的空穴密度(和现有技术模块相比较)。
以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。

Claims (3)

1.一种使用波浪上选择门剪切的3D-NAND存储器通道空穴结构,其特征在于:
所述3D-NAND存储器通道空穴结构为九孔空穴阵列,所述波浪上选择门剪切有两条,分别分布在所述阵列的第三列和第四列之间、第六列和第七列之间。
2.根据权利要求1所述的3D-NAND存储器通道空穴结构,其特征在于:
所述3D-NAND存储器通道空穴结构的线位距离为52-55nm。
3.一种根据权利要求1或2所述的3D-NAND存储器通道空穴结构的制备方法,其特征在于所述方法包括如下步骤:
形成九孔空穴阵列;
在所述九孔空穴阵列的第三列和第四列之间、在第六列和第七列之间形成上选择门剪切,从而沿着所述上选择门剪切将通道空穴结构分隔为三个部分。
CN201710775885.6A 2017-08-31 2017-08-31 一种使用波浪上选择门剪切的3d-nand存储器 Active CN107658306B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710775885.6A CN107658306B (zh) 2017-08-31 2017-08-31 一种使用波浪上选择门剪切的3d-nand存储器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710775885.6A CN107658306B (zh) 2017-08-31 2017-08-31 一种使用波浪上选择门剪切的3d-nand存储器

Publications (2)

Publication Number Publication Date
CN107658306A CN107658306A (zh) 2018-02-02
CN107658306B true CN107658306B (zh) 2019-11-26

Family

ID=61128149

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710775885.6A Active CN107658306B (zh) 2017-08-31 2017-08-31 一种使用波浪上选择门剪切的3d-nand存储器

Country Status (1)

Country Link
CN (1) CN107658306B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817627A (zh) * 2019-01-31 2019-05-28 长江存储科技有限责任公司 一种形成三维存储器的方法及三维存储器
WO2020172798A1 (en) 2019-02-26 2020-09-03 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory device and method for forming the same
US11362142B2 (en) 2020-05-18 2022-06-14 Micron Technology, Inc. Electronic apparatus with tiered stacks having conductive structures isolated by trenches, and related electronic systems and methods
US11631615B2 (en) 2020-05-18 2023-04-18 Micron Technology, Inc. Microelectronic devices including contact structures with enlarged areas, and related electronic systems and methods
US11527546B2 (en) 2020-07-30 2022-12-13 Micron Technology, Inc. Microelectronic devices including conductive structures, and related memory devices, electronic systems, and methods

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106992180A (zh) * 2016-01-21 2017-07-28 爱思开海力士有限公司 半导体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101812260B1 (ko) * 2010-10-20 2017-12-28 삼성전자주식회사 3차원 반도체 기억 소자 및 그 제조 방법
US9711522B2 (en) * 2014-10-03 2017-07-18 Sandisk Technologies Llc Memory hole structure in three dimensional memory
US20160240547A1 (en) * 2015-02-18 2016-08-18 Kabushiki Kaisha Toshiba Semiconductor memory device
US10074665B2 (en) * 2015-09-11 2018-09-11 Toshiba Memory Corporation Three-dimensional semiconductor memory device including slit with lateral surfaces having periodicity
US9754888B2 (en) * 2015-12-14 2017-09-05 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing the same
US9859363B2 (en) * 2016-02-16 2018-01-02 Sandisk Technologies Llc Self-aligned isolation dielectric structures for a three-dimensional memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106992180A (zh) * 2016-01-21 2017-07-28 爱思开海力士有限公司 半导体装置

Also Published As

Publication number Publication date
CN107658306A (zh) 2018-02-02

Similar Documents

Publication Publication Date Title
CN107658306B (zh) 一种使用波浪上选择门剪切的3d-nand存储器
JP7252257B2 (ja) クロスポイントメモリアレイおよび関連する製造技法
TWI268604B (en) Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
CN107658311B (zh) 三维存储器
DE102016113828B4 (de) Halbleitervorrichtung
KR101022250B1 (ko) 멀티게이트 전계 효과 트랜지스터 어레이 레이아웃
DE102011054829A1 (de) Nichtflüchtige Speichervorrichtung, welche widerstandsveränderlicheElemente hat, und verwandte Systeme und Verfahren
EP0920059A3 (de) Speicherzellenanordnung und Verfahren zu deren Herstellung
WO2004061851A3 (en) An improved method for making high-density nonvolatile memory
JP7138722B2 (ja) クロスポイントメモリアレイおよび関連する製造技法
DE102011112904A1 (de) Lichtemittierende Vorrichtungsstruktur und Verfahren zur Herstellung derselben
CN107705710A (zh) 显示装置及其显示基板
KR101471857B1 (ko) 반도체 장치 및 상기 반도체 장치의 레이아웃 방법
CN103699648A (zh) 用于快速检索的树形数据结构及其实现方法
US5399517A (en) Method of routing three layer metal gate arrays using a channel router
DE102006025956B3 (de) Nicht-flüchtiges Speicherzellenfeld
CN104898570B (zh) 一种基于边界延拓的腹板加工单元自动构造方法
DE102018129873A1 (de) Mikroelektronikgehäuse mit einem integrierten Wärmeverteiler
US11264409B2 (en) Array base plate and manufacturing methodthereof, as well as display panel comprising the same
CN106033791B (zh) 一种存储器元件
CN104134670B (zh) 可伸缩分裂栅存储器单元阵列
US20130285190A1 (en) Layout of a MOS Array Edge with Density Gradient Smoothing
TW200629479A (en) Semiconductor device having step gates and method for fabricating the same
Lee et al. Paleobiologic features of Trabeculites maculatus (Tabulata, Late Ordovician, southern Manitoba)
US20230013579A1 (en) Layout structure forming method of sense amplifier and layout structure of sense amplifier

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant