CN107623507A - Digital filter - Google Patents
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- CN107623507A CN107623507A CN201610559802.5A CN201610559802A CN107623507A CN 107623507 A CN107623507 A CN 107623507A CN 201610559802 A CN201610559802 A CN 201610559802A CN 107623507 A CN107623507 A CN 107623507A
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Abstract
A kind of digital filter, the element number N that the collection of filter coefficient corresponding to the digital filter is combined into set A, the set A meet N=2n× m, and for any i, preceding 2 in set An‑iThe set of × m element and adjacent 2n‑iWhen the set of × m element is in proportionate relationship, the digital filter includes：The filter unit of n+1 series connection, wherein：In n filter unit, i-th of filter unit includes 2i‑1× m delay cell, 1 adder and 1 multiplier；A remaining filter unit includes 1 delay cell of m, 1 adder of m and m multiplier；1≤i≤n, m, n are integer, and m ＞ 1.Such scheme can simplify the structure of digital filter, reduce signed magnitude arithmetic(al) number, reduce logical resource consumption.
Description
Technical field
The present invention relates to field of digital signals, more particularly to a kind of digital filter.
Background technology
A kind of algorithm or device that digital filter is made up of digital multiplier, adder and delay unit.Numeral filter
The function of ripple device is to carry out calculation process to inputting the data signal of discrete signal, to reach the purpose for changing frequency spectrum.
In the prior art, for there is limit for length's impact response filter (Finite Impulse Response, FIR), its
Expression formula isWherein, YnFor the output of digital filter, xiFor the input of digital filter, aiFiltered for numeral
The coefficient of ripple device, corresponding ssystem transfer function are
Reference picture 1, a kind of circuit structure diagram of existing general digital filter is given, wherein, Z-1Represent delay
One clock cycle, a trigger is expressed as on circuit realiration.When sampled point corresponding to the coefficient of digital filter is n
When, need to be provided with n-1 trigger, n multiplier and n-1 plus/minus musical instruments used in a Buddhist or Taoist mass in digital filter.When sampling number n compared with
When big, the structure of digital filter is complex, and required signed magnitude arithmetic(al) number is more, and logical resource consumption is larger.
The content of the invention
Present invention solves the technical problem that being how to simplify the structure of digital filter, signed magnitude arithmetic(al) number, drop are reduced
Low logic resource consumption.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of digital filter, the digital filter is corresponding
The collection of filter coefficient be combined into element number N in set A, the set A, meet N=2n× m, and for any i, collection
Close preceding 2 in An-iThe set of × m element and adjacent 2n-iWhen the set of × m element is in proportionate relationship, the numeral
Wave filter includes：The filter unit of n+1 series connection, wherein：In n filter unit, i-th of filter unit includes 2i-1× m
Delay cell, 1 adder and 1 multiplier, a remaining filter unit include m-1 delay cell, m-1 and added
Musical instruments used in a Buddhist or Taoist mass and m multiplier；1≤i≤n, m, n are integer, and m ＞ 1.
Optionally, according to the number of delay cell in the filter unit of n+1 series connection, the filtering to described n+1 series connection
Unit is ranked up.
Optionally, in the filter unit of the n+1 series connection, after the delay cell number in previous stage filter unit is less than
Delay cell number in one-level filter unit, wherein：J-th stage filter unit includes 2j-2× m delay cell, 1 addition
Device and 1 multiplier, wherein：Adder in the j-th stage filter unit, first input end and -1 grade of filter unit of jth
In adder output end coupling, the first input end of the adder in output end and+1 grade of filter unit of jth couples；It is described
Multiplier in j-th stage filter unit, first input end and described 2j-2Afterbody delay cell in × m delay cell
Output end coupling, the second input input constant kj, the second of output end and the adder in the j-th stage filter unit be defeated
Enter end coupling；In the j-th stage filter unit, input and the addition in -1 grade of filter unit of jth of first order delay cell
The output end coupling of device；1st grade of filter unit includes m-1 delay cell, m-1 adder and m multiplier；Its
In, j is integer and 2≤j≤n+1.
Optionally, in the filter unit of the n+1 series connection, after the delay cell number in previous stage filter unit is more than
Delay cell number in one-level filter unit, wherein：As j≤n, j-th stage filter unit includes 2n-j× m delay is single
Member, 1 adder and 1 multiplier, wherein：Adder in the j-th stage filter unit, first input end and jth -1
The output end coupling of adder in level filter unit, the first input of output end and the adder in+1 grade of filter unit of jth
End coupling；Multiplier in the j-th stage filter unit, first input end and described 2n-jLast in × m delay cell
The output end coupling of level delay cell, the second input input constant kj, the addition in output end and the j-th stage filter unit
The second input coupling of device；In the j-th stage filter unit, -1 grade of filtering of input and jth of first order delay cell is single
The output end coupling of adder in member；As j=n+1, j-th stage filter unit includes m-1 delay cell, m-1 and added
Musical instruments used in a Buddhist or Taoist mass and m multiplier；Wherein, j is integer and 1≤j≤n+1.
Optionally, the digital filter also includes：Y selecting unit, wherein：In y level filter units, including 2n-y
Individual delay cell, 1 multiplier and 1 adder, wherein：Multiplier in the y level filter units, first input end
With described 2n-yThe output end coupling of the delay cell of afterbody in individual delay cell, the second input input constant ky, output
End and the second input of the adder in the y level filter units couple；Adder in the y level filter units,
The output end of first input end and y-1 level selecting units couples, the first input end coupling of output end and y level selecting units
Connect；2 in the y level filter unitsn-yThe series connection of individual delay cell, and the input of first order delay cell therein and the
The output end coupling of y-1 level selecting units；1≤y≤Y, 1≤Y≤n；Y level selecting units, the input of the second input are to be filtered
Signal；The input of output end and the level delay cell in y+1 level filter units couples；Control terminal inputs control signal, from
Conduct all the way is selected in the signal of the first input end input of the y level selecting units and the signal of the second input input
Output.
Optionally, the selecting unit is MUX.
Optionally, the digital filter includes：Multiple output ports, the output port include：The n+1 filtering
The output port of multiple filter units in unit.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
When filter coefficient exponent number N corresponding to digital filter meets 2n× m, and for any i, preceding 2 in set An-i
The set of × m element and adjacent 2n-iWhen the set of × m element is in proportionate relationship, digital filter can be divided into n
The filter unit of+1 series connection, n+1 filter unit need N-1 delay cells, m+n-1 adder and m+n-1 to multiply altogether
Musical instruments used in a Buddhist or Taoist mass.Compared in the prior art, it is necessary to N-1 delay cell, N-1 adder and N when filter coefficient exponent number is N
Individual multiplier, such scheme can effectively reduce adder and the quantity of multiplier, therefore can simplify digital filter
Structure, signed magnitude arithmetic(al) number is reduced, reduce logical resource consumption.
Further, multiple output ports are set in digital filter, digital filter can be produced simultaneously
The output of the wave filter of a variety of different coefficients.
Further, it is according to the difference of delay cell number, the filter unit that n levels are connected is more according to the number of delay cell
It is configured less, the number of delay cell is more than or equal to of delay cell in rear stage filter unit in previous stage filter unit
Number so that bit bit wide data corresponding to the delay cell of maximum number are reduced, so as to save resource.
In addition, adding selecting unit in digital filter, can be selected in the output of the wave filter of a variety of different coefficients
Select all the way as output, neatly digital filter can be selected to export.
Brief description of the drawings
Fig. 1 is a kind of structural representation of existing digital filter；
Fig. 2 is a kind of structural representation of digital filter in the embodiment of the present invention；
Fig. 3 is a kind of structural representation of first filter unit in one embodiment of the invention；
Fig. 4 is the structural representation of another digital filter in the embodiment of the present invention；
Fig. 5 is the structural representation of another digital filter in the embodiment of the present invention；
Fig. 6 is a kind of structural representation of digital filter in the embodiment of the present invention.
Embodiment
In some application scenarios, the coefficient of wave filter may be more special.For example, in smart card communications field, card
The signal that piece is sent to card machine uses frequency to be first modulated to for 848KHz square wave as subcarrier, baseband signal on subcarrier,
Then on the radio-frequency carrier that re-modulation is 13.56MHz to frequency.During the reception signal of card machine, generally first removed in AFE(analog front end)
Radio-frequency carrier, then sampled by ADC, be demodulated using digital circuit.Now, digital demodulation generally use matched filtering
Method, subcarrier is detected in reception signal.Wherein, matched filter can be as needed, selects N number of subcarrier as filtering
Device coefficient.
For example, corresponding 16 sampled points [1 11 1-1-1-1-1 111 1-1-1 of the coefficient of matched filter
- 1-1], wherein, subcarrier high level corresponds to 1 in sampled point, and subcarrier low level corresponds to-1 in sampled point, corresponding
Expression formula Y (n) with wave filter sees below formula (1)：
Y (n)=X (n)+X (n-1)+X (n-2)+X (n-3)-X (n-4)-X (n-5)-X (n-6)-X (n-7)+X (n-8)+X
(n-9)+X(n-10)+X(n-11)-X(n-12)-X(n-13)-X(n-14)-X(n-15)； (1)
Corresponding, the ssystem transfer function H (z) of matched filter is such as shown in following formula (2)：
H (z)=z0+z-1+z-2+z-3-z-4-z-5-z-6-z-7+z-8+z-9+z-10+z-11-z-12-z-13-z-14-z-15； (2)
In the prior art, for formula (2) shown in transmission function, shown in the structure reference picture 1 of corresponding matched filter,
Wherein, Z-1One clock cycle of delay is represented, a trigger, a are expressed as on circuit realiration0、a1、a2、……、anFor filter
The coefficient of ripple device, corresponded respectively with multiplier.Matched filter needs to use 15 triggers, 16 multipliers and 15
Individual plus/minus musical instruments used in a Buddhist or Taoist mass.When the coefficient of FIR filter is bigger, its structure is with regard to increasingly complex, and required signed magnitude arithmetic(al) number is more
More, logical resource consumption is bigger.
In embodiments of the present invention, when filter coefficient exponent number N corresponding to digital filter meets 2n× m, and for appointing
Anticipate i, and preceding 2 in set An-iThe set of × m element and adjacent 2n-i, can when the set of × m element is in proportionate relationship
So that digital filter to be divided into the filter unit of n+1 series connection, n+1 filter unit needs N-1 delay cells, m+n-1 altogether
Adder and m+n-1 multiplier.Compared in the prior art, it is necessary to which N-1 delay is single when filter coefficient exponent number is N
Member, N-1 adder and N number of multiplier, such scheme can effectively reduce adder and the quantity of multiplier, therefore energy
Enough simplify the structure of digital filter, reduce signed magnitude arithmetic(al) number, reduce logical resource consumption.
It is understandable to enable above-mentioned purpose, feature and the beneficial effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
The embodiments of the invention provide a kind of digital filter, wherein, filter coefficient corresponding to digital filter needs
Meet following condition：The collection of filter coefficient is combined into set A, and the element number N in set A meets N=2n× m, and for appointing
Anticipate i, and preceding 2 in set An-iThe set of × m element and adjacent 2n-iThe set of × m element is in proportionate relationship, wherein,
1≤i≤n, m, n are integer, and m ＞ 1.
When the coefficient of digital filter meets above-mentioned condition, in embodiments of the present invention, digital filter can include n
+ 1 filter unit.In n+1 filter unit, one of filter unit includes m-1 delay cell, m-1 and added
Musical instruments used in a Buddhist or Taoist mass and m multiplier；In remaining n filter unit, i-th of filter unit includes 2i-1× m delay cell, 1 plus
Musical instruments used in a Buddhist or Taoist mass and 1 multiplier.
The digital filter provided in the above embodiment of the present invention is illustrated below.
For example, the collection of filter coefficient corresponding to digital filter is combined into A, set A includes N number of element, and N is even number,
And the collection of the preceding N/2 element in set A is combined into A1, the collection of the N/2 element adjacent with set A1 is combined into A2 in set A.It is right
In constant k, there is A1=k × A2.Correspondingly, transmission function A1 (Z) transmission function A2s corresponding with set A2 corresponding to set A1
(Z) following relation is met：A1 (Z)=k × A2 (Z), namely A2 (Z)=1/k × A1 (Z).
Now, the transfer function H (z) of digital filter can be reduced to following formula (3)：
H (z)=A (z)=A1 (z)+A2 (z) × Z-(N/2)
=A1 (z)+1/k × A1 (z) × Z-(N/2)=A1 (z) × (1+1/k × Z-(N/2)) (3)
Reference picture 2, give a kind of structural representation of digital filter in the embodiment of the present invention, the digital filtering
Device is corresponding with the transmission function corresponding to formula (3), in Fig. 2, Z-N/2It is expressed as the delay cell of N/2 series connection.
In fig. 2, the collection of filter coefficient is combined into set A1, corresponding transmission function corresponding to the first filter unit 201
For the A1 (Z) in formula (3)；The collection of filter coefficient is combined into set A2, corresponding transmission function corresponding to second filter unit 202
For 1+1/k × Z in formula (3)-(N/2)。
The input of first filter unit 201 inputs signal X to be filteredn, the addition of output end and the second filter unit 202
The first input end coupling of device；In the second filter unit 202, in the delay cell of N/2 series connection, first order delay cell
The output end of input and the first filter unit 201 couples, the output end of afterbody delay cell and the second filter unit 202
In multiplier first input end coupling；Multiplier in second filter unit 202, the second input input constant 1/k are defeated
Go out end and the second input of the adder in the second filter unit 202 couples；Adder in second filter unit 202 it is defeated
Go out end output filter result Yn。
From Fig. 2 it is known that in the second filter unit 202, including N/2 delay cell, 1 multiplier and 1
Individual adder.And in the prior art, the second filter unit 202 includes N/2 delay cell, N/2 multiplier and N/2
Individual adder.The digital filter provided in the embodiment of the present invention, N/2-1 multiplier and N/2-1 addition can be saved
Device.
As can be seen here, compared in the prior art, it is necessary to N-1 delay cell, N-1 when filter coefficient exponent number is N
Adder and N number of multiplier, the scheme provided in the embodiment of the present invention can effectively reduce the number of adder and multiplier
Amount, therefore the structure of digital filter can be simplified, signed magnitude arithmetic(al) number is reduced, reduces logical resource consumption.
In embodiments of the present invention, the structure of the first filter unit 201 can be similar with the structure shown in Fig. 1.
Reference picture 3, give a kind of structural representation of first filter unit in one embodiment of the invention.In Fig. 3, the
Set A1={ a of filter coefficient corresponding to one filter unit0, a1, a2, a3, therefore, corresponding delay cell number is 3,
Adder number is 3, and multiplier number is 4.
In the first filter unit：
Delay cell 301, input input signal X to be filteredn, the input coupling of output end and delay cell 302；Multiply
Musical instruments used in a Buddhist or Taoist mass 304, the first input end of output end and adder 308 couple, and first input end inputs signal X to be filteredn, the second input
The 1st filter coefficient in end input set A1, namely the coefficient of input is a0；Multiplier 305, first input end and delay
The output end coupling of unit 301, the 2nd filter coefficient that the second input is inputted in set A1, namely the coefficient of input are
a1；Adder 308, the output end of the second input and multiplier 305 couple, the first input end of output end and adder 309
Coupling；Delay cell 302, the input of output end and delay cell 303 couple；Multiplier 306, first input end are single with delay
The output end coupling of member 302, the 3rd filter coefficient that the second input is inputted in set A1, namely the coefficient of input is a2,
Second input of output end and adder 309 couples；Adder 309, the first input end coupling of output end and adder 310
Connect；Delay cell 303, output end and the first input end of multiplier 307 couple；Multiplier 307, the input set of the second input
The 4th filter coefficient in A1, namely the coefficient of input is a3, the second input coupling of output end and adder 310.
In embodiments of the present invention, n+1 filter unit put in order can be any setting or according to
The number of the delay cell each included is ranked up.
, can be with when n+1 filter unit is when putting in order according to the number of the delay cell each included to sort
Using the minimum filter unit of the number comprising delay cell as the 1st grade of filter unit, in subsequent every one-level filter unit
The number of delay cell is all higher than the delay cell number in previous stage filter unit, and (n+1)th grade of filter unit is afterbody
Filter unit.Now, the 1st grade of filter unit includes m-1 delay cell, m-1 adder and m multiplier, and (n+1)th
Level filter unit includes 2n-1× m delay cell, 1 adder and 1 multiplier.
When in the filter unit of n+1 series connection, the delay cell number in previous stage filter unit filters less than rear stage
During delay cell number in unit, in the filter unit of n+1 series connection：
Corresponding to j-th stage filter unit, including 2j-2× m delay cell, 1 adder and 1 multiplier, wherein：
Adder in j-th stage filter unit, first input end and the output end of the adder in -1 grade of filter unit of jth
Coupling, the first input end of output end and the adder in+1 grade of filter unit of jth couple；
Multiplier in j-th stage filter unit, first input end and 2j-2Afterbody delay in × m delay cell
The output end coupling of unit, the second input input constant kj, the of adder in output end and the j-th stage filter unit
Two inputs couple；
In j-th stage filter unit, adder in -1 grade of filter unit of input and jth of first order delay cell it is defeated
Go out end coupling；
1st grade of filter unit includes m-1 delay cell, m-1 adder and m multiplier；
Wherein, j is integer and 2≤j≤n+1.
Reference picture 4, give a kind of structural representation of digital filter in the embodiment of the present invention.Number corresponding to Fig. 4
Element number in the filter coefficient set A of word wave filter is 32, and the set A1 of preceding 16 elements composition in set A and
The set A2 of adjacent 16 elements composition meets A1=k5×A2；The set B1 and phase of preceding 8 elements composition in set A1
The set B2 of adjacent 8 elements composition meets B1=k4×B2；The set C1 and adjacent of preceding 4 elements composition in set B1
The set C2 of 4 element compositions meets C1=k3×C2；The set D1 of preceding 2 elements composition in set C1 and adjacent 2
The set D2 of element composition meets D1=k2×D2；The set E1 and 1 adjacent element of preceding 1 element composition in set D1
The set E2 of composition meets E1=k1×E2。
Therefore, digital filter includes (4+1)=5 filter unit, is followed successively by：1st grade of filter unit 401, the 2nd grade of filter
Ripple unit 402,3rd level filter unit 403, the 4th grade of filter unit 404 and the 5th grade of filter unit 405, wherein, m=2, this
When：
In 1st grade of filter unit 401, including 1 delay cell, 1 adder and 2 multipliers, wherein：1st grade
Delay cell in filter unit 401, input input signal X to be filteredn, output end and multiplying in the 1st grade of filter unit 401
The first input end coupling of musical instruments used in a Buddhist or Taoist mass 4012；Multiplier 4011, first input end input signal X to be filteredn, output end with the 1st grade
The first input end of adder in filter unit 401 couples, the 1st member in the second input input filter coefficient sets
Plain k0；Multiplier 4012, in the second input input filter coefficient sets, the ratio k of the 1st element and the 2nd element1, it is defeated
Go out end and the first input end of the adder in the 1st grade of filter unit 401 couples；Adder in 1st grade of filter unit 401,
The first input end of output end and the adder in the 2nd grade of filter unit 402 couples；
In 2nd grade of filter unit 402, including 22-2× 2=2 delay cell, 1 adder and 1 multiplier, its
In：The output end of adder in 2nd grade of filter unit 402, first input end and the adder in the 1st grade of filter unit 401
Coupling, the first input end of output end and the adder in 3rd level filter unit 403 couple；In 2nd grade of filter unit 402
The output end coupling of afterbody delay cell, the input of the second input are normal in multiplier, first input end and 2 delay cells
Number k2, the second input coupling of output end and the adder in the 2nd grade of filter unit 402；In 2nd grade of filter unit 402, the
The output end of the input of one-level delay cell and the adder in the 1st grade of filter unit 401 couples；
In 3rd level filter unit 403, including 23-2× 2=4 delay cell, 1 adder and 1 multiplier, its
In：The output end of adder in 3rd level filter unit 403, first input end and the adder in the 2nd grade of filter unit 402
Coupling, the first input end of output end and the adder in the 4th grade of filter unit 404 couple；In 3rd level filter unit 403
The output end coupling of afterbody delay cell, the input of the second input are normal in multiplier, first input end and 4 delay cells
Number k3, the second input coupling of output end and the adder in 3rd level filter unit 403；In 3rd level filter unit 403, the
The output end of the input of one-level delay cell and the adder in the 2nd grade of filter unit 402 couples；
In 4th grade of filter unit 404, including 24-2× 2=8 delay cell, 1 adder and 1 multiplier, its
In：Adder in 4th grade of filter unit 404, first input end and the output end of the adder in 3rd level filter unit 403
Coupling, the first input end of output end and the adder in the 5th grade of filter unit 405 couple；In 4th grade of filter unit 404
The output end coupling of afterbody delay cell, the input of the second input are normal in multiplier, first input end and 8 delay cells
Number k4, the second input coupling of output end and the adder in the 4th grade of filter unit 404；In 4th grade of filter unit 404, the
The input of one-level delay cell and the output end of the adder in 3rd level filter unit 403 couple；
In 5th grade of filter unit 405, including 25-2× 2=16 delay cell, 1 adder and 1 multiplier, its
In：The output end of adder in 5th grade of filter unit 405, first input end and the adder in the 4th grade of filter unit 404
Coupling, output end output filter result Yn；Multiplier in 5th grade of filter unit 405, first input end and 16 delay cells
The output end coupling of middle afterbody delay cell, the second input input constant k5, output end and the 5th grade of filter unit 405
In adder the second input coupling；In 5th grade of filter unit 405, the input of first order delay cell and the 4th grade of filter
The output end coupling of adder in ripple unit 404.
In Fig. 4, Z-1It is expressed as 1 delay cell, Z-2It is expressed as the delay cell of 2 series connection, Z-4It is expressed as 4 series connection
Delay cell, by that analogy, Z-16It is expressed as the delay cell of 16 series connection.
It is understood that can also be single as the 1st grade of filtering using the largest number of filter units comprising delay cell
Member, the number of the delay cell in subsequent every one-level filter unit are respectively less than the individual of the delay cell in previous stage filter unit
Number, (n+1)th grade of filter unit is as afterbody filter unit.Now, it is single to include m-1 delay for (n+1)th grade of filter unit
Member, m-1 adder and m multiplier, the 1st grade of filter unit include 2n-1× m delay cell, 1 adder and
1 multiplier.
When in the filter unit of n+1 series connection, the delay cell number in previous stage filter unit filters more than rear stage
During delay cell number in unit, in the filter unit of n+1 series connection：
Corresponding to j-th stage filter unit, as j≤n, j-th stage filter unit includes 2n-j× m delay cell, 1
Adder and 1 multiplier, wherein：
Adder in j-th stage filter unit, first input end and the output end of the adder in -1 grade of filter unit of jth
Coupling, the first input end of output end and the adder in+1 grade of filter unit of jth couple；
Multiplier in j-th stage filter unit, first input end and described 2n-jAfterbody in × m delay cell
The output end coupling of delay cell, the second input input constant kj, the adder in output end and the j-th stage filter unit
The second input coupling；
In j-th stage filter unit, adder in -1 grade of filter unit of input and jth of first order delay cell it is defeated
Go out end coupling；
As j=n+1, j-th stage filter unit includes m-1 delay cell, m-1 adder and m multiplier；
Wherein, j is integer and 1≤j≤n+1.
Reference picture 5, gives a kind of structural representation of digital filter in one embodiment of the invention, the number in Fig. 5
The filter coefficient of word wave filter is identical with the filter coefficient of the digital filter in Fig. 4.In Fig. 5, the 1st grade of filter unit
501 include the delay cell of 16 series connection, and the 2nd grade of filter unit 502 includes the delay cell of 8 series connection, 3rd level filtering
Unit 503 include 4 series connection delay cells, the 4th grade of filter unit 504 include 2 connect delay cells, the 5th grade
Filter unit 505 includes 1 delay cell.
In 1st grade of filter unit 501, including 24-1× 2=16 delay cell, 1 adder and 1 multiplier, its
In：Adder in 1st grade of filter unit 501, first input end input signal X to be filteredn, output end and the 2nd grade of filtering are single
The first input end coupling of adder in member 502；Multiplier in 1st grade of filter unit 501, first input end prolong with 16
The output end coupling of afterbody delay cell in slow unit, the second input input constant k5, output end with the 1st grade filtering
The second input coupling of adder in unit 501；16 delay cells in 1st grade of filter unit 501 are cascaded,
And the input of first order delay cell therein inputs signal X to be filteredn；
In 2nd grade of filter unit 502, including 24-2× 2=8 delay cell, 1 adder and 1 multiplier, its
In：The output end of adder in 2nd grade of filter unit 502, first input end and the adder in the 1st grade of filter unit 501
Coupling, the first input end of output end and the adder in 3rd level filter unit 503 couple；In 2nd grade of filter unit 502
The output end coupling of multiplier, first input end and the afterbody delay cell in 8 delay cells, the input of the second input
Constant k4, the second input coupling of output end and the adder in the 2nd grade of filter unit 502；In 2nd grade of filter unit 502
8 delay cells be cascaded, and in the input of first order delay cell therein and the 1st grade of filter unit 501
The output end coupling of adder；
In 3rd level filter unit 503, including 24-3× 2=4 delay cell, 1 adder and 1 multiplier, its
In：The output end of adder in 3rd level filter unit 503, first input end and the adder in the 2nd grade of filter unit 502
Coupling, the first input end of output end and the adder in the 4th grade of filter unit 504 couple；In 3rd level filter unit 503
The output end coupling of multiplier, first input end and the afterbody delay cell in 4 delay cells, the input of the second input
Constant k3, the second input coupling of output end and the adder in 3rd level filter unit 503；In 3rd level filter unit 503
4 delay cells be cascaded, and in the input of first order delay cell therein and the 2nd grade of filter unit 502
The output end coupling of adder；
In 4th grade of filter unit 504, including 24-4× 2=2 delay cell, 1 adder and 1 multiplier, its
In：Adder in 4th grade of filter unit 504, first input end and the output end of the adder in 3rd level filter unit 503
Coupling, the first input end of output end and the adder in the 5th grade of filter unit 505 couple；In 4th grade of filter unit 504
The output end coupling of multiplier, first input end and the afterbody delay cell in 2 delay cells, the input of the second input
Constant k2, the second input coupling of output end and the adder in the 4th grade of filter unit 504；In 4th grade of filter unit 504
2 delay cells be cascaded, and in the input of first order delay cell therein and 3rd level filter unit 503
The output end coupling of adder；
In 5th grade of filter unit 505, including 1 delay cell, 1 adder and 2 multipliers, wherein：5th grade
The output end coupling of adder in filter unit 505, first input end and the adder in the 4th grade of filter unit 504, output
End output filter result Yn；The output end coupling of multiplier 5051, first input end and the adder in the 4th grade of filter unit 504
Connect, the second input input constant k0, the first input end coupling of output end and the adder in the 5th grade of filter unit 505；Multiply
The output end coupling of musical instruments used in a Buddhist or Taoist mass 5052, first input end and the delay cell in the 5th grade of filter unit 505, the input of the second input
k1, the second input coupling of output end and the adder in the 5th grade of filter unit 505；Prolonging in the 5th grade of filter unit 505
The output end coupling of slow unit, input and the adder in the 4th grade of filter unit 504.
Understand in actual applications, the adder of digital circuit can bring the extension of bit bit wide, the bigger filtering of series
Output bit wide is bigger corresponding to adder in unit.
Specifically, by taking the digital filter provided in Fig. 4 as an example, if inputting signal X to be filterednIt is 4 bit bit wides, that
The bit wide of adder output in 1st grade of filter unit be 5 bits, the bit wide that the adder in the 2nd grade of filter unit exports
For 6 bits, the bit wide of the adder output in 3rd level filter unit be 7 bits, and the adder in the 4th grade of filter unit exports
Bit wide be 8 bits, the bit wide of the adder output in the 5th grade of filter unit is 9 bits.Now, in the 5th grade of filter unit
The time delay chain of 16 delay cell compositions needs to postpone the data of 8 bits, that is to say, that, it is necessary to postpone 16 × 8=128 bits
Data, cause the waste of resource.
And the digital filter for being provided in Fig. 5, setting input signal X to be filteredn4 bit bit wides, then the 1st grade of filter
The bit wide of adder in ripple unit 501 is 5 bits, now, what 16 delay cells in first order filter unit 501 formed
What time delay chain postponed is the data of 4 bits, that is to say, that only needs to postpone the data of 64 bits.Compared with the scheme in Fig. 4,
Digital filter in Fig. 5 can reduce the waste of resource.
In Fig. 5, Z-1It is expressed as 1 delay cell, Z-2It is expressed as the delay cell of 2 series connection, Z-4It is expressed as 4 series connection
Delay cell, by that analogy, Z-16It is expressed as the delay cell of 16 series connection.
In specific implementation, the digital filter may have multiple output ends, with the filtering knot of the corresponding number of output
Fruit.The output end of adder in each filter unit can be as the output end of digital filter, therefore there may be n
+ 1 output end, n+1 filter result can be also exported, can also only select the output end of certain several filter unit therein
Output end of the mouth as digital filter.For example, in Fig. 4, adder in the 3rd level filter unit 403 in Fig. 4 is chosen
Export and be used as output port 1, the output of the adder in the 4th grade of filter unit 404 of selection chooses the 5th grade as output port 2
The output of adder in filter unit 405 is as output port 3.
It is understood that in actual applications, can also from the output end of the adder in n+1 filter unit,
One of optional or multiple output ends as digital filter, are not repeated herein.
In actual applications, it may only need a kind of output of wave filter therein, in the embodiment of the present invention, also carry
Another digital filter has been supplied, can also include Y selecting unit in the digital filter, wherein：
Y level filter units, including 2n-yIndividual delay cell, 1 multiplier and 1 adder, wherein：
Multiplier in y level filter units, first input end and described 2n-yThe delay of afterbody in individual delay cell
The output end coupling of unit, the second input input constant ky, the second input coupling of output end and the adder；
The output end coupling of adder in y level filter units, first input end and y-1 level selecting units, output
End and the first input end of i-stage selecting unit couple；
2 in y level filter unitsn-yThe series connection of individual delay cell, and the input of first order delay cell therein and the
The output end coupling of y-1 level selecting units；1≤y≤Y, 1≤Y≤n；
Y level selecting units, the second input input signal to be filtered；The in output end and y+1 level filter units
The input coupling of one-level delay cell；Control terminal inputs control signal, defeated from the first input end of the y level selecting units
Selected in the signal that the signal entered and the second input input all the way as output.
In embodiments of the present invention, selecting unit can be MUX.It is understood that selecting unit can be with
For the other kinds of component with selection function, do not repeat herein.
Reference picture 6, give a kind of structural representation of digital filter in the embodiment of the present invention.Digital filter bag
Include：1st grade of filter unit 601, the 2nd grade of filter unit 602,3rd level filter unit 603, the 4th grade of filter unit 604 and the 5th
Level filter unit 605 and the 6th grade of filter unit 606, and first order selecting unit 607, second level selecting unit 608 and
Third level selecting unit 609.
In Fig. 6, in the 1st grade of filter unit 601, including 32 delay cells, 1 multiplier and 1 adder；2nd
In level filter unit 602, including 16 delay cells, 1 multiplier and 1 adder；In 3rd level filter unit 603, bag
Include 8 delay cells, 1 multiplier and 1 adder；In 4th grade of filter unit 604, including 4 delay cells, 1 multiply
Musical instruments used in a Buddhist or Taoist mass and 1 adder；In 5th grade of filter unit 605, including 2 delay cells, 1 multiplier and 1 adder；
In 6th grade of filter unit 606, including 1 delay cell, 2 multipliers and 1 adder.
In the 1st grade of filter unit 601, the afterbody delay in the first input end of multiplier and 32 delay cells
The output end coupling of unit, the second input input constant k1, the of output end and the adder in the 1st grade of filter unit 601
Two inputs couple；The first input end of adder inputs signal X to be filteredn, the of output end and first order selecting unit 607
One input couples；32 delay cells are cascaded, and the input of first order delay cell inputs signal X to be filteredn。
In the 2nd grade of filter unit 602, the afterbody delay in the first input end of multiplier and 16 delay cells
The output end coupling of unit, the second input input constant k2, the of output end and the adder in the 2nd grade of filter unit 602
Two inputs couple；The first input end of adder couples with the output end of first order selecting unit 607, output end and the second level
The first input end coupling of selecting unit 608；16 delay cells are cascaded, and the input of first order delay cell with
The output end coupling of first order selecting unit 607.
In 3rd level filter unit 603, the afterbody delay in the first input end of multiplier and 8 delay cells
The output end coupling of unit, the second input input constant k3, the of adder in output end and 3rd level filter unit 603
Two inputs couple；The first input end of adder couples with the output end of second level selecting unit 608, output end and the third level
The first input end coupling of selecting unit 609；8 delay cells are cascaded, and the input of first order delay cell with
The output end coupling of second level selecting unit 608.
In the 4th grade of filter unit 604, the afterbody delay in the first input end of multiplier and 4 delay cells
The output end coupling of unit, the second input input constant k4, the of output end and the adder in the 4th grade of filter unit 604
Two inputs couple；The first input end of adder and the output end of third level selecting unit 609 couple, output end with the 5th grade
The first input end coupling of adder in filter unit；4 delay cells are cascaded, and the input of first order delay cell
End and the output end of third level selecting unit 609 couple.
In the 5th grade of filter unit 605, the afterbody delay in the first input end of multiplier and 2 delay cells
The output end coupling of unit, the second input input constant k5, the of output end and the adder in the 5th grade of filter unit 605
Two inputs couple；The first input end of the output end of adder and the adder in the 6th grade of filter unit 606 couples；2 are prolonged
The input of first order delay cell in slow unit and the output end of the adder in the 4th grade of filter unit 604 couple.
In the 6th grade of filter unit 606, the addition in the first input end of multiplier 6061 and the 5th grade of filter unit 605
The output end coupling of device, the second input input constant k7, output end and first of the adder in the 6th grade of filter unit 606
Input couples；The output end of the first input end of multiplier 6062 and the delay cell in the 6th grade of filter unit 606 couples,
Second input input constant k6, the second input coupling of output end and the adder in the 6th grade of filter unit 606；Addition
The output end output filter result Y of devicen；The input of 1 delay cell is defeated with the adder in the 5th grade of filter unit 605
Go out end coupling.
First order selecting unit 607, the second input input signal X to be filteredn；Output end and the 2nd grade of filter unit 602
In first order delay cell input and adder first input end coupling；Control terminal inputs control signal 1, works as control
When signal 1 processed is high level, first order selecting unit 607 selects the signal of the second input input as output；When control is believed
Number 1 when being low level, and first order selecting unit 607 selects the signal of first input end input as output.
Second level selecting unit 608, the second input input signal X to be filteredn, output end and 3rd level filter unit 603
In first order delay cell input and adder first input end coupling；Control terminal inputs control signal 2, works as control
When signal 2 processed is high level, second level selecting unit 608 selects the signal of the second input input as output；When control is believed
Numbers 2 when being low level, and second level selecting unit 608 selects the signal of first input end input as output.
Third level selecting unit 609, the second input input signal X to be filteredn, output end and the 4th grade of filter unit 604
In first order delay cell input and adder first input end coupling；Control terminal inputs control signal 3, works as control
When signal 3 processed is high level, third level selecting unit 609 selects the signal of the second input input as output；When control is believed
Numbers 3 when being low level, and third level selecting unit 609 selects the signal of first input end input as output.
It should be noted that the coefficient of the digital filter provided in Fig. 6 needs to meet following condition：Filter coefficient set
Close in A, the ratio between preceding 32 elements and rear 32 elements is k1, the ratio between preceding 16 elements and adjacent 16 elements
It is worth for k2, the ratio between preceding 8 elements and adjacent 8 elements is k3, the ratio between preceding 4 elements and adjacent 4 elements
It is worth for k4, the ratio between preceding 2 elements and adjacent 2 elements is k5, the ratio between preceding 1 element and adjacent 1 element
It is worth for k6, first element value in the coefficient of digital filter is k7。
In Fig. 6, Z-1It is expressed as 1 delay cell, Z-2It is expressed as the delay cell of 2 series connection, Z-4It is expressed as 4 series connection
Delay cell, by that analogy, Z-32It is expressed as the delay cell of 32 series connection.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (7)
- A kind of 1. digital filter, it is characterised in that the collection of filter coefficient is combined into set A corresponding to the digital filter, Element number N in the set A meets N=2n× m, and for any i, preceding 2 in set An-iThe set of × m element With adjacent 2n-iWhen the set of × m element is in proportionate relationship, the digital filter includes：The filtering list of n+1 series connection Member, wherein：In n filter unit, i-th of filter unit includes 2i-1× m delay cell, 1 adder and 1 multiplier；A remaining filter unit includes m-1 delay cell, m-1 adder and m multiplier；1≤i≤n, m, n It is integer, and m ＞ 1.
- 2. digital filter as claimed in claim 1, it is characterised in that single according to postponing in the filter unit of n+1 series connection The number of member, the filter unit of described n+1 series connection is ranked up.
- 3. digital filter as claimed in claim 2, it is characterised in that in the filter unit of the n+1 series connection, previous stage Delay cell number in filter unit is less than the delay cell number in rear stage filter unit, wherein：J-th stage filter unit includes 2j-2× m delay cell, 1 adder and 1 multiplier, wherein：Adder in the j-th stage filter unit, first input end and the output end of the adder in -1 grade of filter unit of jth Coupling, the first input end of output end and the adder in+1 grade of filter unit of jth couple；Multiplier in the j-th stage filter unit, first input end and described 2j-2Afterbody in × m delay cell The output end coupling of delay cell, the second input input constant kj, the adder in output end and the j-th stage filter unit The second input coupling；In the j-th stage filter unit, adder in -1 grade of filter unit of input and jth of first order delay cell it is defeated Go out end coupling；1st grade of filter unit includes m-1 delay cell, m-1 adder and m multiplier；Wherein, j is integer and 2≤j≤n+1.
- 4. digital filter as claimed in claim 2, it is characterised in that in the filter unit of the n+1 series connection, previous stage Delay cell number in filter unit is more than the delay cell number in rear stage filter unit, wherein：As j≤n, j-th stage filter unit includes 2n-j× m delay cell, 1 adder and 1 multiplier, wherein：Adder in the j-th stage filter unit, first input end and the output end of the adder in -1 grade of filter unit of jth Coupling, the first input end of output end and the adder in+1 grade of filter unit of jth couple；Multiplier in the j-th stage filter unit, first input end and described 2n-jAfterbody in × m delay cell The output end coupling of delay cell, the second input input constant kj, the adder in output end and the j-th stage filter unit The second input coupling；In the j-th stage filter unit, adder in -1 grade of filter unit of input and jth of first order delay cell it is defeated Go out end coupling；As j=n+1, j-th stage filter unit includes m-1 delay cell, m-1 adder and m multiplier；Wherein, j is integer and 1≤j≤n+1.
- 5. digital filter as claimed in claim 4, it is characterised in that as n >=1, the digital filter also includes：Y Individual selecting unit, wherein：In y level filter units, including 2n-yIndividual delay cell, 1 multiplier and 1 adder, wherein：The y levels filter Multiplier in ripple unit, first input end and described 2n-yThe output end coupling of the delay cell of afterbody in individual delay cell Connect, the second input input constant ky, the second input coupling of output end and the adder in the y level filter units； Adder in the y level filter units, first input end and y-1 level selecting units output end coupling, output end with The first input end coupling of y level selecting units；2 in the y level filter unitsn-yIndividual delay cell series connection, and it is therein The input of first order delay cell and the output end of y-1 level selecting units couple；1≤y≤Y, 1≤Y≤n；Y levels select Unit, the second input input signal to be filtered；The input coupling of output end and the level delay cell in y+1 level filter units Connect；Control terminal inputs control signal, the signal and the second input inputted from the first input end of the y level selecting units Selected in the signal of input all the way as output.
- 6. digital filter as claimed in claim 5, it is characterised in that the selecting unit is MUX.
- 7. digital filter as claimed in claim 1, it is characterised in that the digital filter includes：Multiple output ports, The output port includes：The output port of multiple filter units in the n+1 filter unit.
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| CN2669481Y (en) * | 2003-12-26 | 2005-01-05 | 上海复旦微电子股份有限公司 | Digital comb type filter circuit structure |
| US20060222083A1 (en) * | 2002-12-19 | 2006-10-05 | Klein Gunnewiek Reinier B M | Digital filter with spatial scalability |
| CN101227537A (en) * | 2007-01-19 | 2008-07-23 | 中兴通讯股份有限公司 | Broadband acoustics echo eliminating method |
| CN104883157A (en) * | 2015-05-18 | 2015-09-02 | 华侨大学 | Variable sub-band digital filter |
| CN105262503A (en) * | 2015-07-16 | 2016-01-20 | 中国电子科技集团公司第四十一研究所 | Group delay calibration based multipath delay generation device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060222083A1 (en) * | 2002-12-19 | 2006-10-05 | Klein Gunnewiek Reinier B M | Digital filter with spatial scalability |
| CN2669481Y (en) * | 2003-12-26 | 2005-01-05 | 上海复旦微电子股份有限公司 | Digital comb type filter circuit structure |
| CN101227537A (en) * | 2007-01-19 | 2008-07-23 | 中兴通讯股份有限公司 | Broadband acoustics echo eliminating method |
| CN104883157A (en) * | 2015-05-18 | 2015-09-02 | 华侨大学 | Variable sub-band digital filter |
| CN105262503A (en) * | 2015-07-16 | 2016-01-20 | 中国电子科技集团公司第四十一研究所 | Group delay calibration based multipath delay generation device and method |
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