CN107623507B

CN107623507B - Digital filter

Info

Publication number: CN107623507B
Application number: CN201610559802.5A
Authority: CN
Inventors: 李夏禹; 陆继承; 赵晓冬; 王椿珊; 张幸幸
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2016-07-15
Filing date: 2016-07-15
Publication date: 2020-03-27
Anticipated expiration: 2036-07-15
Also published as: CN107623507A

Abstract

A digital filter for a digital signal to be filtered,the set of filter coefficients corresponding to the digital filter is set A, and the number N of elements in the set A satisfies N2ⁿX m, and for any i, the first 2 in set A^n‑iSet of x m elements and adjacent 2^n‑iWhen the set of xm elements are all proportional, the digital filter comprises: n +1 series-connected filter units, wherein: of the n filter units, the ith filter unit includes 2^i‑1Xm delay units, 1 adder, and 1 multiplier; the remaining one filtering unit comprises m-1 delay units, m-1 adders and m multipliers; i is more than or equal to 1 and less than or equal to n, m and n are integers, and m is more than 1. The scheme can simplify the structure of the digital filter, reduce the times of addition and subtraction operation and reduce the consumption of logic resources.

Description

Digital filter

Technical Field

The invention relates to the field of digital signals, in particular to a digital filter.

Background

The digital filter is an algorithm or a device composed of a digital multiplier, an adder and a delay unit. The digital filter is used for operating the digital signal of the input discrete signal so as to achieve the purpose of changing the frequency spectrum.

In the prior art, for a Finite Impulse Response (FIR) filter, the expression is

Wherein, Y_nIs the output of a digital filter, x_iIs an input of a digital filter, a_iFor the coefficients of the digital filter, the corresponding system transfer function is

Referring to fig. 1, a circuit structure diagram of a general digital filter is shown, wherein Z is^-1Representing a delay of one clock cycle, is represented in circuit implementation as a flip-flop. When the sampling point corresponding to the coefficient of the digital filter is n, n-1 triggers, n multipliers and n-1 adders/subtractors are needed to be arranged in the digital filter. When the number n of sampling points is large, the structure of the digital filter is complex, the number of addition and subtraction operations is large, and the consumption of logic resources is large.

Disclosure of Invention

The invention solves the technical problem of how to simplify the structure of the digital filter, reduce the times of addition and subtraction operation and reduce the consumption of logic resources.

To solve the foregoing technical problem, an embodiment of the present invention provides a digital filter, where a set of filter coefficients corresponding to the digital filter is a set a, and a number N of elements in the set a satisfies that N is 2ⁿX m, and for any i, the first 2 in set A^n-iSet of x m elements and adjacent 2^n-iWhen the set of xm elements are all proportional, the digital filter comprises: n +1 series-connected filter units, wherein: of the n filter units, the ith filter unit includes 2^i-1The filter comprises x m delay units, 1 adder and 1 multiplier, wherein the rest filter units comprise m-1 delay units, m-1 adders and m multipliers; i is more than or equal to 1 and less than or equal to n, m and n are integers, and m is more than 1.

Optionally, the n +1 series-connected filtering units are sorted according to the number of delay units in the n +1 series-connected filtering units.

Optionally, in the n +1 filtering units connected in series, the number of delay units in the previous filtering unit is less than the number of delay units in the next filtering unit, where: the j-th stage of the filter unit comprises 2^j-2Xm delay units, 1 adder, and 1 multiplier, wherein: an adder in the j-th stage filter unit, a first input end and an output of the adder in the j-1 th stage filter unitThe output end of the adder is coupled with the first input end of the (j +1) th stage filter unit; multiplier, first input terminal and 2 in j-th stage filter unit^j-2The output end of the last stage delay unit in the x m delay units is coupled, and the constant k is input into the second input end_jThe output end of the adder is coupled with the second input end of the adder in the j-th stage filtering unit; in the j-th stage filtering unit, the input end of the first stage delay unit is coupled with the output end of the adder in the j-1 th stage filtering unit; the 1 st stage of filtering unit comprises m-1 delay units, m-1 adders and m multipliers; wherein j is an integer and is not less than 2 and not more than n + 1.

Optionally, in the n +1 filtering units connected in series, the number of delay units in the previous filtering unit is greater than the number of delay units in the next filtering unit, where: when j is less than or equal to n, the j-th stage of filtering unit comprises 2^n-jXm delay units, 1 adder, and 1 multiplier, wherein: the first input end of the adder in the j-th stage filtering unit is coupled with the output end of the adder in the j-1 th stage filtering unit, and the output end of the adder in the j +1 th stage filtering unit is coupled with the first input end of the adder; multiplier, first input terminal and 2 in j-th stage filter unit^n-jThe output end of the last stage delay unit in the x m delay units is coupled, and the constant k is input into the second input end_jThe output end of the adder is coupled with the second input end of the adder in the j-th stage filtering unit; in the j-th stage filtering unit, the input end of the first stage delay unit is coupled with the output end of the adder in the j-1 th stage filtering unit; when j is n +1, the j-th stage of filtering unit comprises m-1 delay units, m-1 adders and m multipliers; wherein j is an integer and is more than or equal to 1 and less than or equal to n + 1.

Optionally, the digital filter further includes: y selection units, wherein: in the y-th stage of filtering unit, including 2^n-yDelay units, 1 multiplier and 1 adder, wherein: multiplier, first input terminal and 2 in the y-th stage filtering unit^n-yThe output end of the delay unit of the last stage in the delay units is coupled, and the constant k is input to the second input end_yThe output end of the adder is coupled with the second input end of the y-th stage filtering unit; the first input end of the adder in the y-th stage filtering unit is coupled with the output end of the y-1-th stage selection unit, and the output end of the adder is coupled with the first input end of the y-th stage selection unit; 2 in the y-th stage filtering unit^n-yThe delay units are connected in series, and the input end of the first-stage delay unit is coupled with the output end of the y-1 th-stage selection unit; y is more than or equal to 1 and less than or equal to Y, and Y is more than or equal to 1 and less than or equal to n; the second input end of the y-level selection unit inputs a signal to be filtered; the output end of the filter is coupled with the input end of the stage delay unit in the (y +1) th stage filter unit; the control end inputs a control signal, and one path of signal is selected from the signal input by the first input end and the signal input by the second input end of the y-th-level selection unit as output.

Optionally, the selection unit is a multiplexer.

Optionally, the digital filter includes: a plurality of output ports, the output ports comprising: output ports of a plurality of filtering units of the n +1 filtering units.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

when the filter coefficient order N corresponding to the digital filter satisfies 2ⁿX m, and for any i, the first 2 in set A^n-iSet of x m elements and adjacent 2^n-iWhen the x m element sets are all in a proportional relationship, the digital filter can be divided into N +1 filter units connected in series, and the N +1 filter units need N-1 delay units, m + N-1 adders and m + N-1 multipliers in total. Compared with the prior art that N-1 delay units, N-1 adders and N multipliers are needed when the filter coefficient order is N, the scheme can effectively reduce the number of the adders and the multipliers, so that the structure of the digital filter can be simplified, the addition and subtraction operation times can be reduced, and the logic resource consumption can be reduced.

Further, providing a plurality of output ports in the digital filter may enable the digital filter to simultaneously produce the outputs of a plurality of filters of different coefficients.

Furthermore, according to the difference of the number of the delay units, the n stages of filter units connected in series are set according to the number of the delay units, the number of the delay units in the previous stage of filter unit is more than or equal to the number of the delay units in the next stage of filter unit, so that the bit width data corresponding to the delay units with the largest number is reduced, and resources can be saved.

In addition, a selection unit is added in the digital filter, one path of output of the filters with different coefficients can be selected as output, and the output of the digital filter can be flexibly selected.

Drawings

Fig. 1 is a schematic diagram of a conventional digital filter;

FIG. 2 is a schematic diagram of a digital filter according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a first filtering unit according to an embodiment of the invention;

FIG. 4 is a schematic diagram of another digital filter in an embodiment of the invention;

FIG. 5 is a schematic diagram of a digital filter according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of a digital filter in an embodiment of the present invention.

Detailed Description

In some application scenarios, the coefficients of the filter may be special. For example, in the field of smart card communications, the signal sent by the card to the card machine uses a square wave with a frequency of 848KHz as a subcarrier, and a baseband signal is modulated onto the subcarrier first and then onto a radio frequency carrier with a frequency of 13.56 MHz. When a card machine receives signals, radio frequency carriers are usually removed at an analog front end, and then are sampled by an ADC and demodulated by a digital circuit. In this case, digital demodulation generally employs a matched filtering method to detect subcarriers in a received signal. The matched filter may select N subcarriers as filter coefficients as needed.

For example, the coefficients of the matched filter correspond to 16 samples [ 1111-1-1-1-11111-1-1-1 ], where the subcarrier high level corresponds to 1 in the sample and the subcarrier low level corresponds to-1 in the sample, and the expression y (n) of the corresponding matched filter is shown in the following formula (1):

Y(n)＝X(n)+X(n-1)+X(n-2)+X(n-3)-X(n-4)-X(n-5)-X(n-6)-X(n-7)+X(n-8)+X(n-9)+X(n-10)+X(n-11)-X(n-12)-X(n-13)-X(n-14)-X(n-15)； (1)

correspondingly, the system transfer function h (z) of the matched filter is shown in the following formula (2):

H(z)＝z⁰+z^-1+z^-2+z^-3-z^-4-z^-5-z^-6-z^-7+z^-8+z^-9+z^-10+z^-11-z^-12-z^-13-z^-14-z^-15； (2)

in the prior art, the structure of the corresponding matched filter for the transfer function shown in formula (2) is shown in fig. 1, wherein Z^-1Representing a delay of one clock cycle, represented in circuit implementation as a flip-flop, a₀、a₁、a₂、……、a_nThe coefficients of the filter are respectively corresponding to the multipliers one by one. The matched filter requires the use of 15 flip-flops, 16 multipliers and 15 add/subtractors. When the coefficient of the FIR filter is larger, the structure of the FIR filter is more complex, the number of required addition and subtraction operations is more, and the consumption of logic resources is larger.

In the embodiment of the invention, when the order N of the filter coefficient corresponding to the digital filter satisfies 2ⁿX m, and for any i, the first 2 in set A^n-iSet of x m elements and adjacent 2^n-iWhen the x m element sets are all in a proportional relationship, the digital filter can be divided into N +1 filter units connected in series, and the N +1 filter units need N-1 delay units, m + N-1 adders and m + N-1 multipliers in total. Compared with the prior art that N-1 delay units, N-1 adders and N multipliers are needed when the filter coefficient order is N, the scheme can effectively reduce the number of the adders and the multipliers, so that the structure of the digital filter can be simplified, the addition and subtraction operation times can be reduced, and the logic resource consumption can be reduced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The embodiment of the invention provides a digital filter, wherein the filter coefficient corresponding to the digital filter needs to meet the following conditions: the set of filter coefficients is set A, and the number N of elements in the set A satisfies N-2ⁿX m, and for any i, the first 2 in set A^n-iSet of x m elements and adjacent 2^n-iThe collection of x m elements is in a proportional relation, wherein i is more than or equal to 1 and less than or equal to n, m and n are integers, and m is more than 1.

When the coefficients of the digital filter satisfy the above conditions, in an embodiment of the present invention, the digital filter may include n +1 filtering units. In n +1 filtering units, one filtering unit comprises m-1 delay units, m-1 adders and m multipliers; of the remaining n filter units, the ith filter unit includes 2^i-1Xm delay units, 1 adder, and 1 multiplier.

The digital filter provided in the above-described embodiment of the present invention is exemplified below.

For example, the set of filter coefficients corresponding to the digital filter is a, the set a includes N elements, N is an even number, the set of the first N/2 elements in the set a is a1, and the set of N/2 elements adjacent to the set a1 in the set a is a 2. For the constant k, there is a1 ═ k × a 2. Accordingly, the transfer function a1(Z) corresponding to the set a1 and the transfer function a2(Z) corresponding to the set a2 satisfy the following relationship: a1(Z) ═ k × a2(Z), that is, a2(Z) ═ 1/k × a1 (Z).

At this time, the transfer function h (z) of the digital filter can be simplified to the following formula (3):

H(z)＝A(z)＝A1(z)+A2(z)×Z^-(N/2)

＝A1(z)+1/k×A1(z)×Z^-(N/2)＝A1(z)×(1+1/k×Z^-(N/2)) (3)

referring to fig. 2, a schematic diagram of a digital filter corresponding to a transfer function corresponding to equation (3) in an embodiment of the present invention is shownIn 2, Z^-N/2Shown as N/2 delay cells in series.

In fig. 2, the set of filter coefficients corresponding to the first filtering unit 201 is set a1, and the corresponding transfer function is a1(Z) in equation (3); the set of filter coefficients corresponding to the second filtering unit 202 is set a2, and the corresponding transfer function is 1+ 1/kxz in equation (3)^-(N/2)。

The input end of the first filtering unit 201 inputs the signal X to be filtered_nThe output terminal is coupled to the first input terminal of the adder of the second filtering unit 202; in the second filtering unit 202, of N/2 delay units connected in series, the input terminal of the first stage delay unit is coupled to the output terminal of the first filtering unit 201, and the output terminal of the last stage delay unit is coupled to the first input terminal of the multiplier in the second filtering unit 202; a multiplier in the second filtering unit 202, with a second input end inputting a constant 1/k, and an output end coupled to a second input end of the adder in the second filtering unit 202; the output of the adder in the second filtering unit 202 outputs the filtering result Y_n。

As can be seen from fig. 2, the second filtering unit 202 includes N/2 delay units, 1 multiplier, and 1 adder. In the prior art, the second filtering unit 202 includes N/2 delay units, N/2 multipliers, and N/2 adders. The digital filter provided by the embodiment of the invention can save N/2-1 multipliers and N/2-1 adders.

Therefore, compared with the prior art that N-1 delay units, N-1 adders and N multipliers are needed when the filter coefficient order is N, the scheme provided by the embodiment of the invention can effectively reduce the number of the adders and the multipliers, thereby simplifying the structure of the digital filter, reducing the times of addition and subtraction operation and reducing the consumption of logic resources.

In the embodiment of the present invention, the structure of the first filtering unit 201 may be similar to that shown in fig. 1.

Referring to fig. 3, a schematic structural diagram of a first filtering unit in an embodiment of the present invention is shown. In fig. 3, the filter corresponding to the first filtering unitSet of coefficients a1 ═ { a ═ a₀，a₁，a₂，a₃Therefore, the number of corresponding delay units is 3, the number of adders is 3, and the number of multipliers is 4.

In the first filtering unit:

a delay unit 301 having an input terminal for inputting a signal X to be filtered_nThe output terminal is coupled to the input terminal of the delay unit 302; a multiplier 304 having an output coupled to a first input of the adder 308, the first input inputting the signal to be filtered X_nThe second input end inputs the 1 st filter coefficient in the set A1, that is, the input coefficient is a₀(ii) a A multiplier 305 having a first input coupled to the output of the delay unit 301 and a second input for the 2 nd filter coefficient from the set A1, i.e. the input coefficient is a₁(ii) a An adder 308 having a second input coupled to the output of the multiplier 305 and an output coupled to a first input of the adder 309; a delay unit 302, an output terminal of which is coupled to an input terminal of the delay unit 303; a multiplier 306 having a first input coupled to the output of the delay unit 302 and a second input for the 3 rd filter coefficient from the set A1, i.e. the input coefficient is a₂And an output coupled to a second input of adder 309; an output terminal of adder 309 is coupled to a first input terminal of adder 310; a delay unit 303, an output terminal of which is coupled to a first input terminal of the multiplier 307; the 4 th filter coefficient in the set A1 is input to the multiplier 307 at the second input end, that is, the input coefficient is a₃And an output terminal coupled to a second input terminal of adder 310.

In the embodiment of the present invention, the arrangement order of the n +1 filtering units may be set arbitrarily, or may be sorted according to the number of delay units included in each filtering unit.

When the arrangement order of the n +1 filtering units is sorted according to the number of the delay units included in the filtering units, the filtering unit including the smallest number of delay units may be used as the filtering unit of the 1 st stage, the number of delay units in each filtering unit of the subsequent stage is larger than the number of delay units in the filtering unit of the previous stage, and the filtering unit of the n +1 th stage is the filtering unit of the last stageAnd (4) units. At this time, the 1 st stage of filtering unit includes m-1 delay units, m-1 adders and m multipliers, and the n +1 st stage of filtering unit includes 2^n-1Xm delay units, 1 adder, and 1 multiplier.

When the number of delay units in the previous stage of filter unit is less than that of delay units in the next stage of filter unit in the n +1 filter units connected in series, the number of delay units in the n +1 filter units connected in series is as follows:

a filter unit corresponding to the j-th stage and including 2^j-2Xm delay units, 1 adder, and 1 multiplier, wherein:

the first input end of the adder in the j-th stage filtering unit is coupled with the output end of the adder in the j-1 th stage filtering unit, and the output end of the adder in the j +1 th stage filtering unit is coupled with the first input end of the adder;

multiplier in j-th stage filter unit, first input end and 2^j-2The output end of the last stage delay unit in the x m delay units is coupled, and the constant k is input into the second input end_jThe output end of the adder is coupled with the second input end of the adder in the j-th stage filtering unit;

in the j-th stage filter unit, the input end of the first stage delay unit is coupled with the output end of the adder in the j-1 th stage filter unit;

the 1 st stage of filtering unit comprises m-1 delay units, m-1 adders and m multipliers;

wherein j is an integer and is not less than 2 and not more than n + 1.

Referring to fig. 4, a schematic structural diagram of a digital filter in an embodiment of the present invention is shown. The number of elements in the filter coefficient set a of the digital filter corresponding to fig. 4 is 32, and the set a1 composed of the first 16 elements in the set a and the set a2 composed of the adjacent 16 elements satisfy a1 ═ k₅X A2; the set B1 of the first 8 elements in the set a1 and the set B2 of the adjacent 8 elements satisfy that B1 ═ k₄X B2; the set C1 of the first 4 elements in the set B1 and the set C2 of the adjacent 4 elements satisfy that C1 ═ k₃X C2; the set D1 consisting of the first 2 elements in the set C1 and the adjacent 2 elementsThe set of constituents D2 satisfies D1 ═ k₂X D2; the set E1 of the first 1 element in the set D1 and the set E2 of the adjacent 1 element satisfy that E1 ═ k₁×E2。

Thus, the digital filter comprises (4+1) ═ 5 filtering units, in turn: a level 1 filtering unit 401, a level 2 filtering unit 402, a level 3 filtering unit 403, a level 4 filtering unit 404, and a level 5 filtering unit 405, where m is 2, and at this time:

in the stage 1 filtering unit 401, the filtering unit includes 1 delay unit, 1 adder, and 2 multipliers, where: the input end of the delay unit in the 1 st stage filtering unit 401 inputs the signal X to be filtered_nThe output terminal is coupled to the first input terminal of the multiplier 4012 in the stage 1 filtering unit 401; a multiplier 4011 having a first input end for inputting a signal X to be filtered_nThe output terminal is coupled to the first input terminal of the adder in the 1 st stage filtering unit 401, and the second input terminal is input to the 1 st element k in the filter coefficient set₀(ii) a A multiplier 4012, the second input end is input into the filter coefficient set, and the ratio k of the 1 st element to the 2 nd element₁The output terminal is coupled to the first input terminal of the adder in the stage 1 filtering unit 401; an adder in the filtering unit 401 of stage 1, the output terminal of which is coupled to a first input terminal of the adder in the filtering unit 402 of stage 2;

in the 2 nd

stage filtering unit

402, 2 is included^2-2 X 2 ═ 2 delay elements, 1 adder, and 1 multiplier, where: an adder in the filtering unit 402 of stage 2, a first input terminal of which is coupled to an output terminal of the adder in the filtering unit 401 of stage 1, and an output terminal of which is coupled to a first input terminal of the adder in the filtering unit 403 of stage 3; a multiplier in the 2 nd stage filter unit 402, a first input terminal coupled to the output terminal of the last stage delay unit in the 2 delay units, and a second input terminal with a constant k₂The output terminal is coupled to the second input terminal of the adder in the 2 nd stage filtering unit 402; in the 2 nd stage filtering unit 402, the input terminal of the first stage delay unit is coupled to the output terminal of the adder in the 1 st stage filtering unit 401;

in the 3 rd

stage filtering unit

403, 2 is included^3-2X 2-4 delay units, 1 adder, and 1 multiplier, where: an adder in the 3 rd stage filtering unit 403, a first input terminal of which is coupled to an output terminal of the adder in the 2 nd stage filtering unit 402, and an output terminal of which is coupled to a first input terminal of the adder in the 4 th stage filtering unit 404; a multiplier in the 3 rd stage filter unit 403, a first input terminal coupled to the output terminal of the last stage delay unit of the 4 delay units, and a second input terminal to which a constant k is input₃An output terminal is coupled to a second input terminal of the adder in the 3 rd stage filtering unit 403; in the 3 rd stage filtering unit 403, the input terminal of the first stage delay unit is coupled to the output terminal of the adder in the 2 nd stage filtering unit 402;

in the 4 th stage of the

filtering unit

404, 2 is included^4-2X 2-8 delay units, 1 adder, and 1 multiplier, where: an adder in the filtering unit 404 of the 4 th stage, a first input terminal of which is coupled to an output terminal of the adder in the filtering unit 403 of the 3 rd stage, and an output terminal of which is coupled to a first input terminal of the adder in the filtering unit 405 of the 5 th stage; a multiplier in the 4 th stage of filtering unit 404, a first input terminal coupled to the output terminal of the last stage of the 8 delay units, and a second input terminal with a constant k₄The output terminal is coupled to the second input terminal of the adder in the 4 th-stage filtering unit 404; in the 4-stage filtering unit 404, the input terminal of the first-stage delay unit is coupled to the output terminal of the adder in the 3-stage filtering unit 403;

in the 5 th stage of the

filtering unit

405, 2 is included^5-2 X 2 ═ 16 delay elements, 1 adder, and 1 multiplier, where: an adder in the 5 th stage filter unit 405, a first input terminal of which is coupled to an output terminal of the adder in the 4 th stage filter unit 404, and an output terminal of which outputs the filter result Y_n(ii) a A multiplier in the 5 th stage filter unit 405, a first input terminal coupled to the output terminal of the last stage delay unit of the 16 delay units, and a second input terminal to which a constant k is input₅An output terminal is coupled to a second input terminal of the adder in the 5 th stage filtering unit 405; in the 5 th stage filtering unit 405, the input terminal of the first stage delay unit is coupled to the output terminal of the adder in the 4 th stage filtering unit 404.

In FIG. 4, Z^-1Expressed as 1 delay unit, Z^-2Represented as 2 delay cells in series, Z^-4Represented as 4 delay elements in series, and so on, Z^-16Shown as 16 delay cells in series.

It can be understood that the filtering unit containing the largest number of delay units may also be used as the filtering unit of stage 1, the number of delay units in each subsequent stage of filtering unit is smaller than the number of delay units in the previous stage of filtering unit, and the filtering unit of stage n +1 is used as the filtering unit of the last stage. At this time, the (n +1) th stage of filtering unit includes m-1 delay units, m-1 adders and m multipliers, and the 1 st stage of filtering unit includes 2^n-1Xm delay units, 1 adder, and 1 multiplier.

When the number of delay units in the previous stage of filter unit is greater than that of delay units in the next stage of filter unit in the n +1 filter units connected in series, the number of delay units in the n +1 filter units connected in series is as follows:

corresponding to the j-th stage of filtering unit, when j is less than or equal to n, the j-th stage of filtering unit comprises 2^n-jXm delay units, 1 adder, and 1 multiplier, wherein:

multiplier in j-th stage filter unit, first input end and 2^n-jThe output end of the last stage delay unit in the x m delay units is coupled, and the constant k is input into the second input end_jThe output end of the adder is coupled with the second input end of the adder in the j-th stage filtering unit;

when j is n +1, the j-th stage of filtering unit comprises m-1 delay units, m-1 adders and m multipliers;

wherein j is an integer and is more than or equal to 1 and less than or equal to n + 1.

Referring to fig. 5, a schematic diagram of a digital filter according to an embodiment of the present invention is shown, and the filter coefficients of the digital filter in fig. 5 are the same as those of the digital filter in fig. 4. In fig. 5, the 1 st-stage filtering unit 501 includes 16 delay units connected in series, the 2 nd-stage filtering unit 502 includes 8 delay units connected in series, the 3 rd-stage filtering unit 503 includes 4 delay units connected in series, the 4 th-stage filtering unit 504 includes 2 delay units connected in series, and the 5 th-stage filtering unit 505 includes 1 delay unit.

In the 1 st

stage filtering unit

501, 2 is included^4-1 X 2 ═ 16 delay elements, 1 adder, and 1 multiplier, where: the adder in the 1 st stage filtering unit 501 has a first input end for inputting the signal X to be filtered_nThe output terminal is coupled to the first input terminal of the adder in the 2 nd stage filtering unit 502; a multiplier in the 1 st stage filtering unit 501, a first input terminal coupled to the output terminal of the last stage of the 16 delay units, and a second input terminal to which a constant k is input₅The output terminal is coupled to the second input terminal of the adder in the level 1 filtering unit 501; the 16 delay units in the 1 st stage filtering unit 501 are connected in series, and the input end of the first stage delay unit inputs the signal X to be filtered_n；

In the 2 nd

stage filtering unit

502, 2 is included^4-2X 2-8 delay units, 1 adder, and 1 multiplier, where: an adder in the 2 nd stage filtering unit 502, a first input terminal of which is coupled to an output terminal of the adder in the 1 st stage filtering unit 501, and an output terminal of which is coupled to a first input terminal of the adder in the 3 rd stage filtering unit 503; a multiplier in the 2 nd stage filtering unit 502, a first input terminal coupled to the output terminal of the last stage delay unit of the 8 delay units, and a second input terminal to which a constant k is input₄The output terminal is coupled to the second input terminal of the adder in the 2 nd stage filtering unit 502; the 8 delay units in the 2 nd stage filtering unit 502 are connected in series, and the input terminal of the first stage delay unit is coupled to the output terminal of the adder in the 1 st stage filtering unit 501;

in the 3 rd

stage filter unit

503, 2 is included^4-3X 2-4 delay units, 1 adder, and 1 multiplier, where: an adder in the 3 rd stage filtering unit 503, a first input terminal of which is coupled to an output terminal of the adder in the 2 nd stage filtering unit 502, and an output terminal of which is coupled to a first input terminal of the adder in the 4 th stage filtering unit 504; a multiplier in the 3 rd stage filter unit 503, a first input terminal of which is coupled to the output terminal of the last stage delay unit of the 4 delay units, and a second input terminal of which is input with a constant k₃The output terminal is coupled to the second input terminal of the adder in the 3 rd stage filtering unit 503; the 4 delay units in the 3 rd stage filtering unit 503 are connected in series, and the input terminal of the first stage delay unit is coupled to the output terminal of the adder in the 2 nd stage filtering unit 502;

in the 4 th stage of the

filtering unit

504, 2 is included^4-4 X 2 ═ 2 delay elements, 1 adder, and 1 multiplier, where: an adder in the 4-stage filtering unit 504, a first input terminal of which is coupled to an output terminal of the adder in the 3-stage filtering unit 503, and an output terminal of which is coupled to a first input terminal of the adder in the 5-stage filtering unit 505; a multiplier in the 4 th stage of filtering unit 504, a first input terminal coupled to the output terminal of the last stage of delay unit in the 2 delay units, and a second input terminal to which a constant k is input₂The output terminal is coupled to the second input terminal of the adder in the 4 th-stage filtering unit 504; 2 delay units in the 4 th stage filtering unit 504 are connected in series, and the input terminal of the first stage delay unit is coupled to the output terminal of the adder in the 3 rd stage filtering unit 503;

the 5 th stage filtering unit 505 includes 1 delay unit, 1 adder, and 2 multipliers, where: an adder in the filtering unit 505 of the 5 th stage has a first input coupled to an output of the adder in the filtering unit 504 of the 4 th stage and an output outputting the filtering result Y_n(ii) a A multiplier 5051 having a first input coupled to the output of the adder in the 4 th stage filtering unit 504 and a second input to which a constant k is input₀The output terminal is coupled to the first input terminal of the adder in the 5 th stage filtering unit 505; a multiplier 5052 having a first input coupled to the output of the delay unit in the 5 th stage filter unit 505 and a second inputk₁The output terminal is coupled to the second input terminal of the adder in the 5 th stage filtering unit 505; the delay unit in the 5 th stage filter unit 505 has its input coupled to the output of the adder in the 4 th stage filter unit 504.

In practical applications, it is known that an adder of a digital circuit expands bit width, and output bit width corresponding to the adder in a filter unit with a larger number of stages is larger.

In particular, taking the digital filter provided in fig. 4 as an example, if the signal X to be filtered is input_nAnd the bit width is 4 bits, the bit width of the output of the adder in the 1 st-stage filtering unit is 5 bits, the bit width of the output of the adder in the 2 nd-stage filtering unit is 6 bits, the bit width of the output of the adder in the 3 rd-stage filtering unit is 7 bits, the bit width of the output of the adder in the 4 th-stage filtering unit is 8 bits, and the bit width of the output of the adder in the 5 th-stage filtering unit is 9 bits. At this time, the delay chain formed by 16 delay units in the 5 th stage filtering unit needs to delay data with 8 bits, that is, data with 16 × 8-128 bits needs to be delayed, which results in waste of resources.

Whereas for the digital filter provided in fig. 5, the input signal X to be filtered is set_nIs 4 bits wide, the bit width of the adder in the filtering unit 501 of the 1 st stage is 5 bits, and at this time, the delay chain formed by the 16 delay units in the filtering unit 501 of the first stage delays 4 bits of data, that is, only 64 bits of data need to be delayed. The digital filter of fig. 5 can reduce the waste of resources compared to the scheme of fig. 4.

In FIG. 5, Z^-1Expressed as 1 delay unit, Z^-2Represented as 2 delay cells in series, Z^-4Represented as 4 delay elements in series, and so on, Z^-16Shown as 16 delay cells in series.

In a specific implementation, the digital filter may have a plurality of outputs to output a corresponding number of filtering results. The output end of the adder in each filtering unit can be used as the output end of the digital filter, so that n +1 output ends can exist, that is, n +1 filtering results can be output, and the output ends of some filtering units can be selected as the output ends of the digital filter. For example, in fig. 4, the output of the adder in the 3 rd stage filtering unit 403 in fig. 4 is selected as output port 1, the output of the adder in the 4 th stage filtering unit 404 is selected as output port 2, and the output of the adder in the 5 th stage filtering unit 405 is selected as output port 3.

It can be understood that, in practical applications, one or more of the output ends of the adders in the n +1 filtering units may be optionally used as the output end of the digital filter, which is not described herein again.

In practical applications, only one of the filters may be needed to output, and in the embodiment of the present invention, another digital filter is further provided, where the digital filter may further include Y selecting units, where:

a y-th stage of filtering unit comprising 2^n-yDelay units, 1 multiplier and 1 adder, wherein:

multiplier in y-th stage filter unit, first input end and 2^n-yThe output end of the delay unit of the last stage in the delay units is coupled, and the constant k is input to the second input end_yThe output end of the adder is coupled with the second input end of the adder;

the first input end of the adder in the y-th stage of filtering unit is coupled with the output end of the y-1-th stage of selecting unit, and the output end of the adder is coupled with the first input end of the i-th stage of selecting unit;

2 in the y-th stage filter unit^n-yThe delay units are connected in series, and the input end of the first-stage delay unit is coupled with the output end of the y-1 th-stage selection unit; y is more than or equal to 1 and less than or equal to Y, and Y is more than or equal to 1 and less than or equal to n;

the second input end of the y-level selection unit inputs a signal to be filtered; the output end of the delay unit is coupled with the input end of the first stage delay unit in the (y +1) th stage filter unit; the control end inputs a control signal, and one path of signal is selected from the signal input by the first input end and the signal input by the second input end of the y-th-level selection unit as output.

In an embodiment of the present invention, the selection unit may be a multiplexer. It is understood that the selection unit may also be other types of components with selection functions, which are not described herein.

Referring to fig. 6, a schematic diagram of a digital filter according to an embodiment of the present invention is shown. The digital filter includes: a level 1 filtering unit 601, a level 2 filtering unit 602, a level 3 filtering unit 603, a level 4 filtering unit 604, a level 5 filtering unit 605, and a level 6 filtering unit 606, and a first level selection unit 607, a second level selection unit 608, and a third level selection unit 609.

In fig. 6, the 1 st stage filtering unit 601 includes 32 delay units, 1 multiplier and 1 adder; the 2 nd stage filtering unit 602 includes 16 delay units, 1 multiplier and 1 adder; the 3 rd stage filtering unit 603 includes 8 delay units, 1 multiplier, and 1 adder; the 4 th stage filtering unit 604 includes 4 delay units, 1 multiplier and 1 adder; the 5 th stage filtering unit 605 includes 2 delay units, 1 multiplier, and 1 adder; the stage 6 filtering unit 606 includes 1 delay unit, 2 multipliers, and 1 adder.

In the stage 1 filtering unit 601, a first input terminal of the multiplier is coupled to an output terminal of a last stage delay unit of the 32 delay units, and a second input terminal thereof is inputted with a constant k₁The output terminal is coupled to the second input terminal of the adder in the stage 1 filtering unit 601; the first input end of the adder inputs a signal X to be filtered_nThe output terminal is coupled to the first input terminal of the first stage selection unit 607; 32 delay units are connected in series, and the input end of the first stage delay unit inputs the signal X to be filtered_n。

In the 2 nd stage filtering unit 602, a first input terminal of the multiplier is coupled to an output terminal of a last stage delay unit of the 16 delay units, and a second input terminal thereof inputs a constant k₂The output terminal is coupled to the second input terminal of the adder in the 2 nd stage filtering unit 602; a first input of the adder is coupled to the output of the first stage selection unit 607, and an output is coupled to the first input of the second stage selection unit 608The input end is coupled; the 16 delay units are connected in series, and the input terminal of the first stage delay unit is coupled to the output terminal of the first stage selection unit 607.

In the 3 rd stage filter unit 603, a first input terminal of the multiplier is coupled to an output terminal of the last stage delay unit of the 8 delay units, and a second input terminal thereof inputs a constant k₃The output terminal is coupled to the second input terminal of the adder in the 3 rd stage filtering unit 603; a first input of the adder is coupled to an output of the second stage selection unit 608, and an output is coupled to a first input of the third stage selection unit 609; the 8 delay units are connected in series, and the input terminal of the first stage delay unit is coupled to the output terminal of the second stage selection unit 608.

In the 4 th stage filtering unit 604, a first input terminal of the multiplier is coupled to an output terminal of a last stage delay unit of the 4 delay units, and a second input terminal thereof is inputted with a constant k₄The output terminal is coupled to the second input terminal of the adder in the 4 th-stage filtering unit 604; a first input end of the adder is coupled to an output end of the third-stage selection unit 609, and an output end of the adder is coupled to a first input end of an adder in the 5 th-stage filtering unit; the 4 delay units are connected in series, and the input terminal of the first stage delay unit is coupled to the output terminal of the third stage selection unit 609.

In the 5 th stage filtering unit 605, a first input terminal of the multiplier is coupled to an output terminal of the last stage delay unit of the 2 delay units, and a second input terminal thereof is inputted with a constant k₅The output terminal is coupled to the second input terminal of the adder in the 5 th stage filtering unit 605; an output terminal of the adder is coupled to a first input terminal of the adder in the stage 6 filtering unit 606; the input of the first stage of the 2 delay units is coupled to the output of the adder in the 4 th stage of the filtering unit 604.

In the 6 th-stage filtering unit 606, a first input terminal of the multiplier 6061 is coupled to an output terminal of the adder in the 5 th-stage filtering unit 605, and a second input terminal thereof is input with a constant k₇The output terminal is coupled to the first input terminal of the adder in the stage 6 filtering unit 606; first input terminal of multiplier 6062 and in 6 th stage filtering unit 606The output terminal of the delay unit is coupled, and the constant k is input to the second input terminal₆The output terminal is coupled to the second input terminal of the adder in the stage 6 filtering unit 606; the output end of the adder outputs a filtering result Y_n(ii) a The inputs of the 1 delay unit are coupled to the outputs of the adders in the 5 th stage filtering unit 605.

A first stage selection unit 607, a second input terminal for inputting a signal X to be filtered_n(ii) a The output terminal is coupled to the input terminal of the first stage delay unit in the 2 nd stage filtering unit 602 and the first input terminal of the adder; the control terminal inputs a control signal 1, and when the control signal 1 is at a high level, the first-stage selection unit 607 selects the signal input by the second input terminal as an output; when the control signal 1 is at a low level, the first stage selection unit 607 selects the signal inputted from the first input terminal as an output.

A second stage selection unit 608 having a second input terminal for inputting the signal X to be filtered_nThe output terminal is coupled to the input terminal of the first stage delay unit in the 3 rd stage filtering unit 603 and the first input terminal of the adder; the control terminal inputs a control signal 2, and when the control signal 2 is at a high level, the second-stage selection unit 608 selects the signal input by the second input terminal as an output; when the control signal 2 is at a low level, the second stage selection unit 608 selects the signal input from the first input terminal as an output.

A third stage selection unit 609, a second input end of which inputs a signal X to be filtered_nAn output terminal of the adder is coupled to an input terminal of the first stage delay unit in the 4 th stage filtering unit 604; the control end inputs a control signal 3, and when the control signal 3 is at a high level, the third-stage selection unit 609 selects the signal input by the second input end as output; when the control signal 3 is at a low level, the third stage selection unit 609 selects the signal inputted from the first input terminal as an output.

It should be noted that the coefficients of the digital filter provided in fig. 6 need to satisfy the following conditions: in the filter coefficient set A, the ratio of the first 32 elements to the second 32 elements is k₁The ratio between the first 16 elements and the adjacent 16 elements is k₂The first 8 elements are adjacent to the first 8 elementsThe ratio between the elements is k₃The ratio between the first 4 elements and the adjacent 4 elements is k₄The ratio between the first 2 elements and the adjacent 2 elements is k₅The ratio of the first 1 element to the adjacent 1 element is k₆The first element value in the coefficients of the digital filter is k₇。

In FIG. 6, Z^-1Expressed as 1 delay unit, Z^-2Represented as 2 delay cells in series, Z^-4Represented as 4 delay elements in series, and so on, Z^-32Shown as 32 delay cells in series.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A digital filter is characterized in that a set of filter coefficients corresponding to the digital filter is a set A, and the number N of elements in the set A satisfies that N is 2ⁿX m, and for any i, the first 2 in set A^n-iSet of x m elements and adjacent 2^n-iWhen the set of xm elements are all proportional, the digital filter comprises: n +1 series-connected filter units, wherein:

of the n filter units, the ith filter unit includes 2^i-1Xm delay units, 1 adder, and 1 multiplier;

the remaining one filtering unit comprises m-1 delay units, m-1 adders and m multipliers; i is more than or equal to 1 and less than or equal to n, m and n are integers, and m is more than 1.

2. The digital filter of claim 1, wherein the n +1 series-connected filter units are ordered according to the number of delay units in the n +1 series-connected filter units.

3. The digital filter of claim 2, wherein the n +1 serially connected filter units have a smaller number of delay units in a previous filter unit than in a subsequent filter unit, and wherein:

the j-th stage of the filter unit comprises 2^j-2Xm delay units, 1 adder, and 1 multiplier, wherein:

multiplier, first input terminal and 2 in j-th stage filter unit^j-2The output end of the last stage delay unit in the x m delay units is coupled, and the constant k is input into the second input end_jThe output end of the adder is coupled with the second input end of the adder in the j-th stage filtering unit;

in the j-th stage filtering unit, the input end of the first stage delay unit is coupled with the output end of the adder in the j-1 th stage filtering unit;

wherein j is an integer and is not less than 2 and not more than n + 1.

4. The digital filter of claim 2, wherein the n +1 serially connected filter units have a larger number of delay units in a previous filter unit than in a subsequent filter unit, and wherein:

when j is less than or equal to n, the j-th stage of filtering unit comprises 2^n-jXm delay units, 1 adder, and 1 multiplier, wherein:

multiplier, first input terminal and 2 in j-th stage filter unit^n-jThe output terminal of the last stage delay unit in the xm delay units is coupled,constant k is input to the second input terminal_jThe output end of the adder is coupled with the second input end of the adder in the j-th stage filtering unit;

5. The digital filter according to claim 4, wherein when n ≧ 1, the digital filter further comprises: y selection units, wherein:

in the y-th stage of filtering unit, including 2^n-yDelay units, 1 multiplier and 1 adder, wherein: multiplier, first input terminal and 2 in the y-th stage filtering unit^n-yThe output end of the delay unit of the last stage in the delay units is coupled, and the constant k is input to the second input end_yThe output end of the adder is coupled with the second input end of the y-th stage filtering unit; the first input end of the adder in the y-th stage filtering unit is coupled with the output end of the y-1-th stage selection unit, and the output end of the adder is coupled with the first input end of the y-th stage selection unit; 2 in the y-th stage filtering unit^n-yThe delay units are connected in series, and the input end of the first-stage delay unit is coupled with the output end of the y-1 th-stage selection unit; y is more than or equal to 1 and less than or equal to Y, and Y is more than or equal to 1 and less than or equal to n; the second input end of the y-level selection unit inputs a signal to be filtered; the output end of the filter is coupled with the input end of the stage delay unit in the (y +1) th stage filter unit; the control end inputs a control signal, and one path of signal is selected from the signal input by the first input end and the signal input by the second input end of the y-th-level selection unit as output.

6. The digital filter of claim 5, wherein the selection unit is a multiplexer.

7. The digital filter of claim 1, wherein the digital filter comprises: a plurality of output ports, the output ports comprising: output ports of a plurality of filtering units of the n +1 filtering units.