CN100583855C - Cascade integral comb filter - Google Patents
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Abstract
This invention relates to a cascade integral comb filter, comprising integral module, extract module and comb module, and place inside data port and synchronous signal port; the said synchronous signal port is used for transmitting synchronous signals; the said data port is used for the data input according to synchronous signals, and control the transmitted data through the synchronous signals. Through this invention, can adopt data synchronous signal to control data input, solve the problem that the frequency of input data is restricted result from frequency of data transmitted must be the same with master clock in existing technologies, but the invention easy to implement serial processing, and can reduce the time delay in procession. In addition, the invention can also dynamically control variable sample rate and or variable sample phase through the variable counter and comparator set in extract module, thus facilitate the expansion of filter. And the invention can also dynamically control variable exponent number through the selector set in the integral module or comb module.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of cascade integral comb filter.
Background technology
In the software radio IF processing unit, cascaded integrator-comb (CIC) filter extracts the high-speed digital signal of A/D (analog to digital converter) conversion back output, the digital signal of output low rate.If p is the exponent number of cic filter, M is an extraction yield, and then the transfer function of cic filter is:
Cic filter can realize that integral multiple extracts.It is applied to the first order design of the multistage extraction of narrow band signal system usually.The advantage of cic filter is that coefficient all is 1, therefore uses it and need not to carry out multiplying when realizing filtering, just carries out simple accumulating operation and gets final product.In multistage extraction system, the first order that speed is the highest realizes with cic filter, greatly reduces operand at present, has obtained best effect.
Prior art related to the present invention provides a kind of cic filter, it realizes structure chart as shown in Figure 1, comprise integral unit, comb unit and the extracting unit that between integral unit and comb unit, is provided with, integral unit is worked under the beat of master clock, and the work clock of comb unit is generated by the external world and provides.The frequency of input signal is f
s, the operating frequency of integral unit also is f
sBetween integral unit and comb unit, to extract, frequency reducing is f
s/ R, then the operating frequency of comb unit is f
s/ R.
There is following shortcoming in prior art:
Since in the prior art input data frequency must and master clock with frequently, therefore restricted to the input data frequency, but and can not dynamically control sample ratio changeable and sample phases, can not realize the variable of exponent number of sampling.
Summary of the invention
The purpose of this invention is to provide a kind of cascade integral comb filter,, avoided the limited problem of input data frequency that the input data frequency must cause with the restriction of master clock frequency together in the prior art by the present invention.
The objective of the invention is to be achieved through the following technical solutions:
The invention provides a kind of cascade integral comb filter, it comprises: integral unit, extracting unit and comb unit are respectively arranged with FPDP and synchronous signal port in wherein said described integral unit, extracting unit and the comb unit; Described synchronous signal port is used for synchronous signal transmission; Described FPDP is used for according to synchronizing signal input data, and by synchronizing signal the data of output is controlled.
Wherein, described integral unit comprises:
At least one-level integration subelement, and each grade integration subelement comprises first register and second register;
Described first register is used to store described synchronizing signal, exports described synchronizing signal and gives the subordinate unit, and offer second register with one-level;
Described second register is used to store the data of FPDP input, and controls dateout by described synchronizing signal and give the subordinate unit.
Wherein, described integral unit also comprises:
First selector and second selector;
Described first selector is used to receive the data of the integration subelement output of different progression, and selects the data and the output of corresponding progression according to configuration signal;
Described second selector is used to receive the synchronizing signal of the integration subelement output of corresponding described progression, and selects the synchronizing signal and the output of corresponding progression according to configuration signal.
Wherein, described extracting unit comprises:
The first fixed count device and first comparator;
The described first fixed count device is used for producing once according to synchronizing signal of every input, and counting adds up, and sends count value to described first comparator;
Described first comparator, be used to receive the count value of first fixed count device output, and itself and maximum flexibility extraction phase place that the user is provided with are compared, when the two is equal, the output control signal is used for the output of control data, and as the input of the synchronizing signal of comb unit.
Wherein, described extracting unit comprises:
Variable counter and counting terminal point register;
Described counting terminal point register is used for importing user configured counting terminal point according to user's indication and gives variable counter;
Described variable counter is used for according to described counting terminal point control count range, and exports corresponding count value according to the synchronizing signal of input.
Wherein, described extracting unit also comprises:
Second comparator and first extracts phase register;
Described first extracts phase register, is used to store user configured phase value, and exports described phase value and give described second comparator;
Described second comparator, the count value that is used for the output of the described phase value that will receive and described variable counter compares, and when the two was equal, the output control signal was used for the output of control data, and as the input of the synchronizing signal of described comb unit.
Wherein, described extracting unit comprises:
Second extracts phase register, the second fixed count device and the 3rd comparator;
Described second extracts phase register, is used for the extraction phase place of stored configuration, and the corresponding phase place that extracts of output is given described the 3rd comparator;
The described second fixed count device is used for carrying out adding up of count value according to the control of synchronizing signal, and count value is exported to described the 3rd comparator;
Described the 3rd comparator is used for the count value that will receive and compares with extracting phase place, and when the two was equal, the output control signal was used for the output of control data, and as the input of the synchronizing signal of comb unit.
Wherein, described comb unit comprises:
At least one-level pectination subelement, and each grade pectination subelement comprises the 3rd register, the 4th register and the 5th register;
Described the 3rd register be used for by synchronizing signal control the data that are input in it being carried out the differential processing, and the data after will handling sends the 5th register with one-level to;
Described the 4th register is used to store described synchronizing signal, and exports described synchronizing signal and give the subordinate unit, and offers the 5th register with one-level;
Described the 5th register is used for the data after the stores processor, and gives the subordinate unit by described synchronizing signal control dateout.
Wherein, described comb unit also comprises:
Third selector and the 4th selector;
Described third selector is used to receive the data of different progression pectination subelement outputs, and selects the data and the output of corresponding progression according to configuration signal;
Described the 4th selector is used to receive the synchronizing signal of the pectination subelement output of corresponding described progression, and selects the synchronizing signal and the output of corresponding progression according to configuration signal.
As seen from the above technical solution provided by the invention, cic filter described in the present invention comprises integral unit, extracting unit and comb unit, is respectively arranged with FPDP and synchronous signal port in wherein said integral unit, extracting unit and the comb unit; Described synchronous signal port is used for synchronous signal transmission; Described FPDP is used for according to synchronizing signal input data, and by synchronizing signal the data of output is controlled.By the present invention, can pass through the synchronous signal port synchronous signal transmission, and by of the input of described synchronizing signal control data from FPDP, solved the limited problem of input data frequency that the frequency that data are imported in the prior art must cause with master clock frequency together, and the present invention is easy to realize the stream treatment flow process, and can reduce processing delay.
In addition, but the present invention by can also dynamically controlling sample ratio changeable and/or variable sample phases at the variable counter of extracting unit setting and comparator etc., thereby be easy to the expansion of filter.
In addition, the present invention is by being arranged on the dynamic control variable-order of selector in integral unit or the comb unit.
Description of drawings
The implementation structure figure of the cic filter that provides in the prior art is provided Fig. 1;
Fig. 2 is the block diagram of first embodiment provided by the invention;
Input graph of a relation when Fig. 3 equals the clock cycle for cycle data among first embodiment provided by the invention;
Input graph of a relation when Fig. 4 is multiple times than the clock cycle for cycle data among first embodiment provided by the invention;
Fig. 5 is the implementation structure figure of integral unit among first embodiment provided by the invention;
Fig. 6 is that the extracting unit when realizing variable extraction rate, variable extraction phase place among first embodiment provided by the invention is realized building-block of logic
Fig. 7 is the realization building-block of logic of N level comb unit among first embodiment provided by the invention;
Fig. 8 is the realization building-block of logic that integral unit is realized the variable-order part among second embodiment provided by the invention;
Fig. 9 is a realization building-block of logic of realizing the variable-order part among second embodiment provided by the invention in the comb unit.
Embodiment
At cic filter of the present invention, first embodiment provided by the invention, its structure as shown in Figure 2, comprise integral unit, comb unit and the extracting unit that between integral unit and comb unit, is provided with, and FPDP that in described integral unit, extracting unit and comb unit, is provided with respectively and synchronous signal port; Described FPDP is used to import data data_in; Described synchronous signal port is used for input sync signal data_sync, and by described synchronizing signal the data of the FPDP input of integral unit, extracting unit and comb unit is controlled.
In first embodiment provided by the invention, the synchronizing signal data_sync during to control input data disposes, and is specific as follows:
Because synchronizing signal can be imported from the outside by synchronous signal port among the present invention, so described synchronizing signal can dispose neatly according to the clock cycle (cycle of system clock basic frequency): described synchronizing signal can equal the clock cycle, also can be multiple times than the clock cycle.
By the synchronizing signal control data during from the FPDP input and output, the cycle data of cic filter support can equal the clock cycle (that is to say, can be the same with prior art with system's master clock with frequently), also can be multiple times than the clock cycle.When cycle data equals the clock cycle, the relation of the input data data_in of synchronizing signal data_sync and FPDP as shown in Figure 3, when FPDP input data data_in is effective, data_sync is a high level always, and the data of sending in expression each clock cycle of this moment are all effective.
When cycle data is multiple times than the clock cycle, the relation of synchronizing signal data_sync and FPDP input data data_in as shown in Figure 4, synchronizing signal data_sync is a high level in first clock cycle when FPDP input data are effective, is low level in other clock cycle.
By as can be seen above-mentioned, if after data are sent into according to above-mentioned form, the calculating process of available synchronizing signal control data.The implementation structure of each unit among first embodiment is described respectively below.
One, integral unit
Based on the data of importing from FPDP according to above-mentioned form, in first embodiment provided by the invention, the implementation structure of integral unit is as shown in Figure 5: described integral unit comprises one-level integration subelement at least, and each grade integration subelement comprises that first register is that the reg2 among Fig. 5 and second register are the reg1 among Fig. 5; Described first register is used to store described synchronizing signal, exports described synchronizing signal and gives the subordinate unit, and offer second register; Described second register is used to store the data of FPDP input, and controls dateout by described synchronizing signal and give the subordinate unit.The concrete implication of the subordinate unit here is: if when described integral unit only comprises one-level integration subelement, described subordinate unit refers to described extracting unit; When described integral unit comprises multistage integration subelement, and described integration subelement is not when being not afterbody, and described subordinate unit refers to next stage integration subelement; When described integration subelement was afterbody integration subelement, described subordinate unit referred to extracting unit.The specific implementation process is as follows:
Synchronizing signal data_sync is as the effective index signal of FPDP input data data_in, when data_sync is high level, the first register reg2 in the integration subelement of the first order is carried out integration operation, and synchronizing signal data_sync is sent into the second register reg1 in the integration subelement of the first order.At next clock, the synchronizing signal intg1_sync that exports from first order integration subelement is a high level, and it enables the integration operation of second level integration subelement.And the like, finish the integration operation of N level, export integration data intgN and synchronizing signal intgN_sync at last.
Two, extracting unit
When only realizing fixed decimation rate and extract under the situation of phase place that described extracting unit comprises the first fixed count device and first comparator.
The described first fixed count device produces once to count according to synchronizing signal of every input and adds up, and sends count value to described first comparator; Described first comparator receives the count value of first fixed count device output, and the maximum flexibility that itself and user are provided with is extracted phase place compare, when the two was equal, the output control signal was used for the output of control data, and as the input of the synchronizing signal of described comb unit; When the two is unequal, do not export control signal.
Also can behind first comparator, be provided with and the unit in the above-mentioned extracting unit, its be used for first comparator relatively the output of the first fixed count device count value and extract the control signal of the two output when equating of phase place with maximum flexibility that the user is provided with, carry out and operational processes with the synchronizing signal that is input to described extracting unit, and result output is used for controlling the output of control data, and as the input of the synchronizing signal of described comb unit.
By as can be seen above-mentioned, when only realizing fixed decimation rate and extracting under the situation of phase place, counter is the fixed count device, effect along with the synchronizing signal of importing, each synchronizing signal produces one-accumulate, when count value reaches maximum, just extract the data that this moment, synchronizing signal was sent here, finish the fixing purpose that extracts.Extract phase place and also extract phase place for acquiescence.Under this kind mode, synchronizing signal is done the enable signal of counter.
When for realize extraction yield and extract phase place not simultaneously, the structure of described extracting unit is provided with counting terminal point register 1, variable counter 2, first extracts the phase register 3 and second comparator 4 as shown in Figure 6 in extracting unit.Described counting terminal point register 1 is imported user configured counting terminal point according to user's indication and is given variable counter 2, so that control the count range of described variable counter 2.Described variable counter 2 is controlled count range according to described counting terminal point, and according to the synchronizing signal intg_sync that is input to this variable counter 2, enables described variable counter 2 and begin counting, and count value is input to second comparator 4.Described first extracts the user configured phase value of phase register 3 storages, and exports described phase value and give described second comparator 4; The count value of described phase value that described second comparator 4 will receive and the output of described variable counter compares, and when the two is equal, the output control signal, then by with the synchronizing signal that described control signal and input are come in unit 5 carry out with, and the control signal that will obtain with processing be used for the output of control data, and as the input of the synchronizing signal of described comb unit; When the two is unequal, do not export control signal.
Also can not be provided with and unit 5 among Fig. 6, the count value of the described phase value that relatively receives of second comparator 4 and described variable counter output at this moment the two when equating, directly the control signal of output is used for the output of control data, and as the input of the synchronizing signal of described comb unit.
Describe the concrete disposition of extracting unit for example below in conjunction with Fig. 6:
For example, supposing to dispose extraction yield is 6, and variable phase is 3 filter.At first need to dispose variable counter 2 counting terminal points, and it is kept in the counting terminal point register 1, after the synchronizing signal that is transfused to convenient variable counter 2 enables, control its count range 0,1,2 according to the counting terminal point in the counting terminal point register 1,3,4, between 5.Secondly needing configuration to extract phase place is 3, and it is saved in the first extraction phase register 3.Extraction yield is 6, and variable phase is that the operation principle of 3 filter is as follows:
By being input to the synchronizing signal intg_sync in the variable counter 2, enable described variable counter 2 and begin counting, and control its count range 0 according to the counting terminal point in the counting terminal point register 1,1,2,3,4, between 5, and count value is input to second comparator 4, described second comparator 4 extracts the extraction phase value 3 that phase register 3 is input to comparator with described count value and first and compares, when count value reaches after 3, and the output control signal, and by the control signal exported and the synchronizing signal intg_sync of input being carried out and operation with unit 5, if the level of intg_sync is a high level, the comb_i data that then are input to comb unit equal the intg_o data, and the level that is input to the synchronizing signal intg_sync (i.e. comb_sync signal among the figure) of comb unit just equals level " 1 ".
Foregoing description the implementation structure of extracting unit when realizing variable extraction rate and variable extraction phase place, when extracting unit only can be realized the variable extraction rate, do not need to be provided with first in the described extracting unit and extract the phase register 3 and second comparator 4.This moment, the count value of variable counter 2 outputs was directly exported, and by exporting with unit 5 and described synchronizing signal intg_sync and processing back, be divided into two-way then, the one tunnel is input to the synchronous control signal of comb unit as comb unit, and another road is used for the output of control data.Certainly, the count value of variable counter 2 output also can directly be divided into two-way after the output without handling with unit 5, and one the tunnel is input to the synchronous control signal of comb unit as comb unit, and another road is used for the output of control data.
When extracting unit only can be realized the variable extraction phase place, described extracting unit comprised that second extracts phase register, the second fixed count device and the 3rd comparator.
Described second extracts phase register stores user configured extraction phase place, and the corresponding phase place that extracts of output is given described the 3rd comparator as required.The described second fixed count device carries out adding up of count value according to the control that is input to its synchronizing signal, and sends count value to described the 3rd comparator.Described the 3rd comparator compares the count value that receives with extracting phase place, when the two was equal, the output control signal was used for the output of control data, and as the input of the synchronizing signal of described comb unit; When the two is unequal, do not export control signal.With above-mentioned extracting unit, also can behind the 3rd comparator, be provided with and the unit, concrete processing procedure is no longer described.
By as can be seen above-mentioned, when extracting unit only can be realized the variable extraction phase place, need to be provided with configurable register in the described extracting unit and be used for storing the position that needs extract, can change its numerical value, fixed count device and comparator flexibly as required; Described fixed count device is under the effect of the synchronizing signal that input is come in, the count value of extraction yield is along with the rhythm of synchronizing signal adds up, when reaching the extraction phase value of register output, just take out the data that need and give comparator, realize variable extraction phase bit function like this.
Three, comb unit
The implementation structure of described comb unit as shown in Figure 7, as can be seen, the implementation structure of itself and integral part is similar, the data and the synchronizing signal of promptly preserving each grade constantly promote to next stage.Described comb unit comprises one-level pectination subelement at least, and each grade pectination subelement comprises the 3rd register, as the reg3 among Fig. 7, the 4th register, as reg2 among Fig. 7 and the 5th register, as the reg1 among Fig. 7.
Described the 3rd register carries out the differential processing by synchronizing signal control to the data that are input in it, and the data after will handling send the 5th register to.The described synchronizing signal of described the 4th register-stored, and export described synchronizing signal and give the subordinate unit, and offer the 5th register.Described the 5th register is used for the data after the stores processor, and gives the subordinate unit by described synchronizing signal control dateout.The implication of the subordinate unit here is: if described comb unit only comprises and during the pectination subelement, described subordinate unit refers to the signal handling equipment behind the described cic filter; When described comb unit comprises multistage pectination subelement, and when not handling to the end one-level pectination subelement, described subordinate unit refers to next stage pectination subelement; When described comb unit comprises multistage pectination subelement, and when handling afterbody pectination subelement, described subordinate unit refers to the signal handling equipment behind the described cic filter.
Concrete operation principle and integral unit are similar, here are not described in detail.
At cic filter of the present invention, the invention provides second embodiment, it has realized that on the basis of first embodiment filter order is variable.
Integral unit among second embodiment provided by the invention also is provided with the MUX selector on the basis of first embodiment, and data that will be corresponding with variable-order and synchronizing signal are guided to this MUX selector, and control the exponent number that this MUX selector is selected integration, thereby reach the purpose that exponent number can be joined by controlling configurable step_control signal.
To realize that 4 rank or 5 rank are that example describes, its variable-order is realized building-block of logic as shown in Figure 8 below:
First selector (as the mux1 among Fig. 8) and second selector (as the mux2 among Fig. 8) are set, and the data intg5 of the data intg4 of the 4th rank integration subelement output in the described implementation structure figure of Fig. 5 and the 5th rank integration subelement output guides on the interface of first selector, and the synchronizing signal intg5_sync of the correspondence of the synchronizing signal intg4_sync of the correspondence of the 4th rank integration subelement output and the 5th rank integration subelement output guided on the interface of second selector, when the user needs the data of the 4th rank integration subelement output, go out and the corresponding dateout of the 4th rank integration subelement by configurable step_control signal controlling selector Action Selection.Same when the user needs the data of correspondence of the 5th rank integration subelement output, go out the corresponding dateout of exporting with the 5th rank integration subelement by configurable step_control signal controlling selector Action Selection.The MUX selector be can control when needing the described step_control signal of configured in advance to be in what state among this embodiment and the data of the 4th rank integration subelement output or the data of the 5th rank integration subelement output selected.
When realizing variable-order, the structure of the comb unit of second embodiment provided by the invention is also to be provided with two selectors on the basis of above-mentioned structure as Fig. 7, be third selector (as the mux3 among Fig. 9) and the 4th selector (as the mux4 among Fig. 9), and data that will be corresponding with variable-order and synchronizing signal are guided to this two selectors respectively, and control the exponent number that this selector is selected pectination, thereby reach the purpose that exponent number can be joined by controlling configurable step_control signal.
To realize that 4 rank or 5 rank can be changed into example and describe, its variable-order is realized building-block of logic as shown in Figure 9, it has comprised two selectors, be third selector (as the mux3 among Fig. 9) and the 4th selector (as the mux4 among Fig. 9), and dateout comb_4 that respectively will be corresponding and be incorporated on the connecting interface of third selector wherein with the corresponding dateout comb_5 of the 5th rank pectination subelement with the 4th rank pectination subelement in the comb unit, synchronizing signal comb4_sync that will be corresponding and be incorporated on the connecting interface of the 4th selector with the corresponding synchronizing signal comb5_sync of the 5th rank pectination subelement with the 4th rank pectination subelement in the comb unit.
When the user needs the data of the 4th rank pectination subelement correspondence, go out input data corresponding output by configurable step_control signal controlling third selector Action Selection, and control the 4th selector Action Selection and go out the synchronizing signal output corresponding with the 4th rank pectination subelement with the 4th rank pectination subelement.Equally when the user needs the data of the 5th rank pectination subelement correspondence, go out and the corresponding input data of the 5th rank pectination subelement by configurable step_control signal controlling third selector Action Selection, and control the 4th selector Action Selection and go out the synchronizing signal corresponding output with the 5th rank pectination subelement.Can control the data that the MUX selector is selected the 4th rank pectination subelement or the 5th rank pectination subelement when needing the described step_control signal of configured in advance to be in what state among this embodiment.
The present invention also can adopt the independently work of module controls integral unit or the work of comb unit, to realize the purpose of control integration and control differential respectively.
By the specific embodiments of the invention described above as can be seen, among the present invention, can accomplish the flexible configuration of extraction yield, phase place, these major parameters of exponent number, thereby be easy to the expansion of filter by the present invention; And when adopting the flow chart of data processing of flowing water, it is few to handle time-delay; The present invention is simple in structure in addition, is easy to hardware and realizes.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (9)
1, a kind of cascade integral comb filter comprises integral unit, extracting unit and comb unit, it is characterized in that:
Be respectively arranged with FPDP and synchronous signal port in described integral unit, extracting unit and the comb unit;
Described synchronous signal port is used for synchronous signal transmission;
Described FPDP is used for according to synchronizing signal input data, and by synchronizing signal the data of output is controlled.
2, cascade integral comb filter according to claim 1 is characterized in that, described integral unit comprises:
At least one-level integration subelement, and each grade integration subelement comprises first register and second register;
Described first register is used to store described synchronizing signal, exports described synchronizing signal and gives the subordinate unit, and offer second register with one-level;
Described second register is used to store the data of FPDP input, and controls dateout by described synchronizing signal and give the subordinate unit.
3, cascade integral comb filter according to claim 2 is characterized in that, described integral unit also comprises:
First selector and second selector;
Described first selector is used to receive the data of the integration subelement output of different progression, and selects the data and the output of respective stages scalar product molecular cell according to configuration signal;
Described second selector is used to receive the synchronizing signal of the integration subelement output of corresponding described progression, and selects the synchronizing signal and the output of corresponding progression according to configuration signal.
4, according to claim 1,2 or 3 described cascade integral comb filters, it is characterized in that described extracting unit comprises:
The first fixed count device and first comparator;
The described first fixed count device, counting adds up to be used for producing once according to synchronizing signal of every input, and sends count value to described first comparator;
Described first comparator, be used to receive the count value of first fixed count device output, and itself and maximum flexibility extraction phase place that the user is provided with are compared, when the two is equal, the output control signal is used for the output of control data, and as the input of the synchronizing signal of comb unit.
5, according to claim 1,2 or 3 described cascade integral comb filters, it is characterized in that described extracting unit comprises:
Variable counter and counting terminal point register;
Described counting terminal point register is used for importing user configured counting terminal point according to user's indication and gives variable counter;
Described variable counter is used for according to described counting terminal point control count range, and exports corresponding count value according to the synchronizing signal of input.
6, cascade integral comb filter according to claim 5 is characterized in that, described extracting unit also comprises:
Second comparator and first extracts phase register;
Described first extracts phase register, is used to store user configured phase value, and exports described phase value and give described second comparator;
Described second comparator, the count value that is used for the output of the described phase value that will receive and described variable counter compares, and when the two was equal, the output control signal was used for the output of control data, and as the input of the synchronizing signal of described comb unit.
7, according to claim 1,2 or 3 described cascade integral comb filters, it is characterized in that described extracting unit comprises:
Second extracts phase register, the second fixed count device and the 3rd comparator;
Described second extracts phase register, is used for the extraction phase place of stored configuration, and the corresponding phase place that extracts of output is given described the 3rd comparator;
The described second fixed count device is used for carrying out adding up of count value according to the control of synchronizing signal, and count value is flowed to described the 3rd comparator;
Described the 3rd comparator is used for the count value that will receive and compares with extracting phase place, and when the two was equal, the output control signal was used for the output of control data, and as the input of the synchronizing signal of comb unit.
8, cascade integral comb filter according to claim 1 is characterized in that, described comb unit comprises:
At least one-level pectination subelement, and each grade pectination subelement comprises the 3rd register, the 4th register and the 5th register;
Described the 3rd register be used for by synchronizing signal control the data that are input in it being carried out the differential processing, and the data after will handling sends the 5th register with one-level to;
Described the 4th register is used to store described synchronizing signal, and exports described synchronizing signal and give the subordinate unit, and offers the 5th register with one-level;
Described the 5th register is used for the data after the stores processor, and gives the subordinate unit by described synchronizing signal control dateout.
9, cascade integral comb filter according to claim 8 is characterized in that, described comb unit also comprises:
Third selector and the 4th selector;
Described third selector is used to receive the data of different progression pectination subelement outputs, and selects the data and the output of corresponding progression according to configuration signal;
Described the 4th selector is used to receive the synchronizing signal of the pectination subelement output of corresponding described progression, and selects the synchronizing signal and the output of corresponding progression according to configuration signal.
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-
2006
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Non-Patent Citations (2)
| Title |
|---|
| 基于抽取滤波器多相分解的盲自适应符号同步算法. 孙建成，张太镒，刘枫，宫世子.电子与信息学报，第26卷第11期. 2004 |
| 基于抽取滤波器多相分解的盲自适应符号同步算法. 孙建成，张太镒，刘枫，宫世子.电子与信息学报，第26卷第11期. 2004 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109391246A (en) * | 2018-11-01 | 2019-02-26 | 哈尔滨工业大学 | A kind of configurable decimation filter of digital |
| CN109391246B (en) * | 2018-11-01 | 2021-12-24 | 哈尔滨工业大学 | Configurable digital decimation filter |
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| CN1984104A (en) | 2007-06-20 |
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