CN102882814A - Parameterized and modularized multi-channel digital down-conversion design platform and parameterized and modularized multi-channel digital down-conversion design method - Google Patents

Abstract

The invention provides a parameterized and modularized multi-channel digital down-conversion design platform and a parameterized and modularized multi-channel digital down-conversion design method, belonging to the digital signal processing field. A design platform is a parameterized and modularized multi-channel digital down-conversion design platform, which selects M channels from analog input signals of N channels to perform analog-digital conversion and performs the digital down-conversion treatment to output M paths of baseband digital signals. The invention is also a design method, wherein the design process is as follows: an input analog signal gating performs the analog-digital conversion and then the orthorhombic mixing; order H of a filter and a branch extracting multiple D area analyzed in real time; the signals after performing the orthorhombic mixing are respectively delayed, extracted and buffered; meanwhile, the selected filter coefficients are extracted and rearranged, so that the coefficient vector of every branch is obtained and buffered; the buffered data and coefficient are multiplied and added, and the results are periodically extracted and summed, then the output of the M path is obtained. The parameterized and modularized multi-channel digital down-conversion design platform has the advantages of usability, generality and flexibility; the platform is used for transforming multiple intermediate frequency sampling signals to a baseband signal; and meanwhile, the purpose of reducing the data speed rate is achieved.

Description

Parameterized module multi-channel digital down-conversion design platform and method

Technical field

The present invention relates to digital signal processing technique field, be mainly concerned with the specific implementation of multiphase filter structure, specifically a kind of parameterized module multi-channel digital down-conversion design platform and method can realize the Digital Down Convert design of parametrization, modularization, multichannel, variable filter exponent number.

Background technology

Utilize application-specific integrated circuit (ASIC) to realize that the technology of Digital Signal Processing has the advantages that cost is high, the rate of reusing is low and versatility is poor.Along with the fast development of signal processing technology, software radio becomes the key technology of current signal process field.The basic thought of software radio is take general a, standard, modular hardware platform as support, realizes various functions by software programming.Therefore the function of software implementation has reduced the hardware circuit design of function singleness, very flexible, has especially reduced the simulation link, has given full play to signal and has processed digitized advantage.Along with the raising of sampling rate, major issue is exactly that streaming rate after the sampling is very high, causes follow-up conversion speed not catch up with; If data throughput is too high, be difficult to requirement of real time, so being carried out the reduction of speed processing, the data flow behind the A/D just seems most important.A kind of feasible way adopts digital down-conversion technology exactly, high-speed data-flow is become the middle low rate data streams that can process in real time, again low speed data is done follow-up processing.Digital down-conversion technology is one of core technology of software radio reception, and general digital down converter also is applied to the fields such as various Wireless Telecom Equipments and radar and information-based household electrical appliances more and more widely, has importance extremely.

The digital quadrature down-conversion technique is that the if sampling signal is transformed to digital baseband, mainly contains two kinds of implementation methods: based on the Orthogonal Transformation Method of digital mixing with based on the digital quadrature transformation method of multiphase filter structure.

The former multiplies each other the two-way orthogonal signalling that if sampling output signal and local oscillator produce respectively to carry out digital mixing, and through low pass filter, the filtering high fdrequency component obtains required base band quadrature two-way signal with the signal after the mixing.The shortcoming of this down conversion method is for the Wideband Intermediate Frequency signal, needs higher sample rate, because the restriction of operating frequency is difficult to design the low pass filter of satisfying the demand.

The digital quadrature transformation method based on multiphase filter structure is utilized bandpass sample theory, determines the if sampling frequency according to carrier frequency and signal bandwidth, chooses respectively the sequence of parity after the sampling, by correcting filter, realizes exporting the two-way orthogonal signalling.According to heterogeneous structure and the equivalent transformation principle of FIR filter, can and extract and carry out simultaneously low-pass filtering, greatly reduce the requirement to filter process speed.The shortcoming of this down conversion method be the exponent number of branching filter and extract after data rate fix, in the time of in being used in different systems, change greatlyr, flexibility is relatively poor, versatility is not strong.

Summary of the invention

The object of the invention is to overcome the shortcoming such as above-mentioned digital down-conversion technology very flexible, versatility be not strong, Digital Down Convert design platform and the method for a kind of modularization, parametrization, multichannel, variable filter exponent number is provided.The present invention can receive the coefficient of configuration parameter and filter in real time, and the method that adopts submodule to build realizes Digital Down Convert, has the characteristics such as ease for use, versatility and flexibility.

The present invention is a kind of parameterized module multi-channel digital down-conversion design platform, include analog-to-digital conversion module and N passage Digital Down Converter Module, N road analog signal is given N Digital Down Converter Module through the digital signal of analog-to-digital conversion module output and is done the Digital Down Convert processing, and output N roadbed band digital signal; Parameterized module multi-channel digital down-conversion design platform of the present invention also includes N channel analog signal Shaping Module, the parameter receiver module, input channel gating module, N channel parameters input port, N road analog signal inputs to N channel analog signal Shaping Module, export the N road through the analog signal of shaping and give analog-to-digital conversion module, data-interface is given the parameter receiver module with parameter simultaneously, the parameter receiver module is given input channel gating module with the control signal of passage gating, N passage of input channel gating module output enables control signal to analog-to-digital conversion module, enable under the control of control signal at N passage, (M≤N) the road analog signal is done analog-to-digital conversion to analog-to-digital conversion module to the M that selects, output M railway digital signal is to M Digital Down Converter Module, the parameter receiver module is given the channel parameters on M road respectively the parameter input port of M Digital Down Converter Module simultaneously, under parameter control, do M railway digital down-converted, and output M roadbed band digital signal, every roadbed band signal is by I, the digital signal of Q two-way quadrature consists of; Described Digital Down Converter Module is the Digital Down Converter Module of parameterized module.

Digital down-conversion technology is one of core technology of software radio reception, simultaneously digital down-conversion technology also is applied to the fields such as various Wireless Telecom Equipments and radar and information-based household electrical appliances more and more widely, and shortcoming is very limited it in application but existing digital down-conversion technology very flexible, versatility be not strong etc.For digital down-conversion technology is more widely used, the present invention adopts parametrization and modular thought on the basis of existing digital down-conversion technology, make Digital Down Convert as a module, and this module is realized parametrization control.For realizing goal of the invention, the parameterized module Digital Down Convert design platform of variable-data-rate provided by the invention, variable filter exponent number, realize simultaneously the Digital Down Convert of the individual channel signal of N (N 〉=1), the Digital Down Converter Module of each passage can independently be used by parameter configuration.

The present invention processes to the Digital Down Convert of the M road signal selected that the design philosophy that all is based on above-mentioned parameter Modularized digital down-conversion realizes, by the parameter input to M Digital Down Converter Module, realize the Digital Down Convert processing of M road signal under each autoregressive parameter control, output M roadbed band digital signal, wherein every roadbed band signal comprises the signal of I, Q two-way quadrature.

Realization of the present invention also is: the Digital Down Converter Module of parameterized module, also increasing on the basis of original quadrature frequency mixing module, data delay cache module, filter coefficient module and multiply accumulating module has parameter input port, filter order and data rate control module, branching filter coefficient module.The parameter input port is given filter order and data rate control module with filter order control signal and speed control signal simultaneously, filter order and data rate control module simultaneously output filter exponent number and branch's extracting multiple signal and are delivered to branch's extracting multiple signal the input of data delay cache module to the branching filter coefficient module; Be provided with feedback command information channel and filter factor sendaisle between branching filter coefficient module and the parameter input port, select the branching filter coefficient that processing will be used according to parameter, the branching filter coefficient module is given the multiply accumulating module with each branching filter coefficient; The data of quadrature mixing are given the data delay cache module simultaneously, under the control of branch's extracting multiple signal, the data delay cache module carries out the delay under the parameter control to the data of mixing and extracts and process, and the data after extracting are done buffer memory, then exports to the multiply accumulating module; The multiply accumulating module is finished the multiply accumulating of data and filter coefficient and is exported the baseband digital signal of Digital Down Converter Module.

The realization of Digital Down Converter Module is to build realization by submodule, and each submodule connects by interconnected signal each other.The submodule of Digital Down Converter Module has: quadrature frequency mixing module, filter order and data rate control module, branching filter coefficient module, data delay cache module, multiply accumulating module.Simultaneously the present invention arranges the several data interface, can make things convenient for and external equipment between realize interactive type communication, the simultaneously design of data-interface has also embodied the present invention's extensibility on this basis, makes digital down-conversion technology use more flexibly and simply.

Realization of the present invention also is: the branching filter coefficient module in the parameterized module Digital Down Converter Module also is parametrization control.Be provided with feedback command information channel and filter factor sendaisle between branching filter coefficient module and the parameter input port, according to filter order and branch's extracting multiple signal filter coefficient selected.If the inner filter coefficient that presets can satisfy the demand of design, choice for use is preset at the filter coefficient among the buffer area A; If the filter order of determining does not mate with the filter order that presets, then send feedback signal to the parameter input port, and export to data-interface through the parameter receiver module, require data-interface to send the filter coefficient of corresponding exponent number, and the filter coefficient that will receive in real time is buffered among the buffer area B of branching filter coefficient module, gives the multiply accumulating module of each branch.

The present invention is not only a kind of parameterized module multi-channel digital down-conversion design platform or a kind of method for designing of parameterized module multi-channel digital down-conversion, its design cycle as shown in Figure 3, design process comprises:

A, N passage are that the multi-channel analog signal Shaping Module carries out shaping to N road analog signal to be processed, and the analog signal after the output N road shaping also sends to analog-to-digital conversion module.

B, parameter receiver module receive data interface mainly comprise parameter that Ethernet interface, PCI mouth, serial ports, USB mouth are sent here and required filter coefficient, from Digital Down Converter Module feedback information are sent to data-interface simultaneously, carry out interactive process.

C, input channel gating module are exported the control signal that enables of N passage, and N passage of passage gating control signal generation of sending here according to the parameter receiver module enables control signal, and this enables control signal as the input signal of following analog-to-digital conversion module.

D, analog-to-digital conversion module comprise N analog to digital converter, and the N that analog-to-digital conversion module provides in input channel gating module enables under the control of control signal, select the analog signal of M road shaping and carry out analog-to-digital conversion and export independently digital signal of M road.

Said process realizes that mainly the present invention parses passage and enables control signal by receiving in real time parameter to inputting gating and the analog-to-digital conversion of analog signal channel, and selecting needs passage to be processed to carry out follow-up Digital Down Convert processing.

E, parameterized digital down conversion module comprise M digital down-converted module, wherein each Digital Down Converter Module is to realize parametrization setting and control by input parameter, and the specific implementation process of Digital Down Converter Module comprises successively: quadrature mixing, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; Baseband digital signal after obtaining M railway digital down-converted after the Digital Down Converter Module.

Realization of the present invention also is: the parameter receiver module among the above process B, the reception of its parameter, form and be allocated as follows shown in:

The order that B1, receive data interface (data-interface can be Ethernet interface, PCI mouth, serial ports, USB mouth etc.) are sent here and corresponding filter coefficient send to data-interface with each Digital Down Converter Module feedack simultaneously.

B2, resolve the order that receives according to concrete communication protocol, obtain filter order control signal L and the speed control signal K of each passage, export to the parameter input port of the Digital Down Converter Module of respective channel, realize the parametrization control to each railway digital down-conversion.

B3, receiving filter coefficient, and filter coefficient carried out buffer memory, then export to the branching filter coefficient module of respective channel.

Realization of the present invention also is: the generation that enables control signal of input channel gating module among the above process C, and its production method is:

The control signal of the passage gating that C1, input channel gating module reception parameter receiver module are sent here, resolve control signal according to concrete interface communications protocol, what obtain N passage enables control signal Ctrl[N-1:0], Ctrl[N-1:0] initialization value be made as zero, and be defined as effectively high.

C2, Ctrl[0 wherein] be that the analog-to-digital conversion of passage 1 enables control, Ctrl[1] be that the analog-to-digital conversion of passage 2 enables control ..., Ctrl[N-1] and be that the analog-to-digital conversion of passage N enables control.

C3, as Ctrl[0] when being high, it is that the analog signal of selector channel 1 is carried out analog-to-digital conversion that expression passage 1 enables, as Ctrl[0] when low, it is that the analog signal of passage 1 is not carried out analog-to-digital conversion that expression passage 1 does not enable; As Ctrl[1] when being high, expression passage 2 enables, as Ctrl[1] when being low, expression passage 2 does not enable ..., the rest may be inferred selects a needed M passage with N M effective signal that enables in the control signal respectively.

Realization of the present invention also is: the parameterized digital down conversion module realizes that Digital Down Convert processes, and the Digital Down Convert on each road of the M railway digital signal selected is processed all can be used Digital Down Converter Module to carry out parametrization control by input parameter to realize Digital Down Convert.The design process of Digital Down Converter Module comprises: quadrature mixing, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; Below each process is elaborated:

Digital signal and orthogonal local oscillation sequence that analog-to-digital conversion is exported in E1, quadrature mixing

With Multiply each other sample rate f _sWith signal intermediate frequency f ₀Satisfy certain relation, make the local oscillator sequence that multiplies each other

With Satisfy:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{1,0,-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\},$ So will carry out 2 times of extractions to sampled signal first, obtain signal X (2n); After simultaneously sampled signal being postponed a clock cycle, carry out again 2 times of extractions and obtain signal X (2n+1), signal X (2n+1) has postponed a clock cycle than signal X (2n), adopt d type flip flop latch signal X (2n) to be about to X (2n) and postpone a clock cycle, sequence X (2n) and the X (2n+1) that extracts after aliging alternately multiplied each other respectively 1 and-1, obtain I (n), Q (n) two paths of signals of quadrature.

E2, according to input parameter L and K, determine filter order H and the extracting multiple D of branch.The exponent number of the low-pass filter coefficients commonly used that sets in advance has 32 rank, 64 rank, 128 rank, 144 rank, be pre-stored among the buffer area A, can be in the situation that the filter coefficient of selecting this to preset without external filter coefficient input, make this invention not exclusively depend on the filter coefficient of outside input, have independence in function; If the inner filter coefficient that presets satisfies the demand of design, but the filter coefficient that presets among the choice for use buffer area A, if the filter order H that determines does not mate with the filter order that presets, can export to data-interface to parameter receiver module feedback signal Cmd, require the filter coefficient on data-interface transmission H rank, and the H rank filter coefficient that will receive in real time is buffered among the buffer area B of branching filter coefficient module.

E3, controlling data delay according to the extracting multiple D of branch that obtains among the above process E2, is f in frequency _sUnder/2 the clock control, to I (n), Q (n) two paths of signals of the quadrature that produces among the E1 carry out respectively 0,1,2 ..., a D-1 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel D data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD, this moment, the data rate of each branch road was the same, I (n) among data rate and the E1, Q (n) two paths of data speed are identical, are f _s/ 2.

E4, controlling data pick-up according to the extracting multiple D of branch that obtains among the above process E2, is f in frequency _sUnder/2 the clock control, to data branch road Id1, Id2 after postponing among the E3 ..., IdD, Qd1, Qd2 ..., QdD carries out respectively D and doubly extracts namely and extract a number every D-1 data, data branch road after obtaining like this extracting be Ic1, Ic2 ..., IcD, Qc1, Qc2 ..., QcD, this moment each branch data rate be data rate among the E3 1/D doubly, be f _s/ 2D.

E5, be f in frequency _sUnder the clock control of/2D, with data branch road Ic1, Ic2 after the extraction that obtains among the E4 ..., IcD, Qc1, Qc2 ..., QcD write respectively separately data buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., among the RAMDQD.

E6, according to the filter order H that obtains among the above process E2 and the extracting multiple D of branch, produce switching signal Select by data selector, choose optimum filter coefficient, when Select is ' 0 ', choose the filter coefficient among the buffer area A, when Select is ' 1 ', choose the filter coefficient among the buffering area B.

E7, control the generation of branching filter coefficient according to the extracting multiple D of branch that obtains among the above process E2, at first with the coefficient C of the filter chosen among the above process E6 ₁, C ₂, C ₃..., C _HCarry out odd even and extract the filter coefficient C of even number ₂, C ₄..., C _HForm I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C _H-1Form Q path filter coefficient, I path filter coefficient is begun to carry out D from first coefficient doubly extract, obtain the filter coefficient C of I1 branch ₂,

,

I path filter coefficient is carried out D since second coefficient doubly extract, obtain the filter coefficient C of I2 branch ₄,

,

The rest may be inferred to the filter coefficient C of ID branch _2D,

,

I path filter coefficient resolves into the filter coefficient vector of D branch altogether, at last the filter coefficient vector inverted sequence of each branch is buffered in separately coefficient buffering area RAMCI1, RAMCI2 ..., among the RAMCID, be followed successively by by address order from small to large such as the coefficient of buffer memory among the RAMCI1

,

C ₂, the coefficient in other buffering area as can be known in like manner, the generation of Q road branching filter coefficient is identical with the treatment step on I road.

E8, branch's filtering are actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 2D branch need 2D multiply accumulating module, in frequency are

Clock control under, with above process E5 buffer area RAMDI1, RAMDI2, RAMDID, RAMDQ1, RAMDQ2, the I of buffer memory among the RAMDQD, the data reading of each branch of Q two-way, simultaneously with above process E7 buffer area RAMCI1, RAMCI2, RAMCID, RAMCQ1, RAMCQ2, the I of buffer memory among the RAMCQD, the filter coefficient of each branch of Q two-way is read, the data of reading among RAMDI1 and the RAMCI1 and coefficient are given respectively the input of a multiply accumulating module, carry out the filtering of I1 branch, the filtering of other each branch is identical, I, the filtering result of each branch of Q two-way is doutI1, doutI2, doutID, doutQ1, doutQ2, doutQD, this moment, the data rate of each branch was f _s/ 2D.

E9, be f in frequency _sUnder the clock control of/2D, with D the branch's filtering in I road among the E8 as a result doutI1, doutI2 ..., the doutID addition, the I road result who obtains Digital Down Convert exports doutI; With D the branch's filtering in Q road as a result doutQ1, doutQ2 ..., the doutQD addition, the Q road result who obtains Digital Down Convert exports doutQ.So far, finished the processing of parameterized module Digital Down Convert.

Processing through process A～F, control by external parameter, can select the analog signal of M passage of actual needs, the analog signal of M passage is exported the digital signal of M passage after analog-to-digital conversion, the Digital Down Converter Module of each passage receives parameter separately, the digital signal that receives is carried out Digital Down Convert process, output M roadbed band digital signal.Whole method for designing has realized the multichannel analog intermediate frequency signal is converted to the multichannel baseband digital signal, and has reached the requirement that reduces data rate.

To sum up, the inventive method takes full advantage of the design of parametrization and modularization idea realization Digital Down Convert, and compared with prior art, the present invention has following advantage:

1, the present invention is based on the changeable channel Digital Signal Processing, by input channel gating module, passage is set enables control signal, selecting needs channel signal to be processed to carry out subsequent treatment, and the channel signal that need not process will not processed.Like this enable to arrange has advantages of changeable channel, can reach the purpose of effective saving power consumption simultaneously.

2, the present invention is based on parametrization, modular thinking, each railway digital down conversion module can realize the parametrization independent process to every railway digital signal neatly by receiving in real time parameter separately; Simultaneously, in certain scope, the parameter of being given by the outside is controlled the change of filter order and data rate, makes it be applicable to the system that need not require, and range of application is broader.Integrality, flexibility and ease for use with parameterized module design.

3, data-interface of the present invention can be Ethernet interface, PCI mouth, serial ports, USB mouth etc., data-interface sends order and corresponding filter coefficient to the parameter receiver module, simultaneously also the information of Digital Down Converter Module of the present invention can be fed back to data-interface, carry out interactive process, the selection of this multiple interfaces and interactive process have increased simplicity, ease for use and the versatility of system.

4, the filter coefficient of in real time receive data interface transmission of the present invention, the filter coefficient that also can select inside to preset has realized that filter factor is moving variable, moves back the generalization control that can keep, has very strong versatility and practicality.

Description of drawings

Fig. 1 is the modularization block diagram of design platform of the present invention, also is the formation block diagram of method for designing of the present invention;

Fig. 2 is the formation block diagram of single passage Digital Down Converter Module in the M passage Digital Down Converter Module of the present invention;

Fig. 3 is the flow chart of single passage Digital Down Converter Module;

Fig. 4 is the flow chart of the quadrature frequency mixing module of single passage Digital Down Converter Module;

Fig. 5 is the filter order of single passage Digital Down Converter Module and the flow chart of data rate control module;

Fig. 6 is the symmetric form FIR filter block diagram of single passage Digital Down Converter Module;

Fig. 7 is the formation block diagram of the I circuit-switched data delay buffer module of single passage Digital Down Converter Module:

Fig. 8 is the formation block diagram of the branching filter coefficient module of single passage Digital Down Converter Module;

Fig. 9 is the formation block diagram of multiply accumulating module of the I road branch filtering of single passage Digital Down Converter Module;

Figure 10 is the time-sharing multiplex sequential chart of multiply accumulating module of the I road branch filtering of single passage Digital Down Converter Module.

Embodiment

Following embodiment is used for explanation the present invention, but is not used for limiting the scope of application of the present invention.

Embodiment 1

The present invention is a kind of parameterized module multi-channel digital down-conversion design platform, include analog-to-digital conversion module and N passage Digital Down Converter Module, N road analog signal is given N Digital Down Converter Module through the digital signal of analog-to-digital conversion module output and is done the Digital Down Convert processing, and output N roadbed band digital signal; Referring to Fig. 1, parameterized module multi-channel digital down-conversion design platform of the present invention also includes N channel analog signal Shaping Module, the parameter receiver module, input channel gating module, N channel parameters input port, N road analog signal inputs to N channel analog signal Shaping Module, export the N road through the analog signal of shaping and give analog-to-digital conversion module, data-interface is given the parameter receiver module with parameter simultaneously, the parameter receiver module is given input channel gating module with the order of passage gating, N passage of input channel gating module output enables control signal to analog-to-digital conversion module, enable under the control of control signal at N passage, analog-to-digital conversion module is done analog-to-digital conversion to the M road analog signal of selecting, output M railway digital signal is to M Digital Down Converter Module, the parameter receiver module is given the channel parameters on M road respectively the parameter input port of M Digital Down Converter Module simultaneously, under parameter control, do M railway digital down-converted, and output M roadbed band digital signal.Digital Down Converter Module of the present invention is the Digital Down Converter Module of parameterized module.

Referring to Fig. 2, the Digital Down Converter Module of parameterized module of the present invention is in original quadrature frequency mixing module, the data delay cache module, also increase on the basis of filter coefficient module and multiply accumulating module the parameter input port is arranged, filter order and data rate control module, the branching filter coefficient module, the parameter input port is given filter order and data rate control module with filter order control signal and speed control signal simultaneously, filter order and data rate control module while output filter exponent number and branch's extracting multiple signal are to the branching filter coefficient module, and branch's extracting multiple signal is delivered to the input of data delay cache module, be provided with feedback command information channel and filter coefficient sendaisle between branching filter coefficient module and the parameter input port, select the branching filter coefficient of actual needs according to parameter, the branching filter coefficient module is given the multiply accumulating module with each branching filter coefficient; The data of quadrature mixing are given the data delay cache module simultaneously, under the control of branch's extracting multiple signal, the data delay cache module carries out the delay under the parameter control to the data of mixing and extracts and process, data after processing are done buffer memory, then export to the multiply accumulating module, the multiply accumulating module is finished the multiply accumulating of data and filter coefficient and is exported the baseband digital signal of Digital Down Convert.

Branching filter coefficient module in the parameterized module Digital Down Converter Module of the present invention also is parametrization control, be provided with feedback command information channel and filter coefficient sendaisle between branching filter coefficient module and the parameter input port, according to filter order and branch's extracting multiple signal filter coefficient is selected, if the inner filter coefficient that presets can satisfy the demand of design, choice for use is preset at the filter coefficient among the buffer area A, if the filter order of determining does not mate with the filter order that presets, send feedback signal to the parameter input port, and export to data-interface through the parameter receiver module, require data-interface to send the filter coefficient on corresponding rank, and the filter coefficient that will receive in real time is buffered among the buffer area B of branching filter coefficient module, gives the multiply accumulating module of each branch.

Embodiment 2

Parameterized module multi-channel digital down-conversion design platform is with embodiment 1.

The present invention or a kind of parameterized module multi-channel digital down-conversion method for designing, method for designing are to move at above-mentioned parameterized module multi-channel digital down-conversion design platform, and referring to Fig. 1, design process comprises:

A, N passage are that the multi-channel analog signal Shaping Module carries out shaping to N road analog signal, and the analog signal after the output N shaping;

B, parameter receiver module receive data interface mainly comprise Ethernet interface, PCI mouth, serial ports, USB mouth, and the parameter of sending here and required filter coefficient can feed back to data-interface with the information of submodule among the present invention simultaneously, carry out interactive process.

The reception of its parameter, form and be allocated as follows shown in:

The order that B1, receive data interface (data-interface can be Ethernet interface, PCI mouth, serial ports, USB mouth etc.) are sent here and corresponding filter coefficient, simultaneously also the information of submodule among the present invention can be fed back to data-interface, carry out interactive process, the selection of multiple interfaces has increased simplicity, ease for use and the versatility of system.

B2, resolve the order that receives according to concrete communication protocol, obtain filter order control signal L and the speed control signal K of each passage, export to the parameter input port of the Digital Down Converter Module of respective channel, realize the parametrization control to each railway digital down-conversion.

B3, receiving filter coefficient, and filter coefficient carried out buffer memory, then export to the branching filter coefficient module of respective channel.

C, input channel gating module are exported the control signal that enables of N passage, and N passage of passage gating control signal generation of sending here according to the parameter receiver module enables control signal, and this enables control signal as the input signal of following analog-to-digital conversion module; Select M input channel gating module by N, gating is set enables, select the passage that need to process and carry out subsequent treatment, and the port number that need not process will not enable, and can effectively reduce the power consumption of system.

The generation that enables control signal of input channel gating module, its production method is:

The control signal of the passage gating that C1, input channel gating module reception parameter receiver module are sent here, resolve control signal according to concrete interface communications protocol, what obtain N passage enables control signal Ctrl[N-1:0], Ctrl[N-1:0] initialization value be made as zero, and be defined as effectively high.

C2, Ctrl[0 wherein] be that the analog-to-digital conversion of passage 1 enables control, Ctrl[1] be that the analog-to-digital conversion of passage 2 enables control ..., Ctrl[N-1] and be that the analog-to-digital conversion of passage N enables control.

C3, as Ctrl[0] when being high, it is that the analog signal of selector channel 1 is carried out analog-to-digital conversion that expression passage 1 enables, as Ctrl[0] when low, it is that the analog signal of passage 1 is not carried out analog-to-digital conversion that expression passage 1 does not enable; As Ctrl[1] when being high, expression passage 2 enables, as Ctrl[1] when being low, expression passage 2 does not enable ..., the rest may be inferred selects a needed M passage with N M effective signal that enables in the control signal respectively.

D, analog-to-digital conversion module comprise N analog to digital converter, and the N that analog-to-digital conversion module provides in input channel gating module enables under the control of control signal, select the analog signal of M road shaping and carry out analog-to-digital conversion and export independently digital signal of M road.

E, parameterized digital down conversion module comprise M digital down-converted module, wherein each Digital Down Converter Module is to realize parametrization control by input parameter, and Digital Down Converter Module realizes that the specific implementation process of Digital Down Convert comprises successively: quadrature mixing, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating.

F, the analog signal of N passage of input distinguished the operation of implementation A～E, obtain the baseband digital signal after the M railway digital down-converted.

In the realization to the parameterized digital down-conversion of the M railway digital signal selected, the Digital Down Convert on each road all can be used Digital Down Converter Module to carry out parametrization control by input parameter and realize Digital Down Convert.The parametrization of Digital Down Convert, modularized design, make we by the outside to parameter in certain scope, carry out the change of filter order and data rate, have integrality and the reusability of parameterized module, make its application broader.Design process comprises: quadrature mixing, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; Below each process is elaborated:

Digital signal and the orthogonal local oscillation sequence of E1, analog-to-digital conversion output

With

Multiply each other sample rate f _sWith signal intermediate frequency f ₀Satisfy certain relation, make the local oscillator sequence that multiplies each other

With

Satisfy:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{1,0,-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\},$

Referring to Fig. 4, first sampled signal is carried out 2 times of extractions, obtain signal X (2n); After simultaneously sampled signal being postponed a clock cycle, carry out again 2 times of extractions and obtain signal X (2n+1), signal X (2n+1) has postponed a clock cycle than signal X (2n), adopt d type flip flop latch signal X (2n) to be about to X (2n) and postpone a clock cycle, sequence X (2n) and the X (2n+1) that extracts after aliging alternately multiplied each other respectively 1 and-1, obtain respectively I (n), Q (n) two paths of signals of quadrature.

E2, referring to Fig. 5, according to input parameter L and K, determine filter order H and the extracting multiple D of branch, the exponent number of the low-pass filter coefficients commonly used that sets in advance has 32 rank, 64 rank, 128 rank, 144 rank, be pre-stored among the buffer area A, can make this invention not exclusively depend on the outside filter coefficient of inputting in the situation that select this filter coefficient that presets without external filter coefficient input, have independence in function.

If the inner filter coefficient that presets satisfies the demand of design, but the filter coefficient that presets among the choice for use buffer area A, if the filter order H that determines does not mate with the filter order that presets, can export to data-interface to parameter receiver module feedback signal Cmd, require the filter coefficient on data-interface transmission H rank, and the H rank filter coefficient that will receive in real time is buffered among the buffer area B of branching filter coefficient module; This both coefficients of in real time receive data interface transmission of filter factor, the filter coefficient design that also can select inside to preset makes filter factor moving variable, moves back the generalization control that can keep, has very strong versatility, practicality.

E3, referring to Fig. 7, control data delay according to the extracting multiple D of branch that obtains among the E2, be f in frequency _sUnder/2 the clock control, to I (n), Q (n) two paths of signals of the quadrature that produces among the E1 carry out respectively 0,1,2 ..., a D-1 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel D data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD, this moment, the data rate of each branch road was the same, I (n) among data rate and the E1, Q (n) two paths of data speed are identical, are f _s/ 2.

E4, controlling data pick-up according to the extracting multiple D of branch that obtains among the E2, is f in frequency _sUnder/2 the clock control, to data branch road Id1, Id2 after postponing among the E3 ..., IdD, Qd1, Qd2 ..., QdD carries out respectively D and doubly extracts namely and extract a number every D-1 data, the data branch road after obtaining like this extracting be Ic1, Ic2 ..., IcD, Qc1, Qc2 ..., QcD.This moment each branch data rate be data rate among the E3 1/D doubly, be f _s/ 2D.

E5, referring to Fig. 6, be f in frequency _sUnder the clock control of/2D, with data branch road Ic1, Ic2 after the extraction that obtains among the E4 ..., IcD, Qc1, Qc2 ..., QcD write respectively separately data buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., among the RAMDQD.

E6, referring to Fig. 8, according to the filter order H that obtains among the E2 and the extracting multiple D of branch, produce switching signal Select by data selector, choose optimum filter coefficient.When Select is ' 0 ', choose the filter coefficient among the buffer area A, when Select is ' 1 ', choose the filter coefficient among the buffering area B.

E7, control the generation of branching filter coefficient according to the extracting multiple D of branch that obtains among the E2.At first with the coefficient C of the filter chosen among the E6 ₁, C ₂, C ₃..., C _HCarry out odd even and extract the filter coefficient C of even number ₂, C ₄..., C _HForm I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C _H-1Form Q path filter coefficient, I path filter coefficient is begun to carry out D from first coefficient doubly extract, obtain the filter coefficient C of I1 branch ₂,

,

I path filter coefficient is carried out D since second coefficient doubly extract, obtain the filter coefficient C of I2 branch ₄,

,

The rest may be inferred to the filter coefficient C of ID branch _2D,

,

I path filter coefficient resolves into the filter coefficient vector of D branch altogether, at last the filter coefficient vector inverted sequence of each branch is buffered in separately coefficient buffering area RAMCI1, RAMCI2 ..., among the RAMCID, be followed successively by by address order from small to large such as the coefficient of buffer memory among the RAMCI1

,

C ₂, the coefficient in other buffering area as can be known in like manner, the generation of Q road branching filter coefficient is identical with the treatment step on I road.

E8, branch's filtering are actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 2D branch need 2D multiply accumulating module.Referring to Fig. 9, in frequency be

Clock control under, with E5 buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., the I, the data reading of each branch of Q two-way of buffer memory among the RAMDQD, simultaneously with E7 buffer area RAMCI1, RAMCI2 ..., RAMCID, RAMCQ1, RAMCQ2 ..., the I, the filter coefficient of each branch of Q two-way of buffer memory reads among the RAMCQD, the data of reading among RAMDI1 and the RAMCI1 and coefficient are given respectively the input of a multiply accumulating module, carry out the filtering of I1 branch.The filtering of other each branch is identical, the filtering result of I, each branch of Q two-way be doutI1, doutI2 ..., doutID, doutQ1, doutQ2 ..., doutQD, this moment each branch data rate be f _s/ 2D.

E9, be f in frequency _sUnder the clock control of/2D, with D the branch's filtering in I road among the E8 as a result doutI1, doutI2 ..., the doutID addition, the I road result who obtains Digital Down Convert exports doutI; With D the branch's filtering in Q road as a result doutQ1, doutQ2 ..., the doutQD addition, the Q road result who obtains Digital Down Convert exports doutQ.So far, finished the processing of parameterized module Digital Down Convert.

Embodiment 3

Parameterized module multi-channel digital down-conversion design platform and parameterized module multi-channel digital down-conversion method for designing are with embodiment 1-2.

For making purpose of the present invention, advantage and technical method clearer, the below is described in detail the modules in the embodiment of the present invention as the basis take modularization idea on programmable logic device Xilinx Virtex5 Series FPGA.

1, N (N 〉=1) channel analog signal Shaping Module.Each passage comprises an analog signal shaping circuit, and the analog signal shaping circuit is exported to analog-to-digital conversion module after being used for the analog signal of N passage of input adjusted.

2, input channel gating module.This module is exported the control signal that enables of N passage, is used for N separate analog channel selected to select M passage.This enables control signal as the input of analog-to-digital conversion module, only has the effective respective channel analog signal of enable signal selected.

3, analog-to-digital conversion module.This module comprises N analog to digital converter, and (the individual analog signal that effectively enables after control signal is come gating M road shaping of M≤N) is carried out independently digital signal of analog-to-digital conversion output M road according to the M that provides in the input channel gating module.

4, parameter receiver module.The parameter receiver module is the interface that carries out data communication with the outside, is used for receiving the order that sends such as data-interfaces such as Ethernet interface, PCI mouth, serial ports, USB mouths and the filter coefficient of needs.This module also can feed back to data-interface with the information of submodule among the present invention simultaneously, carries out interactive process.This module obtains filter order control signal L and the speed control signal K of each passage mainly according to the command analysis of concrete communication protocol with reception, exports to the Digital Down Converter Module of respective channel; The filter coefficient of each passage that will receive simultaneously carries out buffer memory, also Digital Down Converter Module can be sent here feedback command send to outside port.

5, M channel parameters Modularized digital down conversion module.This module is nucleus module of the present invention, comprises M digital down-converted module, wherein the digital lower side frequency of each passage be by to M Digital Down Converter Module respectively input parameter realize parametrization setting and control, independently process.Digital Down Converter Module comprises each submodule, wherein has: quadrature frequency mixing module, filter order and data rate control module, branching filter coefficient module, data delay cache module and multiply accumulating module.Below the submodule of Digital Down Converter Module is described, concrete block diagram is seen Fig. 2.

6, quadrature frequency mixing module.The theory diagram of quadrature mixing as shown in Figure 4.Based on the thought of modularized processing, the input of this module is the digital signal of analog-to-digital conversion module output, and output is I, the Q two-way baseband signal of quadrature after the mixing.This module is carried out mixing to the digital signal of A/D sampling output, sampled signal is carried out odd even extracts, the two paths of signals that obtains respectively with the orthogonal local oscillation sequence

With

Multiply each other the baseband signal of output two-way quadrature.

7, filter order and data rate control module.Filter order control signal L and speed control signal K that this module is sent here according to the parameter receiver module, carrying out the optimization of filter order selects, obtain the total exponent number H and the extracting multiple D of branch that need when pre-filter, exponent number H and the extracting multiple D of branch are exported to other submodule through buffer memory.Here filter order control signal L is defined as the outside filter order that sends; Speed control signal K is defined as the multiple that extracts according to the actual conditions needs after the mixing of sampled signal quadrature; H is defined as the exponent number of actually determined filter; The extracting multiple D of branch is defined as the front extracting multiple that need to carry out each branch data of each branching filter filtering.

8, data delay cache module.According to the extracting multiple D of branch that process 7 obtains, this module registration hands over that I, the Q two paths of data after the mixing postpones respectively, extraction and caching process.Following process is all take the I road as example, as shown in Figure 7, first to data postpone successively 1,2 ..., a D-1 unit, altogether obtain the parallel data in D road, again every circuit-switched data being carried out respectively D doubly extracts, the D circuit-switched data obtains D tap altogether, and the data of D tap are buffered in respectively in D the buffer area, exports to the data input pin of multiply accumulating module in the process 10.

9, branching filter coefficient module.This module is buffered in the filter coefficient that receives in the independent buffer area.The total exponent number H of multiphase filter and the extracting multiple D of branch that obtain according to process 7, this module can be selected the filter coefficient of corresponding exponent number, and according to the multiphase filtering principle filter coefficient is extracted and resets, the coefficient vector that obtains D tap is the coefficient vector of D branching filter, exports to respectively the coefficient input of multiply accumulating module in the process 10 behind the buffer memory.

10, multiply accumulating module.Through the processing of process 1～9, this module realizes is that the final step of multiphase filter is multiply accumulating.After the coefficient of each branching filter of the data of each branch of process 8 output and process 9 outputs carried out multiply accumulating respectively, obtain the output of D the branching filter on I road, again with the output of this D branching filter by the control signal output of periodically suing for peace, finally obtain the I road output of Digital Down Convert.The processing procedure on Q road is similar.

Embodiment 4

Parameterized module multi-channel digital down-conversion design platform and parameterized module multi-channel digital down-conversion method for designing are with embodiment 1-2-3.

For making purpose of the present invention, advantage and technical method clearer, the present invention will be described in more detail by corresponding parameter is set.Host computer by the PCI mouth to the parameter that this platform sends is in this example: N=16, and M=8, filter order H=144, the extracting multiple D=6 of branch, the parameter that each passage is processed in this example is duplicate.The below is described in further detail embodiment of the present invention on programmable logic device Xilinx Virtex5 Series FPGA.

Realize that step of the present invention is as follows:

Step 1, the analog signal shaping.

N=16 in this example after the analog input signal of 16 passages of 16 channel analog signal Shaping Module receptions is adjusted, exports to analog-to-digital conversion module again.

Step 2 parses the control signal that enables of 16 passages.

In this example, data-interface is pci interface, and host computer sends parameter to the parameter receiver module by pci interface.The parameter receiver module parses the order of passage gating according to the communication protocol of pci interface, what obtain 16 passages enables control signal Ctrl[15:0].In this example, the control signal that enables that parses is CtrI[15:0]=0000000011111111.

Step 3, multichannel is selected.

To enable control signal Ctrl[15:0 in the step 2] send to analog-to-digital conversion module, the analog signal of control respective channel is carried out analog-to-digital conversion.In this example, the analog signal of selector channel 1～8 is carried out analog-to-digital conversion, obtains 8 railway digital signals.And passage 9～16 does not enable namely not carry out analog-to-digital conversion.

Step 4 parses the control parameter of 8 passages.

The parameter receiver module receives order and corresponding filter coefficient that host computer sends in real time according to the communication protocol of pci interface.From the order parse 8 passages filter order control signal L1, L2 ..., L8 and speed control signal K1, K2 ..., K8.Give the parameter input port of passage 1 Digital Down Converter Module with L1 and K1, give the parameter input port of passage 2 Digital Down Converter Module with L2 and K2 ..., give the parameter input of passage 8 Digital Down Converter Module with L8 and K8; The filter coefficient of 8 passages sends to respectively 8 Digital Down Converter Module simultaneously, and is buffered in the buffer area of branching filter coefficient module.

Step 5, the realization of parameterized module Digital Down Convert.

The structure of the parameterized digital down conversion module of 8 passages is identical, different is that control parameter and the filter coefficient inputted are distinguished to some extent, the parameter L 1 that produces by step 4, L2 ..., L8 and K1, K2 ..., K8 can realize the parametrization control on each road.Below the step of passage 1 parameterized digital down conversion module of the present invention is described in detail:

1, signal in orthogonal mixing.

In this example, the intermediate frequency f of analog signal ₀=210M, bandwidth B=5M.According to bandpass sample theory

N gets the integer that satisfies fs 〉=2B, the sample rate f s=120M of the analog to digital converter in this example.The local oscillator sequence

With Satisfy following relation:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{1,0,-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\}.$

Based on above-mentioned condition, be under the control of 120M clock in frequency, from first efficient clock along, at first sampled signal is carried out 2 times of extractions, obtain signal X (2n); After simultaneously sampled signal being postponed a clock cycle, carry out again 2 times of extractions and obtain signal X (2n+1).Signal X (2n+1) has postponed a clock cycle than signal X (2n), X (2n) is postponed a clock cycle, then at efficient clock when arriving, the sequence X (2n) and the X (2n+1) that extract after aliging are alternately multiplied each other respectively 1 and-1, obtain I (n), Q (n) two paths of signals of quadrature.The data rate of this moment has been reduced to half of sample rate, is 60M.

2, parse filter order H and the extracting multiple D of branch of passage 1.

In this example, parameter L 1=144 and K1=12 according to host computer sends determine filter order H=144, the extracting multiple D=6 of branch.The filter order H=144 that determines in this example, do not mate with the filter order that presets, to parameter receiver module feedback signal Cmd, send to host computer by pci interface, host computer receives this feedback signal, and the filter coefficient that sends the H=144 rank by pci interface is buffered among the buffer area B of branching filter coefficient module.

3, data delay.

Control data delay according to the extracting multiple D=6 of branch that obtains.Be under the clock control of 60M in frequency, to I (n), Q (n) two paths of signals of the quadrature that produces in 1 carry out respectively 0,1,2 ..., 5 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel 6 data branch road Id1, Id2 ..., Id6, Qd1, Qd2 ..., Qd6, this moment, the data rate of each branch road was the same, I in the data rate and 1 (n), Q (n) two paths of data speed are identical, are 60M.

4, branch data extracts.

Control data pick-up according to the extracting multiple D=6 of branch that obtains.Be under the clock control of 60M in frequency, to data branch road Id1, Id2 after postponing in 3 ..., Id6, Qd1, Qd2 ..., Qd6 carries out respectively 6 times of extractions and namely extracts a number every 5 data, data branch road after obtaining like this extracting be Ic1, Ic2 ..., Ic6, Qc1, Qc2 ..., Qc6.This moment, the data rate of each branch was 1/6 times of data rate in 3, was 10M.

5, branch data buffer memory.

Be under the clock control of 10M in frequency, data branch road Ic1, Ic2 after the extraction that extraction obtains according to branch data ..., Ic6, Qc1, Qc2 ..., Qc6 write respectively separately data buffer area RAMDI1, RAMDI2 ..., RAMDI6, RAMDQ1, RAMDQ2 ..., among the RAMDQ6.

6, the selection of filter coefficient.

According to the filter order H=144 that obtains and the extracting multiple D=6 of branch, produce switching signal Select=1 by data selector, that chooses that optimum filter coefficient namely receives in real time is buffered in filter coefficient among the buffer area B.

7, the generation of branching filter coefficient.

Control the generation of branching filter coefficient according to the extracting multiple D=6 of branch that obtains.At first with the coefficient C of the filter chosen ₁, C ₂, C ₃..., C ₁₄₄Carry out odd even and extract the filter coefficient C of even number ₂, C ₄..., C ₁₄₄Form I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C ₁₄₃Form Q path filter coefficient.Then I path filter coefficient is begun to carry out D=6 from first coefficient and doubly extract, obtain the filter coefficient C of I1 branch ₂, C ₁₄, C ₂₆..., C ₁₃₄I path filter coefficient is carried out D=6 since second coefficient doubly extract, obtain the filter coefficient C of I2 branch ₄, C ₁₆, C ₂₈..., C ₁₃₆The rest may be inferred to the filter coefficient C of I6 branch ₁₂, C ₂₄, C ₃₆..., C ₁₄₄I path filter coefficient resolves into the filter coefficient vector of 6 branches altogether.At last the filter coefficient vector inverted sequence of each branch is buffered in separately coefficient buffering area RAMCI1, RAMCI2 ..., among the RAMCI6, be followed successively by C such as the coefficient of buffer memory among the RAMCI1 by address order from small to large ₁₃₄..., C ₂₆, C ₁₄, C ₂, the coefficient in other buffering area as can be known in like manner.

The generation of Q road branching filter coefficient is identical with the treatment step on I road.

8, branch's filtering is processed.

Branch's filtering is actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 12 branches need 12 multiply accumulating modules, also just needs 12 adder and multiplier DSP48E.Be under the clock control of 120M in frequency, with buffer area RAMDI1, RAMDI2 ..., RAMDI6, RAMDQ1, RAMDQ2 ..., the I, the data reading of each branch of Q two-way of buffer memory among the RAMDQ6, simultaneously with buffer area RAMCI1, RAMCI2 ..., RAMCI6, RAMCQ1, RAMCQ2 ..., the I, the filter coefficient of each branch of Q two-way of buffer memory reads among the RAMCQ6.The data of reading among RAMDI1 and the RAMCI1 and coefficient are given respectively A, the B input of a DSP48E, and the operating frequency of DSP48E is identical with data rate here, is 120M, and the mode of operation that DSP48E is set is the multiply accumulating pattern.Referring to Figure 10, utilize the thought of DSP48E time-sharing multiplex, realized the filtering of I1 branch; The filtering of other each branch is identical.

Be under the clock control of 120M in frequency, extract take 12 as the Output rusults of count cycle to DSP48E, the filtering that can obtain I, each branch of Q two-way as a result doutI1, doutI2 ..., doutI6, doutQ1, doutQ2 ..., doutQ6, this moment each branch data rate be 10M.

9, passage 1 Digital Down Convert I, Q two-way result output

Be under the clock control of 10M in frequency, with 6 branch's filtering in I road of obtaining as a result doutI1, doutI2 ..., the doutI6 addition, the I road result who obtains Digital Down Convert exports doutI; With 6 the branch's filtering in Q road as a result doutQ1, doutQ2 ..., the doutQ6 addition, the Q road result who obtains Digital Down Convert exports doutQ.

Finished the parameterized digital down-converted of passage 1 by step 1～9, the processing procedure of the processing procedure of passage 2～8 and passage 1 is similar, so far finishes the Digital Down Convert of 1～8 passage and processes, and gets 8 railway digital baseband signals.

Above-mentioned implementation method is the better embodiment of the present invention; but embodiments of the present invention are not subjected to the restriction of above-mentioned embodiment; other is any is not running counter to change, replacement, combination, simplification or the repacking of making under Spirit Essence of the present invention, technical scheme and the principle; all should be considered as the substitute mode of equivalence, be included within protection scope of the present invention.

To sum up, the invention discloses a kind of parameterized module multi-channel digital down-conversion design platform and method, the present invention is a kind of Digital Down Convert design platform of parameterized module, the analog input signal of N passage to be selected M passage carry out analog-to-digital conversion, then do Digital Down Convert and process output M roadbed band digital signal, subsequent treatment is used altogether.The present invention is not only a kind of design platform or a kind of method for designing, and the design process of the method for designing of this parameterized moduleization multi-channel digital down-conversion is: supplied with digital signal is carried out the quadrature mixing; Separate out filter order H and the extracting multiple D of branch according to the parametric solution that receives in real time, the signal after the quadrature mixing is done respectively delay, extraction and buffer memory; Simultaneously the filter coefficient of choosing is extracted rearrangement, obtain each branching filter coefficient vector and do buffer memory; The data of buffer memory and coefficient are sent to the multiply accumulating module simultaneously do branch's filtering and process, to its periodicity of fruiting extract, summation, get M roadbed band signal, each road signal comprises the orthogonal signalling of I, Q two-way.The present invention has advantages of ease for use, versatility and flexibility, is used for multichannel if sampling signal is transformed into baseband signal, reaches simultaneously the purpose that reduces data rate.

Claims (7)

1. parameterized module multi-channel digital down-conversion design platform, include analog-to-digital conversion module and N passage Digital Down Converter Module, N road analog signal is given N Digital Down Converter Module through the digital signal of analog-to-digital conversion module output and is done the Digital Down Convert processing, and output N roadbed band digital signal; It is characterized in that: parameterized module multi-channel digital down-conversion design platform also includes N channel analog signal Shaping Module, the parameter receiver module, input channel gating module, N channel parameters input port, N road analog signal inputs to N channel analog signal Shaping Module, export the N road through the analog signal of shaping and give analog-to-digital conversion module, data-interface is given the parameter receiver module with parameter simultaneously, the parameter receiver module is given input channel gating module with the order of passage gating, N passage of input channel gating module output enables control signal to analog-to-digital conversion module, enable under the control of control signal at N passage, analog-to-digital conversion module is done analog-to-digital conversion to the M road analog signal of selecting, output M railway digital signal is to M Digital Down Converter Module, the parameter receiver module is given the channel parameters on M road respectively the parameter input port of M Digital Down Converter Module simultaneously, under parameter control, do M railway digital down-converted, and output M roadbed band digital signal; Described Digital Down Converter Module is the Digital Down Converter Module of parameterized module.

According to claim 1 in parameterized module multi-channel digital down-conversion design platform, it is characterized in that: the Digital Down Converter Module of parameterized module, in original quadrature frequency mixing module, the data delay cache module, also increase on the basis of filter coefficient module and multiply accumulating module the parameter input port is arranged, filter order and data rate control module, the branching filter coefficient module, the parameter input port is given filter order and data rate control module with filter order control signal and speed control signal simultaneously, filter order and data rate control module while output filter exponent number and branch's extracting multiple signal are to the branching filter coefficient module, and branch's extracting multiple signal is delivered to the input of data delay cache module, be provided with feedback command information channel and filter factor sendaisle between branching filter coefficient module and the parameter input port, select the branching filter coefficient of actual needs according to parameter, the branching filter coefficient module is given the multiply accumulating module with each branching filter coefficient; The data of quadrature mixing are given the data delay cache module simultaneously, under the control of branch's extracting multiple signal, the data delay cache module carries out the reduction of speed processing of the lower delay of parametrization control and extraction to the data of mixing, data behind the reduction of speed are done buffer memory, then the multiply accumulating module is given in output, and the multiply accumulating module is finished the multiply accumulating of data and filter coefficient and exported the I of Digital Down Convert, Q two-way baseband digital signal.

According to claim 2 in parameterized module multi-channel digital down-conversion design platform, it is characterized in that: the branching filter coefficient module in the parameterized module Digital Down Converter Module also is parametrization control, according to filter order and branch's extracting multiple signal filter coefficient is selected, if inner preset filter coefficients can satisfy the demand of design, choice for use is preset at the filter coefficient among the buffer area A, if the filter order of determining does not mate with the filter order that presets, send feedback signal to the parameter input port, and export to data-interface through the parameter receiver module, require data-interface to send the filter coefficient on corresponding rank, and the filter coefficient that will receive in real time is buffered among the buffer area B of branching filter coefficient module, gives the multiply accumulating module of each branch.

4. parameterized module multi-channel digital down-conversion method for designing, it is characterized in that: design process comprises:

A, N passage are that the multi-channel analog signal Shaping Module carries out shaping to N road analog signal to be processed, and the analog signal after the output N road shaping also sends to analog-to-digital conversion module;

B, parameter receiver module receive data interface mainly comprise parameter that Ethernet interface, PCI mouth, serial ports, USB mouth are sent here and required filter coefficient, from Digital Down Converter Module feedback information are sent to data-interface simultaneously, carry out interactive process;

C, input channel gating module are exported the control signal that enables of N passage, and N passage of passage gating control signal generation of sending here according to the parameter receiver module enables control signal, and this enables control signal as the input signal of following analog-to-digital conversion module;

D, analog-to-digital conversion module comprise N analog to digital converter, and the N that analog-to-digital conversion module provides in input channel gating module enables under the control of control signal, select the analog signal of M road shaping and carry out analog-to-digital conversion and export independently digital signal of M road;

E, parameterized digital down conversion module comprise M digital down-converted module, wherein each Digital Down Converter Module is to realize parametrization control by input parameter, and Digital Down Converter Module realizes that the specific implementation process of Digital Down Convert comprises successively: quadrature mixing, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating;

F, the analog signal to be processed of N passage of input carried out respectively the operation of design process A～E, obtain the baseband digital signal after the M railway digital down-converted.

5. the parameterized module multi-channel digital down-conversion method for designing described in according to claim 4 is characterized in that the parameter receiving course, the wherein reception of parameter, form and be allocated as follows shown in:

The order that B1, receive data interface are sent here and corresponding filter coefficient send to each Digital Down Converter Module feedack to data-interface simultaneously;

B2, resolve the order that receives according to concrete communication protocol, obtain filter order control signal L and the speed control signal K of each passage, export to the parameter input port of the Digital Down Converter Module of respective channel, realize the parametrization control to each railway digital down-conversion;

B3, receiving filter coefficient, and filter coefficient carried out buffer memory, then export to the branching filter coefficient module of respective channel.

6. parameterized module multi-channel digital down-conversion method for designing according to claim 5 is characterised in that the generation that enables control signal of input channel gating, and its production method is:

The control signal of the passage gating that C1, input channel gating module reception parameter receiver module are sent here, resolve control signal according to concrete interface communications protocol, what obtain N passage enables control signal Ctrl[N-1:0], Ctrl[N-1:0] initialization value be made as zero, and be defined as effectively high;

C2, Ctrl[0 wherein] be that the analog-to-digital conversion of passage 1 enables control, Ctrl[1] be that the analog-to-digital conversion of passage 2 enables control ..., Ctrl[N-1] and be that the analog-to-digital conversion of passage N enables control;

C3, as Ctrl[0] when being high, it is that the analog signal of selector channel 1 is carried out analog-to-digital conversion that expression passage 1 enables, as Ctrl[0] when low, it is that the analog signal of passage 1 is not carried out analog-to-digital conversion that expression passage 1 does not enable; As Ctrl[1] when being high, expression passage 2 enables, as Ctrl[1] when being low, expression passage 2 does not enable, the rest may be inferred selects a needed M passage with N M effective signal that enables in the control signal respectively.

7. the parameterized module multi-channel digital down-conversion method for designing described in according to claim 6, it is characterized in that the realization of parameterized digital down-conversion, Digital Down Convert to each road of the M railway digital signal selected all can realize parametrization control, and design process comprises: quadrature mixing, filter order and data rate control, branching filter coefficient are selected, data delay buffer memory and multiply accumulating; Below each process is elaborated:

Digital signal and orthogonal local oscillation sequence that analog-to-digital conversion is exported in E1, quadrature mixing With

Multiply each other sample rate f _sWith signal intermediate frequency f ₀Satisfy certain relation, make the local oscillator sequence that multiplies each other

With

Satisfy:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{1,0},-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\},$ First sampled signal is carried out 2 times of extractions, obtain signal X (2n); After simultaneously sampled signal being postponed a clock cycle, carry out again 2 times of extractions and obtain signal X (2n+1), signal X (2n+1) has postponed a clock cycle than signal X (2n), adopt d type flip flop latch signal X (2n) to be about to X (2n) and postpone a clock cycle, sequence X (2n) and the X (2n+1) that extracts after aliging alternately multiplied each other respectively 1 and-1, obtain respectively I (n), Q (n) two paths of signals of quadrature;

E2, according to input parameter L and K, determine filter order H and the extracting multiple D of branch, the exponent number of the low-pass filter coefficients commonly used that sets in advance has 32 rank, 64 rank, 128 rank, 144 rank, be pre-stored among the buffer area A, can be in the situation that the filter coefficient of selecting this to preset without external filter coefficient input, if the inner filter coefficient that presets satisfies the demand of design, the filter coefficient that presets among the choice for use buffer area A, if the filter order H that determines does not mate with the filter order that presets, Cmd exports to data-interface to parameter receiver module feedback signal, require the filter coefficient on data-interface transmission H rank, and the H rank filter coefficient that will receive in real time is buffered among the buffer area B of branching filter coefficient module;

E3, controlling data delay according to the extracting multiple D of branch that obtains among the above process E2, is f in frequency _sUnder/2 the clock control, to I (n), Q (n) two paths of signals of the quadrature that produces among the E1 carry out respectively 0,1,2 ..., a D-1 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel D data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD, this moment, the data rate of each branch road was the same, I (n) among data rate and the E1, Q (n) two paths of data speed are identical, are f _s/ 2;

E4, controlling data pick-up according to the extracting multiple D of branch that obtains among the above process E2, is f in frequency _sUnder/2 the clock control, to data branch road Id1, Id2 after postponing among the E3 ..., IdD, Qd1, Qd2 ..., QdD carries out respectively D and doubly extracts namely and extract a number every D-1 data, data branch road after obtaining like this extracting be Ic1, Ic2 ..., IcD, Qc1, Qc2 ..., QcD, this moment each branch data rate be data rate among the E3 1/D doubly, be f _s/ 2D;

E5, be f in frequency _sUnder the clock control of/2D, with data branch road Ic1, Ic2 after the extraction that obtains among the E4 ..., IcD, Qc1, Qc2 ..., QcD write respectively separately data buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., among the RAMDQD;

E6, according to the filter order H that obtains among the above process E2 and the extracting multiple D of branch, produce switching signal Select by data selector, choose optimum filter coefficient, when Select is ' 0 ', choose the filter coefficient among the buffer area A, when Select is ' 1 ', choose the filter coefficient among the buffering area B;

E7, control the generation of branching filter coefficient according to the extracting multiple D of branch that obtains among the above process E2, at first with the coefficient C of the filter chosen among the above process E6 ₁, C ₂, C ₃..., C _HCarry out odd even and extract the filter coefficient C of even number ₂, C ₄..., C _HForm I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C _H-1Form Q path filter coefficient, I path filter coefficient is begun to carry out D from first coefficient doubly extract, obtain the filter coefficient C of I1 branch ₂,

, I path filter coefficient is carried out D since second coefficient doubly extract, obtain the filter coefficient C of I2 branch ₄...,

,

The rest may be inferred to the filter coefficient C of ID branch _2D,

,

I path filter coefficient resolves into the filter coefficient vector of D branch altogether, at last the filter coefficient vector inverted sequence of each branch is buffered in separately coefficient buffering area RAMCI1, RAMCI2 ..., among the RAMCID, be followed successively by by address order from small to large such as the coefficient of buffer memory among the RAMCI1

,

C ₂, the coefficient in other buffering area as can be known in like manner, the generation of Q road branching filter coefficient is identical with the treatment step on I road;

E8, branch's filtering are actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 2D branch need 2D multiply accumulating module, in frequency are

Clock control under, with above process E5 buffer area RAMDI1, RAMDI2, RAMDID, RAMDQ1, RAMDQ2, the I of buffer memory among the RAMDQD, the data reading of each branch of Q two-way, simultaneously with above process E7 buffer area RAMCI1, RAMCI2, RAMCID, RAMCQ1, RAMCQ2, the I of buffer memory among the RAMCQD, the filter coefficient of each branch of Q two-way is read, the data of reading among RAMDI1 and the RAMCI1 and coefficient are given respectively the input of a multiply accumulating module, carry out the filtering of I1 branch, the filtering of other each branch is identical, I, the filtering result of each branch of Q two-way is doutI1, doutI2, doutID, doutQ1, doutQ2, doutQD, this moment, the data rate of each branch was f _s/ 2D;

E9, be f in frequency _sUnder the clock control of/2D, with D the branch's filtering in I road among the E8 as a result doutI1, doutI2 ..., the doutID addition, the I road result who obtains Digital Down Convert exports doutI; With D the branch's filtering in Q road as a result doutQ1, doutQ2 ..., the doutQD addition, the Q road result who obtains Digital Down Convert exports doutQ.So far, finished the processing of parameterized module Digital Down Convert.

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