CN109031213B

CN109031213B - Universal dynamic reconfigurable digital beam forming method and device

Info

Publication number: CN109031213B
Application number: CN201810564579.2A
Authority: CN
Inventors: 周小龙
Original assignee: CETC 14 Research Institute
Current assignee: CETC 14 Research Institute
Priority date: 2018-06-04
Filing date: 2018-06-04
Publication date: 2022-05-13
Anticipated expiration: 2038-06-04
Also published as: CN109031213A

Abstract

The invention discloses a universal dynamic reconfigurable digital beam forming method and device. The method comprises the steps of configuring M input channels, inputting data in parallel through the M input channels, combining the M channel data input in parallel into one channel data for output in a time-sharing mode, carrying out multi-channel time-sharing running water multiplication and accumulation operation on the one channel data by adopting N parallel multiplication and accumulation branches to obtain an operation result, and splitting the operation result into K wave beams for parallel output in a time-sharing mode, wherein K is the total wave beam number, and the wave beam number A synthesized by each multiplication and accumulation branch in a time-sharing mode meets the condition A which is K/N. The invention constructs an operation framework by taking a reconfigurable multiply-accumulate branch as a basic unit, realizes the digital beam forming of multi-channel and multi-beam by time-sharing in the branch and parallel running water operation among the branches, and realizes the digital beam forming which supports various data rates and can dynamically configure the number of channels and beams by dynamic reconfiguration of the operation framework.

Description

Universal dynamic reconfigurable digital beam forming method and device

Technical Field

The present invention relates to digital beamforming methods and apparatuses, and particularly to a universal dynamic reconfigurable digital beamforming method and apparatus.

Background

Digital Beam Forming (DBF) is a new technology of one-gate radar established by introducing a Digital signal processing method on the basis of an analog Beam Forming principle. For the inter-channel phase difference caused by the electromagnetic wave propagation path difference caused by different spatial positions of the antenna units, the traditional analog beam forming process is to perform phase shift and analog synthesis on each array element signal on an intermediate frequency carrier or a radio frequency carrier, and the digital beam forming is to perform AD sampling digitization on the signals output by the array antenna, and then use a digital beam former to perform complex weighting to compensate the inter-channel phase difference, so as to realize in-phase superposition of the signals, thereby realizing the maximum energy reception in a certain direction and obtaining the performances of super-resolution and low side lobe.

Because the phased array radar array antenna has a large number of output channels and a high data rate, the digital beam forming is mostly realized by adopting the FPGA. However, the data rate of the array downlink, the number of channels and the number of beams to be synthesized in each type of radar are different, and respective digital beam forming FPGA programs are often required to be repeatedly developed for each type of radar, so that manpower and material resources are consumed, the radar development period is prolonged, and the development difficulty is increased. Therefore, it is necessary to provide a dynamically reconfigurable digital beam forming method with general applicability in various types of radars based on the idea of dynamic reconfiguration, so as to improve the development efficiency of the digital beam forming FPGA and make it suitable for ASIC design, and avoid the repeated design of the digital beam former in various types of radars.

Disclosure of Invention

The technical problem to be solved by the invention is to overcome the defects of the prior art and provide a universal dynamic reconfigurable digital beam forming method and device.

In order to solve the technical problems, the invention is suitable for the dynamic reconfigurable digital beam forming of the FPGA and the special ASIC, realizes the digital beam forming of multi-channel and multi-beam by time-sharing in the branches and parallel running-water operation among the branches, and realizes the digital beam forming which supports various data rates and can dynamically configure the number of channels and beams by the dynamic reconfiguration of an operation framework.

The invention discloses a universal dynamic reconfigurable digital beam forming method, which comprises the following steps:

the method comprises the following steps: configuring M input channels, inputting data in parallel through the M input channels, and combining the M channel data input in parallel into one path of data for output in a time-sharing manner, wherein M is a natural number;

step two: carrying out multi-channel time-sharing running water multiplication and accumulation operation on the one-path data by adopting N parallel multiplication and accumulation branches to obtain an operation result, wherein N is a natural number;

step three: and splitting the operation result into K beams in a time-sharing manner and outputting the K beams in parallel, wherein K is the total beam number, and the beam number A synthesized by each multiply-accumulate branch in a time-sharing manner meets the condition that A is K/N.

Preferably, the operation result satisfies the following condition:

where Q (X, K) is the output result, K is 0,1, …, K is the total number of output beams, X is 0,1, … X, X is the total number of input range gates, D (i, X) is the input data of the xth range gate of the ith channel, and w (i, K) is the weight of the kth beam of the ith channel.

Preferably, the multiply-accumulate branches include weighting branches, accumulating branches, and weight RAM groups, where the weight RAM group includes N independent RAMs, and each RAM stores a weight of a corresponding weighting branch.

Preferably, each weighting branch includes a multiplier, and the multiplier multiplies each channel data by a weight, where M channel data are serially and pipelined and multiplies each channel data by a weight, and a clock cycle outputs one channel data, so as to implement time-sharing and pipelined multiplication of each channel data and a beam weights, and N branches implement weighting of K beams in parallel, where K is equal to a × N.

Preferably, when the synthesized total beam number K satisfies K < a × N, the weighting branch is dynamically turned off to reduce the power consumption of the circuit.

Preferably, each accumulation branch comprises an accumulator, the accumulation of M channels of A wave beams is completed through time division multiplexing, the output of the accumulator is fed back to the input end to realize channel accumulation, the wave beam time division multiplexing is inserted into the register through a feedback loop, and the A wave beam time division multiplexing is inserted into the A registers; after accumulation is finished, 0 is fed back to the input end through the selector, and the feedback path of the accumulator is disconnected.

Preferably, the weight RAM group is a weight RAM group that realizes serial flow weighting of a number of beams of M channels by matching with the weighting branch, and a × M weights need to be stored in each RAM.

Preferably, the M channel data in the first step and the K beams in the third step respectively satisfy s _ M _ value dynamic configuration, where s _ axi _ data _ i is ith channel input data, i is 0,1, … M-1, M _ axi _ data _ K is kth beam output data, and K is 0,1, … K-1.

Preferably, M input channels in the first step are connected with interfaces, K beams in the third step are output through output channels, and the output channels are connected with interfaces, where the interfaces are non-blocking standard AXI4-Stream interfaces.

The invention also provides a universal dynamic reconfigurable digital beam forming device, which comprises a channel merging module, a time-sharing running water multiply-accumulate module and a beam splitting module, wherein the channel merging module is connected with the time-sharing running water multiply-accumulate module, the time-sharing running water multiply-accumulate module is connected with the beam splitting module,

the channel merging module is configured with M input channels, data is input in parallel through the M input channels, and the M channel data input in parallel are merged into one path of data in a time-sharing manner, wherein M is a natural number;

the time-sharing running water multiply-accumulate module comprises N parallel multiply-accumulate branches for carrying out multi-channel time-sharing running water multiply-accumulate operation on the one-path data to obtain an operation result, wherein N is a natural number;

and the beam splitting module splits the operation result into K beams in a time-sharing manner and outputs the K beams in parallel, wherein K is the total beam number, and the beam number A synthesized by each multiply-accumulate branch in a time-sharing manner meets the condition that A is K/N.

Preferably, the operation result satisfies the following condition:

Preferably, the time-sharing running water multiply-accumulate module comprises a weighting calculation path, a channel synthesis path and a weight RAM group, wherein the weight RAM group comprises N independent RAMs, and each RAM stores the weight of the corresponding weighting branch.

Preferably, the weighting calculation path includes a multiplier, and the multiplier multiplies each channel data by a weight, where M channel data are serially and serially multiplied by pipeline, and each a clock cycle outputs one channel data, so as to implement time-sharing and pipeline multiplication of each channel data and a beam weights, and N branches implement weighting of K beams in parallel, where K is equal to a × N.

Preferably, the channel synthesis path includes an accumulator, which completes accumulation of M channels of a beams by time-division multiplexing, and feeds back the output of the accumulator to the input end to realize channel accumulation, the beam time-division multiplexing is inserted into the register through the feedback loop, and the a beams time-division multiplexing is inserted into the a registers; after accumulation is finished, 0 is fed back to the input end through the selector, and the feedback path of the accumulator is disconnected.

Preferably, the weight RAM group is a weight RAM group for realizing serial flow weighting of a number of beams of M channels by matching with the weighting branch, and a × M weights need to be stored in each RAM.

Preferably, M channel data in the channel combining module and K beams in the beam splitting module respectively satisfy s _ M _ value dynamic configuration, where s _ axi _ data _ i is ith channel input data, i is 0,1, … M-1, M _ axi _ data _ K is kth beam output data, and K is 0,1, … K-1.

Preferably, M input channels of the channel merging module are connected with interfaces, K beams in the beam splitting module are output through an output channel, and the output channel is connected with an interface, where the interface is a non-blocking standard AXI4-Stream interface.

The invention achieves the following beneficial effects: firstly, under the application condition of high working main frequency and low data rate, each multiply-accumulate branch circuit completes the flow weighted synthesis of a plurality of input channels and a plurality of beams in a time-sharing manner, and the operation efficiency is high. Secondly, under the application condition of more input channels, the expansion of the processing channels can be realized through the parallel operation of a plurality of digital beam formers. Thirdly, the time-sharing accumulation synthesis of a plurality of beams is realized through a feedback loop formed by cascading 1 adder and a plurality of registers, and the register stage can be dynamically reconstructed to realize the compatibility of any beam time-sharing accumulation. Fourthly, on the basis that each multiply-accumulate branch completes a plurality of wave beams in a time-sharing mode, a plurality of multiply-accumulate branches are adopted to complete the synthesis of more wave beams in parallel, and the multiply-accumulate branches can be dynamically turned on or turned off according to the number of the wave beams so as to reduce the power consumption of the circuit. Fifthly, the input/output interface conforms to the non-blocking standard AXI Stream interface and supports the interrupt transmission of input data. Therefore, the invention is compatible with various data rate inputs, the number of channels and the number of beams can be dynamically configured, and the invention is suitable for different application scenes and has strong universality.

Drawings

Fig. 1 is a flow chart diagram of a universal dynamic reconfigurable digital beamforming method of the present invention.

FIG. 2 is a schematic diagram of the order of the RAM group storing weights in the universal dynamic reconfigurable digital beam forming method of the present invention.

Fig. 3 is a schematic structural diagram of the channel synthesis accumulator with a beams time-sharing according to the present invention.

Fig. 4 is a schematic diagram of a universal dynamically reconfigurable digital beamforming apparatus of the present invention.

Fig. 5 is a schematic diagram of a 24-channel 48-beam digital beamforming process of the present invention.

FIG. 6 is a timing diagram illustrating 24-channel merging according to the present invention.

FIG. 7 is a schematic diagram of the 24-channel 2-beam time-division weighting and channel synthesis timing sequence of the present invention.

Fig. 8 is a schematic diagram of the order of the weight coefficients stored in the 24-channel 48-beam RAM according to the present invention.

Fig. 9 is a schematic diagram of the structure of the channel synthesis accumulator of the present invention with 2 beam time-sharing.

Fig. 10 is a schematic diagram of the beam splitting timing sequence of the 2 beams of the present invention.

Fig. 11 is a schematic diagram of the 48-channel 24-beam pipelined digital beamforming process after reconstruction according to the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

Example 1

In the universal dynamic reconfigurable digital beam forming method in this embodiment, as shown in fig. 1, M channel data input in parallel are first combined into one channel in a time-sharing manner, then, N parallel reconfigurable multiply-accumulate branches are used to perform multi-channel time-sharing flow multiply-accumulate operation on the channel data, and finally, the operation result is split into K beams in a time-sharing manner and is output in parallel. Each multiply-accumulate branch processes M channel data, the number of beams time-shared and synthesized by each multiply-accumulate branch is A (K/N), each multiply-accumulate branch is divided into a weighting branch and an accumulating branch, wherein s _ axi _ data _ i is ith channel input data, and i (0, 1, … M-1); m _ axi _ data _ K is the K-th beam output data after the calculation is completed, and K is 0,1, … K-1. The input and output interfaces all conform to the non-blocking standard AXI4-Stream interface, the number of channels M can be dynamically configured by the input interface s _ M _ value, and the number of beams K can be dynamically configured by the input interface s _ K _ value.

If the weight of the kth wave beam of the ith channel is w (i, k), the input data of the xth range gate of the ith channel is D (i, x), and the output result is Q (x, k), then after the dynamic reconfigurable digital wave beam is formed, the method can obtain:

where K is 0,1, …, K is the total number of output beams, X is 0,1, … X, and X is the total number of input range gates.

And combining the data of the M channels input in parallel into one path for output in a time-sharing manner. Setting the input data rate as fin and the work dominant frequency fwork, wherein the work dominant frequency meets the following requirements: fwork ≧ A × M × fin. The method includes the steps that data of each channel are registered when s _ axi _ valid is valid, then polling is conducted on M channel data, the polling is conducted once every A clock period, when the registered data are valid, the data of each channel are sequentially and serially output, the data and valid signals of the data are valid for A clock periods, the y% (M x A) (% represents remainder and the same below) path of data are output in the y valid clock period, valid signals are output in the last channel of the same distance point at the same time, all channels of the same distance point are represented to be completely output, and invalid valid signals are output in invalid clock periods, wherein y is 0,1 and ….

Each weighting branch has a multiplier to complete the multiplication of each channel data and the weight value, so as to realize the weighting of the channel data. And one multiplication operation is completed in each clock cycle, the M channel data are subjected to serial pipeline multiplication, one channel data is output in each A clock cycle, so that the time-sharing pipeline multiplication of each channel data and A beam weights can be realized, and the N branches are subjected to parallel weighing of K (equal to A x N) beams. If the total beam number K is smaller, namely K < A x N, some weighting branches can be closed dynamically to reduce the power consumption of the circuit.

The weight RAM group comprises N independent RAMs, and each RAM stores the weight of the corresponding weighted branch. In order to realize the serial flow weighting of A wave beams of M channels by matching with the weighting branch circuits, A x M weight values need to be stored in each RAM. The storage sequence is shown in fig. 2, where Ch represents a channel, B represents a beam, each RAM stores a beam weight of a 1 st channel a, then a beam weight of a 2 nd channel a, and so on; the 1 st RAM stores 1-A wave beam weight, the 2 nd RAM stores A + 1-2A wave beam weight, and so on.

Each accumulation branch is provided with an accumulator, and the accumulation of M channels of A wave beams is completed through time division multiplexing. The input last signal indicates the end of accumulation and outputs a beam results in series. The structural block diagram is shown in fig. 3, channel accumulation is realized by feeding back the output of the adder to the input end, beam time division multiplexing is realized by inserting a feedback loop into a register, and A beam time division multiplexing is inserted into A registers. After the accumulation is finished, 0 is fed back to the input end through the selector, which is equivalent to disconnecting the feedback path of the accumulator. The feedback path output from a register of the a registers may be dynamically reconfigured to change the number of feedback register stages to support the case where the number of beams is less than a.

And splitting the wave beam for the wave beam synthesis result of each branch to perform serial-parallel conversion, and extracting A paths of data from the A wave beam results which are output in series and outputting the data in parallel. The method comprises the steps of firstly carrying out A-path shifting on input data respectively, shifting an ith path by A-i-1 clock cycle, and simultaneously outputting a result after the A-path shifting when y% A is equal to A-1 in an y-th effective clock cycle, wherein i is equal to 0,1 …, A-1, y is equal to 0, and 1 ….

Example 2

The present embodiment is an embodiment of the apparatus, and belongs to a unified technical concept with embodiment 1, and please refer to method embodiment 1 for the content not described in detail in embodiment 2 of the apparatus.

As shown in fig. 4, the universal dynamic reconfigurable digital beam forming apparatus in this embodiment includes a channel merging module, a time-sharing stream multiplication and accumulation module, and a beam splitting module, where the channel merging module is connected to the time-sharing stream multiplication and accumulation module, and the time-sharing stream multiplication and accumulation module is connected to the beam splitting module.

(1) Channel merging module

The channel combination is used for channel data parallel-serial conversion, and the data of M channels input in parallel are combined into one path for output in a time-sharing mode. Setting the input data rate as fin and the work dominant frequency fwork, wherein the work dominant frequency meets the following requirements: fwork ≧ A × M × fin. The method includes the steps that data of each channel are registered when s _ axi _ valid is valid, then polling is conducted on M channel data, the polling is conducted once every A clock period, when the registered data are valid, the data of each channel are sequentially and serially output, the data and valid signals of the data are valid for A clock periods, the y% (M x A) (% represents remainder and the same below) path of data are output in the y valid clock period, valid signals are output in the last channel of the same distance point at the same time, all channels of the same distance point are represented to be completely output, and invalid valid signals are output in invalid clock periods, wherein y is 0,1 and ….

(2) Time-sharing flow water multiplication accumulation module

The time-sharing running water multiply-accumulate module comprises a weighting calculation channel, a channel synthesis channel and a weight RAM group.

The weighting calculation path comprises N weighting branches, and each branch is provided with a multiplier to complete the multiplication of each channel data and the weight value so as to realize the weighting of the channel data. And one multiplication operation is completed in each clock cycle, the M channel data are subjected to serial flow multiplication, one channel data is output in each A clock cycle, so that the time-sharing flow multiplication of each channel data and A beam weights can be realized, and the N branches are subjected to parallel weighing of K (equal to A x N) beams. If the total number of synthesized beams is small, namely K < A x N, some weighting branches can be closed dynamically to reduce the power consumption of the circuit.

The weight RAM group comprises N independent RAMs, and each RAM stores the weight of the corresponding weighted branch. In order to realize serial flow multiplication of A wave beams of M channels by matching with the weighting branch circuits, A x M weight values need to be stored in each RAM. The storage sequence is shown in fig. 2, where Ch represents a channel, B represents a beam, each RAM stores a beam weight of a 1 st channel a, then a beam weight of a 2 nd channel a, and so on; the 1 st RAM stores 1-A wave beam weight, the 2 nd RAM stores A + 1-2A wave beam weight, and so on.

The channel synthesis path comprises N accumulation branches, each branch is provided with an accumulator, and accumulation of M channels of A beams is completed through time division multiplexing. The input last signal indicates the end of accumulation, and a beam results are output in series. The structural block diagram is shown in fig. 3, channel accumulation is realized by feeding back the output of the adder to the input end, beam time division multiplexing is realized by inserting a feedback loop into a register, and A beam time division multiplexing is inserted into A registers. After the accumulation is finished, 0 is fed back to the input end through the selector, which is equivalent to disconnecting the feedback path of the accumulator. The feedback path output from a register of the a registers may be dynamically reconfigured to change the number of feedback register stages to support the case where the number of beams is less than a.

(3) Beam splitting module

Example 3

The present embodiment takes a design of a 24-channel 48-beam serial digital beam as an example to illustrate the technical solution of the present invention.

Under the application requirements of an ASIC working main frequency of 500MHz, input single-channel data rate of 10M, channel number of 24 and output beam number of 48, a 24-channel 48-beam pipelined digital beam former is designed.

The input data rate is 10M, the working main frequency fwok is 500M, the number of channels M is 24, in order to meet the condition that fwok is larger than or equal to a M fin, the beam number a processed by each path of the multiply-accumulate branches in a time-sharing mode is 2, the beam number K is 48, and the enabled multiply-accumulate branch number N is 24. The digital beam former designed according to the above parameters, as shown in fig. 5, includes 24 multiply-accumulate branches, each of which implements time-division weighted synthesis of 24 channels and 2 beams.

The channel merging module merges the 24 channel data input in parallel into one path of serial output, and a timing chart is shown in fig. 6. Registering data s _ axi _ data 0-23 of each channel when s _ axi _ valid is valid, then polling and selecting output from 24 channel data, polling once every 2 clock cycles, when the registered data is valid, serially outputting the data of each channel in turn through a ch _ comb _ data signal, enabling the data and the ch _ comb _ valid signal thereof for 2 clock cycles, and outputting the ch _ comb _ last signal at the same time at the last channel data output of the same distance point.

The weighting calculation path comprises 24 weighting branches, each branch completes the multiplication of the data and the weight value of each channel through a multiplier so as to realize the weighting of the channel data, and the time sequence diagram of the channel data is shown as the weighted signal in fig. 7. The multiplication operation is completed once in each clock cycle, the data serial flow multiplication of 24 channels is realized and is output by the wgt _ mult _ data signal, because one channel data is output in every 2 clock cycles, the time-sharing flow multiplication of 2 beams in each channel can be realized, the input source data is multiplied by the beam 1 weight w1 in the 1 st clock cycle of the effective valid, the 2 nd clock cycle is multiplied by the beam 2 weight w2, and the source data of each channel is correspondingly multiplied by the weight of the corresponding channel. The 24 branches implement in parallel the weighting of 48 (equal to 2 x 24) beams.

The weight RAM group comprises 24 independent RAMs, and each RAM stores the weight of the corresponding weighted branch. In order to realize serial flow multiplication of 2 beams of 24 channels by matching with the weighting branch, 2 × 24 weight values need to be stored in each RAM. The weight storage in the RAM is as shown in fig. 8, each RAM stores the weight of 1 st channel 1-2 wave beams, then stores the weight of 2 nd channel 1-2 wave beams, and so on; and 1-2 wave beam weight values are stored in the 1 st RAM, 3-4 wave beam weight values are stored in the 2 nd RAM, and the like.

The channel synthesis path comprises 24 channel accumulation branches, each branch completes accumulation of 24 channels and 2 beams through time division multiplexing of an accumulator, and 2 beam results are output in series. The adder outputs feedback to the input end to realize accumulation, time division multiplexing is realized by inserting a feedback loop into a register, 2 wave beams are inserted into 2 registers in time division multiplexing, and an accumulator circuit is shown in fig. 9. After the accumulation is finished, 0 is fed back to the input end through the selector, which is equivalent to disconnecting the feedback path of the accumulator. The timing diagram is shown in fig. 7 as the weighted merge signal, when the wgt _ mult _ last signal is asserted, the result of the 24-channel accumulation is output, wherein d1 w1 is the result of the 24-channel weighted accumulation (equal to 1_1 w1_1+1_2 w1_2+ … +1_24 w1_ 24).

The beam splitting is used for the serial-to-parallel conversion of the beam forming result of each branch, and 2 parallel data outputs are extracted from the 2 beam results output in series, and the timing diagram is shown in fig. 10. And the 24 branches extract 48 beam synthesis results in parallel.

In the above embodiment, a 24-channel 48-beam running-water digital beam former is designed, and if the main frequency of the ASIC operation is 500MHz, and the input single-channel data rate is reduced from 10M to 5M, the reconfigurable multiply-accumulate branch can be dynamically reconfigured into beam synthesis in which the number of channels M is 48 and the number of beams a is 2, which realize time-sharing processing, under the condition that fwok is not less than a × M × fin. At this time, if only the synthesized output of 24 beams is needed, the clocks of the last 12 multiply-accumulate branches can be turned off in a dynamic reconstruction manner, only the operations of the first 12 branches are started to reduce the power consumption of the circuit, the structure of the reconstructed beam former is shown in fig. 11, and the circuits in the dashed frame are all set to be invalid by turning off the clocks.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. A universal dynamic reconfigurable digital beam forming method is characterized in that: the method comprises the following steps:

step three: splitting the operation result into K wave beams in a time-sharing manner and outputting the wave beams in parallel, wherein K is the total wave beam number, and the wave beam number A synthesized by each multiply-accumulate branch in a time-sharing manner meets the condition that A is K/N;

the operation result satisfies the following conditions:

wherein Q (X, K) is the output result, K is 0,1, …, K is the total output beam number, X is 0,1, … X, X is the total input range gate number, D (i, X) is the input data of the xth range gate of the ith channel, and w (i, K) is the weight of the kth beam of the ith channel;

the multiply-accumulate branch comprises a weighting branch, an accumulate branch and a weight RAM group, the weight RAM group comprises N independent RAMs, and each RAM stores the weight of the corresponding weighting branch;

each weighting branch comprises a multiplier, the multiplier multiplies each channel data by a weight, wherein M channel data are serially and serially multiplied by pipeline, each A clock cycle outputs one channel data, time-sharing pipeline multiplication of each channel data and A beam weights is realized, N branches realize weighting of K beams in parallel, and K is equal to A x N.

2. The universal dynamic reconfigurable digital beamforming method according to claim 1 wherein: and when the synthesized total beam number K meets K < A x N, dynamically closing the weighting branch to reduce the power consumption of the circuit.

3. The universal dynamic reconfigurable digital beamforming method according to claim 1 wherein: each accumulation branch comprises an accumulator, accumulation of M channels of A wave beams is completed through time division multiplexing, the output of the accumulator is fed back to an input end to realize channel accumulation, the wave beam time division multiplexing is inserted into a register through a feedback loop, and the A wave beam time division multiplexing is inserted into the A register; after accumulation is finished, 0 is fed back to the input end through the selector, and the feedback path of the accumulator is disconnected.

4. The universal dynamic reconfigurable digital beamforming method according to claim 1 wherein: the weight RAM group is used for realizing serial flow weighting of the A wave beams of the M channels by matching with the weighting branch, and A x M weights need to be stored in each RAM.

5. The universal dynamic reconfigurable digital beamforming method according to claim 1 wherein: the M channel data in the first step and the K beams in the third step respectively satisfy s _ M _ value dynamic configuration, where s _ axi _ data _ i is ith channel input data, i is 0,1, … M-1, M _ axi _ data _ K is kth beam output data, and K is 0,1, … K-1.

6. The universal dynamic reconfigurable digital beamforming method according to claim 1 wherein: in the first step, M input channels are connected with interfaces, in the third step, K beams are output through output channels, the output channels are connected with interfaces, and the interfaces are non-blocking standard AXI4-Stream interfaces.

7. A universal dynamic reconfigurable digital beam forming device is characterized in that: the system comprises a channel merging module, a time-sharing flow multiplication and accumulation module and a beam splitting module, wherein the channel merging module is connected with the time-sharing flow multiplication and accumulation module;

the beam splitting module splits the operation result into K beams in a time-sharing manner and outputs the K beams in parallel, wherein K is the total beam number, and the beam number A synthesized by each multiply-accumulate branch in a time-sharing manner meets the condition that A is K/N;

the operation result satisfies the following conditions:

the time-sharing flow multiplication accumulation module comprises a weighting calculation path, a channel synthesis path and a weight RAM group, wherein the weight RAM group comprises N independent RAMs, and each RAM stores the weight of a corresponding weighting branch;

the weighting calculation path comprises a multiplier which multiplies each channel data by a weight, wherein M channel data are subjected to serial flow multiplication, one channel data is output in each A clock cycle, time-sharing flow multiplication of each channel data and A beam weights is realized, N branches are subjected to parallel weighing of K beams, and K is equal to A x N.

8. The universal dynamic reconfigurable digital beamforming device as recited in claim 7, wherein: and when the synthesized total beam number K meets K < A x N, dynamically closing the weighting branch to reduce the power consumption of the circuit.

9. The universal dynamic reconfigurable digital beamforming device according to claim 7 wherein: the channel synthesis path comprises an accumulator, the accumulation of M channels of A wave beams is completed through time division multiplexing, the output of the accumulator is fed back to an input end to realize the channel accumulation, the wave beam time division multiplexing is inserted into a register through a feedback loop, and the A wave beam time division multiplexing is inserted into the A register; after accumulation is finished, 0 is fed back to the input end through the selector, and the feedback path of the accumulator is disconnected.

10. The universal dynamic reconfigurable digital beamforming device according to claim 7 wherein: the weight RAM group is used for realizing serial flow weighting of A wave beams of M channels by matching with the weighting branch circuits, and A x M weights need to be stored in each RAM.

11. The universal dynamic reconfigurable digital beamforming device according to claim 7 wherein: the method further includes that M channel data in the channel merging module and K beams in the beam splitting module respectively satisfy s _ M _ value dynamic configuration, where s _ axi _ data _ i is ith channel input data, i is 0,1, … M-1, and M _ axi _ data _ K is kth beam output data, and K is 0,1, … K-1.

12. The universal dynamic reconfigurable digital beamforming device according to claim 11 wherein: the M input channels of the channel merging module are connected with interfaces, K beams in the beam splitting module are output through output channels, the output channels are connected with interfaces, and the interfaces are non-blocking standard AXI4-Stream interfaces.