CN104320088B - A kind of Digital Down Convert circuit - Google Patents
A kind of Digital Down Convert circuit Download PDFInfo
- Publication number
- CN104320088B CN104320088B CN201410581682.XA CN201410581682A CN104320088B CN 104320088 B CN104320088 B CN 104320088B CN 201410581682 A CN201410581682 A CN 201410581682A CN 104320088 B CN104320088 B CN 104320088B
- Authority
- CN
- China
- Prior art keywords
- mrow
- circuit
- filtering
- cic
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000605 extraction Methods 0.000 claims abstract description 109
- 238000001914 filtration Methods 0.000 claims abstract description 95
- 238000007781 pre-processing Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 16
- 238000005070 sampling Methods 0.000 claims description 12
- 101100439738 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CIC1 gene Proteins 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 claims description 5
- 230000001186 cumulative effect Effects 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 23
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Complex Calculations (AREA)
- Superheterodyne Receivers (AREA)
Abstract
The invention discloses a kind of Digital Down Convert circuit, including data preprocessing module and frequency mixing module, it is characterised in that：The I roads output terminal of frequency mixing module is connected with the first CIC filtering extraction circuits in turn respectively with Q roads output terminal, 2nd CIC filtering extraction circuits, HB filtering extractions circuit and FIR filtering extraction circuits, first CIC filtering extraction circuits, 2nd CIC filtering extraction circuits, HB filtering extractions circuit and FIR filtering extraction circuits are connected with controller, in the first CIC filtering extraction circuits, bypass selecting switch is also associated with 2nd CIC filtering extractions circuit and HB filtering extraction circuits, when a certain bypass selecting switch is connected, the extraction yield of that stage circuit corresponding to the bypass selecting switch is 1.Its remarkable result is：Circuit structure is simple, easy to control, when input signal sample rate is 102.4MSPS, signal processing bandwidth can in the range of 100Hz~40MHz flexible configuration.
Description
Technical field
The present invention relates to Digital Signal Processing, is a kind of Digital Down Convert circuit specifically.
Background technology
In the receiver back end signal processing having been widely used at present and software radio, multirate signal processing is most
The item of digital signal processing technology that the nearly more than ten years grow up, it be to filter, extract, it is interior be inserted as basic means, by changing
The sampling rate of varying signal is to adapt to the needs of various processing digital signals, and Digital Down Convert (Digital Down
Convert, DDC) it is important component therein.
Digital Down Convert (DDC) is located at after high-speed a/d converter, the needs and processing energy handled according to follow-up signal
Power, there is provided suitable data sampling rate and process bandwidth, so its arithmetic speed directly limit the highest sample rate of A/D, and
Determine the maximum process bandwidth of receiver.
And current commercial digital low-converter has bigger limitation, otherwise it is that the data sampling rate inputted is inadequate
Height, otherwise be to provide can process bandwidth it is restricted, compatibility and flexibility it is poor.
It is a kind of algorithms most in use structure for realizing arrowband DDC shown in Fig. 1, it is mixed including digital controlled oscillator (NCO), numeral
Frequency device, CIC (Cascaded Integrator Comb, cascaded integrator-comb) decimation filter, HB (Half Band, half band)
Decimation filter, FIR (Finite Impulse Response, finite impulse response) wave filter and parameter setting and control etc.
Module, due to using cic filter, when realizing arrowband demand, being limited to the maximum extraction yield of cic filter, therefore can carry
The process bandwidth scope of confession is little, is usually no more than 1MHz, it is difficult to adapt to application demand.
The content of the invention
Only in view of this, in order to provide larger range of signal processing bandwidth, a variety of signal processings of flexible adaptation need
Ask, give full play to the adaptable advantage of software radio, the present invention provides a kind of Digital Down Convert circuit, used specific
Technical solution be：
A kind of Digital Down Convert circuit, including data preprocessing module and frequency mixing module, the data preprocessing module are used
In the collection for realizing digital medium-frequency signal, the frequency mixing module includes digital controlled oscillator, and digital controlled oscillator output two-way is mutual
Orthogonal local oscillation signal simultaneously realizes Frequency mixing processing with the intermediate-freuqncy signal, and the output of I roads and Q are formed in the output terminal of the frequency mixing module
Road exports, its key is：The I roads output terminal of the frequency mixing module is connected with the first CIC filtering in turn respectively with Q roads output terminal
Extraction circuit, the 2nd CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extraction circuits, the digital controlled oscillator,
First CIC filtering extractions circuit, the 2nd CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extractions circuit with
Controller is connected, which is used for realization parameter and the logic control of modules, in the first CIC filtering extractions electricity
Bypass selecting switch is also associated with road, the 2nd CIC filtering extractions circuit and HB filtering extraction circuits, when a certain bypass selection
During switch connection, the extraction yield of that stage circuit corresponding to the bypass selecting switch is 1.
Through the above scheme as can be seen that this programme is filtered in common lower frequency changer circuit structure by adding level-one CIC
Ripple extraction circuit, while bypass selecting switch is added to CIC filtering extractions circuits at different levels and HB filtering extraction circuits, when needing pole
When wide process bandwidth, the two CIC filtering extractions circuits and HB filtering extraction circuits of front end are set to bypass, are filtered by FIR
Extraction circuit plays the role of filtering and provides maximum bandwidth；When minimum process bandwidth is needed, the CIC filtering of front end two
Extraction circuit can extract very big extraction yield, then with HB filtering extractions circuit and FIR filtering extraction electrical combinations, just can obtain
The extraction yield of bigger, so that extremely narrow process bandwidth is readily obtained, in the other processing that can be provided in bandwidth range
Bandwidth, control parameter that can be according to the emphasis of application item by each circuit module of controller flexible configuration, so as to reach
Optimal application effect.
As further describing, the data preprocessing module includes parallel/serial modular converter, FIFO buffer modules and patrols
Control module is collected, for adapting to the output of different A/D converters, realizes the sampling of digital medium-frequency signal.
In order to ensure the extraction yield for meeting system, 5 grades of the first CIC filtering extractions circuit sampling cascades, and described second
The 6 grades of cascades of CIC filtering extractions circuit sampling.
Further, the cascade series scope of the HB filtering extractions circuit is 1~3.
The present invention remarkable result be：
Circuit structure is simple, easy to control, is 102.4 MSPS (Million samples in input signal sample rate
Per second million extract the/second) when, signal processing bandwidth can in the range of 100Hz~40MHz flexible configuration, correspondence it is defeated
The baseband signal data rate gone out changes in the range of 128SPS~51.2MSPS, extends the signal of existing digital down converter
Process bandwidth.
Brief description of the drawings
Fig. 1 is the schematic block circuit diagram of existing digital down converter；
Fig. 2 is the schematic block circuit diagram of the present invention；
Fig. 3 is the flow chart of data processing figure of digital controlled oscillator (NCO)；
Fig. 4 is the flow chart of data processing figure of CIC filtering extraction circuits；
Fig. 5 is the flow chart of data processing figure of HB filtering extraction circuits；
Fig. 6 is the flow chart of data processing figure of FIR filtering extraction circuits.
Embodiment
The embodiment and operation principle of the present invention are described in further detail below in conjunction with the accompanying drawings.
As shown in Fig. 2, a kind of Digital Down Convert circuit, including data preprocessing module and frequency mixing module, the data are pre-
Processing module includes parallel/serial modular converter, FIFO buffer modules and Logic control module, for adapting to different A/D converters
Output, realize the sampling of digital medium-frequency signal, the frequency mixing module includes digital controlled oscillator, digital controlled oscillator output two-way
Mutually orthogonal local oscillation signal simultaneously realizes Frequency mixing processing with the intermediate-freuqncy signal, and it is defeated to form I roads in the output terminal of the frequency mixing module
Go out and exported with Q roads.
Figure it is seen that Digital Down Convert circuit receives the digital sample number from A/D converter output from input terminal
According to rear, realize that parallel/serial conversion and FIFO are buffered by pretreatment module first, form digital medium-frequency signal.
NCO in figure is digital controlled oscillator, can produce the mutually orthogonal local oscillation signal sin (ω of two-waycAnd cos (ω n)cN), for being mixed with the digital medium-frequency signal X (n) after sampling, to realize the purpose of frequency conversion, its internal processes is shown in
Fig. 3.It is to produce discrete sine signal using look-up table, with 1/f during worksFor periodical input data, a data are often inputted,
The phase accumulator of NCO is increased by a 2 π × fLO/fsPhase increment, then with the phase after cumulative plus shake
(Dither) lookup address of the value as sine table, exports the numerical value on the address, and what is obtained is exactly the sinusoidal sample value of the point,
Wherein fLOFor local oscillating frequency, fsFor the sample frequency of NCO input signals.
Frequency mixer recited above, by the digital local oscillator signal from NCO modules and the digital intermediate frequency sampling signal of input
Carry out mixing calculating, the mutually orthogonal mixed frequency signal I of output I and Q two-way0(n) and Q0(n), i.e.,
I0(n)=X (n) × cos (ωcn)
Q0(n)=X (n) × [- sin (ωcn)]
After mixing, frequency is converted to base band, completes digital intermediate frequency to the frequency spectrum shift of base band.
The data transfer rate of I, Q signal after mixing still be digital intermediate frequency sampling signal sample rate, data transfer rate it is very high, it is necessary into
The extraction of row reduction of speed rate is handled, and to realize undistorted extraction, it is necessary to which optimization design decimation filter is to prevent frequency alias；According to
System requirements, realize the drop data rate processing of total decimation factor D by the way of multi-stage cascade.
Therefore, in the present invention, the I roads output terminal of the frequency mixing module is connected with first in turn respectively with Q roads output terminal
CIC filtering extractions circuit, the 2nd CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extraction circuits, the numerical control
Oscillator, the first CIC filtering extractions circuit, the 2nd CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extractions
Circuit is connected with controller, which is used for realization parameter and the logic control of modules, is filtered in the first CIC
Bypass selecting switch is also associated with extraction circuit, the 2nd CIC filtering extractions circuit and HB filtering extraction circuits, when certain one side
When road selecting switch is connected, the extraction yield of that stage circuit corresponding to the bypass selecting switch is 1.
Two CIC filtering extraction circuits recited above, i.e. CIC1 and CIC2 in Fig. 2, each CIC filtering extractions circuit
According to different application demands, using different cascade numbers, CIC1 here is cascaded using 5 grades of cascades, CIC2 using 6 grades, 5 grades
The internal data process flow of the CIC1 modules of cascade is shown in Fig. 4, what the process flow of the CIC2 modules of 6 grades of cascades was cascaded with 5 grades
CIC1 modules are similar, simply more 1 grade of increases.
By being to the CIC filtering extraction circuit analyses shown in Fig. 4, its impulse response
The system function of multistage cic filter is
Wherein R is delay factor, and general R=1 or 2, M are extracting multiple, and N cascades series for CIC.
The frequency response of multistage cic filter is
I, Q two-way mixed frequency signal of input are filtered first CIC1 filtering extractions circuit and M1Extract, counted again
It is fs/M according to rate1I, Q data, then make second level filtering and M by the 2nd CIC filtering extractions circuit2Extract, counted again
It is f according to rates/(M1×M2) I, Q data, export to next stage HB filtering extraction circuits；Exported after two-stage CIC extractions
Data can obtain the extraction yield of higher, be more conducive to realize extremely narrow process bandwidth；And when needs realize extremely wide processing band
When wide, the arrival next stage module of the data lossless after mixing can be made by setting by-pass switch.
HB filtering extractions circuit recited above, is the module of a multi-stage cascade, and internal data process flow is shown in Fig. 5,
HB filtering extractions circuit has following property：
H(ejω)=1-H (ej(π-ω))
H(ejπ/2)=0.5
HB multi-stage cascade filtering extraction circuits flexibly configurable cascades series N, is adapted for carrying out M3=2NExtraction again, level
Connection series N is generally 1~3；By the processing of HB filtering extraction circuits, the data transfer rate of I, Q two paths of signals of output further drops
It is low, after signal input HB filtering extraction circuits, compared with initial samples rate, fall below fs/(M1×M2×M3)。
As CIC filtering extraction circuits, HB filtering extraction circuits are similarly configured with by-pass switch, can be according to application
Demand is flexibly set, when set HB filtering extraction circuits are bypassed when, the data for being input to HB filtering extraction circuits can be with
Nondestructively export to next stage module.
FIR filtering extractions circuit recited above, main function are to carry out shaping filter, interior data to whole channel
Process flow is shown in Fig. 6, and the frequency response of FIR filtering extraction circuits is
FIR filtering extractions circuit carries out shaping filter and M to the data of input4Extraction again, with CIC filtering extraction circuits
Different with HB filtering extraction circuits, whether FIR filtering extraction circuits do not set by-pass switch, but can set and be extracted, after processing
The data transfer rate of output is down to the f of initial samples rates/(M1×M2×M3×M4)。
By the processing of above CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extraction circuits, input
If sampling signal realizes total decimation factor D=M1×M2×M3×M4Extraction again, and after FIR filtering extraction circuits
To final process bandwidth.
During specific control, the parameter of modules and logic control are realized by controller, with fpga chip
Performance is more and more stronger, and scale is increasing, and average unit cost is more and more lower, and whole circuit can also utilize high speed FPGA to realize, lead to
Cross and the control parameter of modules is adjusted, when input signal sample rate is 102.4 MSPS, signal processing bandwidth can
The flexible configuration in the range of 100Hz~40MHz.
Claims (2)
1. a kind of Digital Down Convert circuit, including data preprocessing module and frequency mixing module, the data preprocessing module are used for
Realize the collection of digital medium-frequency signal, the frequency mixing module includes digital controlled oscillator and frequency mixer, it is characterised in that：The numerical control
Oscillator produces discrete sine signal using look-up table, often inputs a data, the phase accumulator of NCO increase by 2 π ×
fLO/fsPhase increment, the sinusoidal sample of the point is obtained as the lookup address of sine table plus jitter value using the phase after cumulative
This value and cosine sample value, export local oscillation signal, wherein fLOFor local oscillating frequency, fsFor the sample frequency of NCO input signals；
Local oscillation signal and intermediate-freuqncy signal are mixed by the frequency mixer, and the output terminal of frequency mixer includes I roads output terminal and Q roads are defeated
Outlet, I roads output terminal export the mutually orthogonal mixed frequency signal I of two-way respectively with Q roads output terminal0(n) and Q0(n)；
The I roads output terminal of the frequency mixing module is connected with the first CIC filtering extractions circuit, second in turn respectively with Q roads output terminal
CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extraction circuits, the digital controlled oscillator, the first CIC filtering are taken out
Sense circuit, the 2nd CIC filtering extractions circuit, HB filtering extractions circuit and FIR filtering extractions circuit are connected with controller, should
Controller is used for realization parameter and the logic control of modules；
The impulse response of the first CIC filtering extractions circuit and the 2nd CIC filtering extraction circuits is：
The first CIC filtering extractions circuit and the 2nd CIC filtering extractions circuit are multi-stage cascade filter circuit, cic filter
System function be：
<mrow>
<msub>
<mi>H</mi>
<mi>N</mi>
</msub>
<mrow>
<mo>(</mo>
<mi>z</mi>
<mo>)</mo>
</mrow>
<mo>=</mo>
<msup>
<mrow>
<mo>&lsqb;</mo>
<mfrac>
<mn>1</mn>
<mrow>
<mi>M</mi>
<mi>R</mi>
</mrow>
</mfrac>
<mfrac>
<mrow>
<mn>1</mn>
<mo>-</mo>
<msup>
<mi>z</mi>
<mrow>
<mo>-</mo>
<mi>M</mi>
<mi>R</mi>
</mrow>
</msup>
</mrow>
<mrow>
<mn>1</mn>
<mo>-</mo>
<msup>
<mi>z</mi>
<mrow>
<mo>-</mo>
<mn>1</mn>
</mrow>
</msup>
</mrow>
</mfrac>
<mo>&rsqb;</mo>
</mrow>
<mi>N</mi>
</msup>
</mrow>
Wherein R is delay factor, and M is extracting multiple, and N cascades series for CIC；
The frequency response of multistage cic filter is
<mrow>
<msub>
<mi>H</mi>
<mi>N</mi>
</msub>
<mrow>
<mo>(</mo>
<msup>
<mi>e</mi>
<mrow>
<mi>j</mi>
<mi>&omega;</mi>
</mrow>
</msup>
<mo>)</mo>
</mrow>
<mo>=</mo>
<msup>
<mrow>
<mo>&lsqb;</mo>
<mfrac>
<mrow>
<mi>sin</mi>
<mrow>
<mo>(</mo>
<mfrac>
<mrow>
<mi>&omega;</mi>
<mi>M</mi>
</mrow>
<mn>2</mn>
</mfrac>
<mo>)</mo>
</mrow>
</mrow>
<mrow>
<mi>sin</mi>
<mrow>
<mo>(</mo>
<mfrac>
<mi>&omega;</mi>
<mn>2</mn>
</mfrac>
<mo>)</mo>
</mrow>
</mrow>
</mfrac>
<mo>&rsqb;</mo>
</mrow>
<mi>N</mi>
</msup>
<mo>;</mo>
</mrow>
I, Q two-way mixed frequency signal of input are filtered first CIC1 filtering extractions circuit and M1Extract again, obtaining data transfer rate is
fs/M1I, Q data, then make second level filtering and M by the 2nd CIC filtering extractions circuit2Extract again, obtaining data transfer rate is
fs/(M1×M2) I, Q data, export and give HB filtering extraction circuits；
It is also associated with the first CIC filtering extractions circuit, the 2nd CIC filtering extractions circuit and HB filtering extraction circuits
Selecting switch is bypassed, when a certain bypass selecting switch is connected, the extraction of that stage circuit corresponding to the bypass selecting switch
Rate is 1；
When extremely wide process bandwidth is needed, controller is electric by the two CIC filtering extractions circuits and HB filtering extractions of front end
Road is set to bypass, and the FIR filtering extractions circuit is arranged to without extracting；
The data preprocessing module includes parallel/serial modular converter, FIFO buffer modules and Logic control module, for adapting to
The output of different A/D converters, realizes the sampling of digital medium-frequency signal.
A kind of 2. Digital Down Convert circuit according to claim 1, it is characterised in that：The level of the HB filtering extractions circuit
It is 1~3 to join series scope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410581682.XA CN104320088B (en) | 2014-10-27 | 2014-10-27 | A kind of Digital Down Convert circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410581682.XA CN104320088B (en) | 2014-10-27 | 2014-10-27 | A kind of Digital Down Convert circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104320088A CN104320088A (en) | 2015-01-28 |
| CN104320088B true CN104320088B (en) | 2018-04-17 |
Family
ID=52375285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410581682.XA Active CN104320088B (en) | 2014-10-27 | 2014-10-27 | A kind of Digital Down Convert circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104320088B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106817107B (en) * | 2015-12-02 | 2020-07-03 | 北京航天测控技术有限公司 | Iterative decimation filtering device and method for digital down-conversion |
| CN106849905A (en) * | 2017-01-16 | 2017-06-13 | 上海创远仪器技术股份有限公司 | A kind of Network Analyzer filtering algorithm of variable series |
| CN108736901A (en) * | 2017-04-17 | 2018-11-02 | 北京中科晶上科技股份有限公司 | A kind of DDC controllers and corresponding intermediate-freuqncy signal receive processor |
| CN109327203B (en) * | 2018-11-29 | 2022-03-01 | 西安恒盛安信智能技术有限公司 | Digital down-conversion method based on secondary symmetric filtering |
| CN113098515A (en) * | 2020-01-08 | 2021-07-09 | 炬芯科技股份有限公司 | Analog-to-digital conversion system and audio equipment |
| CN113300795B (en) * | 2021-05-20 | 2022-06-14 | 重庆会凌电子新技术有限公司 | Spectrum monitor and control method thereof |
| CN116015248A (en) * | 2022-12-16 | 2023-04-25 | 淮安汇鸿精密模具有限公司 | CIC-HB cascading digital filter and verification method thereof |
| CN117040486B (en) * | 2023-10-07 | 2023-12-19 | 成都玖锦科技有限公司 | Multi-gear digital filter and broadband digital receiver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719769A (en) * | 2009-11-20 | 2010-06-02 | 中国电子科技集团公司第四十一研究所 | Arbitrary extracting and filtering device |
| CN102946229A (en) * | 2012-10-23 | 2013-02-27 | 三维通信股份有限公司 | Digital down conversion implementing method |
| CN103166598A (en) * | 2013-03-01 | 2013-06-19 | 华为技术有限公司 | Digital filter, collocation method of digital filter, electronic device and wireless communication system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7792228B2 (en) * | 2004-03-15 | 2010-09-07 | Samsung Electronics Co., Ltd. | Apparatus and method for digital down-conversion in a multi-mode wireless terminal |
-
2014
- 2014-10-27 CN CN201410581682.XA patent/CN104320088B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719769A (en) * | 2009-11-20 | 2010-06-02 | 中国电子科技集团公司第四十一研究所 | Arbitrary extracting and filtering device |
| CN102946229A (en) * | 2012-10-23 | 2013-02-27 | 三维通信股份有限公司 | Digital down conversion implementing method |
| CN103166598A (en) * | 2013-03-01 | 2013-06-19 | 华为技术有限公司 | Digital filter, collocation method of digital filter, electronic device and wireless communication system |
Non-Patent Citations (2)
| Title |
|---|
| 软件无线电调制解调器的设计;王辉;《中国优秀硕士学位论文全文数据库 信息科技辑》;20100815(第08期);正文第45至54页 * |
| 高速信号采集存储及传输系统的设计与实现;杨振家 等;《电子技术应用》;20120906;第38卷(第09期);第8-10页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104320088A (en) | 2015-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104320088B (en) | A kind of Digital Down Convert circuit | |
| CN104796151B (en) | Sampling rate conversion device and method with continuously variable bandwidth | |
| CN101257482B (en) | Method and device for realizing digital baseband variable velocity to convert modulating system | |
| CN101262240A (en) | An easy-to-realize method and device for full digital frequency conversion | |
| CN102882814B (en) | Parameterized and modularized multi-channel digital down-conversion design platform and parameterized and modularized multi-channel digital down-conversion design method | |
| CN101567701A (en) | High efficient multi-path digital down converter system | |
| CN104393854A (en) | FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof | |
| CN102098005B (en) | Digital down converter and digital upconverter | |
| CN101222213A (en) | Interpolation CIC wave filter based on programmable logic device and its implementing method | |
| CN102403986A (en) | Multi-channel CIC (Cascade Integrator Comb) decimation filter and method for realizing same | |
| CN105281708B (en) | A kind of high speed FIR filter achieving method based on segmentation parallel processing | |
| CN102891662B (en) | A kind of general rate down-conversion, up conversion device and method | |
| CN102946229B (en) | A kind of implementation method of Digital Down Convert | |
| CN101072019B (en) | Wave filter and its filtering method | |
| CN102347768B (en) | Conversion equipment of digital sampling rate and method thereof | |
| CN102361437A (en) | Adaptive low pass filter | |
| CN104320207B (en) | Vector signal analysis device and method | |
| CN204316468U (en) | A kind of multi-path digital filter | |
| CN102638269A (en) | Multiphase frequency conversion circuit | |
| CN104539261B (en) | A kind of interpolation filtering processing method of any sample rate conversion | |
| CN206745358U (en) | A kind of nuclear magnetic resonance digit receiver | |
| CN202043074U (en) | Configurable digital downconverter | |
| CN202978914U (en) | Zero intermediate frequency receiver | |
| CN103475335A (en) | Polyphase digital drop sampling filter | |
| CN203406840U (en) | Polyphase digital downsampling filter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Building 2, No. 25 Qiangwei Road, Changshengqiao Town, Nan'an District, Chongqing, 401336 Patentee after: CHONGQING HUILING ELECTRON NEW TECHNOLOGY Co.,Ltd. Country or region after: China Address before: 401336 No. 7 Camellia Road, Nan'an District, Chongqing Patentee before: CHONGQING HUILING ELECTRON NEW TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| CP03 | Change of name, title or address |