CN107591446B

CN107591446B - Super junction device and manufacturing method thereof

Info

Publication number: CN107591446B
Application number: CN201610530616.9A
Authority: CN
Inventors: 曾大杰; 肖胜安; 李东升
Original assignee: Shenzhen Sanrise Tech Co ltd
Current assignee: Shenzhen Shangyangtong Technology Co ltd
Priority date: 2016-07-07
Filing date: 2016-07-07
Publication date: 2021-01-12
Anticipated expiration: 2036-07-07
Also published as: CN107591446A

Abstract

The invention discloses a super junction device, wherein a super junction structure is formed in a charge flowing area, the super junction device comprises a first primitive cell, the stepping of the first primitive cell is larger than that of a super junction unit, the voltage endurance capacity of the super junction device is increased and the on-resistance is reduced through the stepping of the smaller super junction unit, the area of the super junction structure covered by a plane gate of the first primitive cell is increased through the stepping of the larger first primitive cell, and the input capacitance of the super junction device is improved. The invention also discloses a manufacturing method of the super junction device. The invention can improve the breakdown voltage of the super junction device, reduce the on-resistance, obtain higher Ciss under very low Vds and enable the Ciss to be slowly reduced in a larger Vds range, thereby slowing down the speed of the switching process, effectively reducing the electromagnetic interference performance of the device in an application circuit and reducing the overshoot of Vgs in the switching process from the on state to the off state.

Description

Super junction device and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction (junction) device; the invention also relates to a manufacturing method of the super junction device.

Background

The super junction structure is a structure formed by alternately arranged N-type columns and P-type columns. If a super junction structure is used for replacing an N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided through an N-type column in a conduction state, and the P-type column does not provide the conduction path when the conduction state is conducted; under the cut-off state, the PN upright posts bear the reverse bias voltage together, so that a super-junction Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is formed. The super-junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device.

As shown in fig. 1, is a top view of an existing superjunction device; the general super junction device structure comprises a charge flowing region, a terminal region which is transversely subjected to reverse bias voltage and a transition region which is arranged between the charge flowing region and the terminal region, wherein the terminal region surrounds the periphery of the charge flowing region, and in the figure 1, a region 1 represents the charge flowing region, a region 2 represents the transition region, and a region 3 represents the terminal region.

Region 1 includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and both P-type columns 22 and N-type columns 23 in fig. 1 have a stripe structure. N-type column 23 provides a conduction path when the superjunction device is turned on, and P-type column 22 and N-type column 23 are mutually depleted when the superjunction device is reversely biased to commonly bear a reverse bias.

And the area 2 and the area 3 are positioned at the terminal of the super junction device and are used as a terminal protection structure for representing the super junction device together. The regions 2 and 3 provide no current when the device is turned on, and in a reverse bias state are used to bear a voltage from the surface of the region 1 peripheral cell to the substrate at the outermost end surface of the device, which is a lateral voltage, and a voltage from the surface of the region 1 peripheral cell to the substrate, which is a vertical voltage.

There is at least one P-type ring 25 in region 2, fig. 1 is a P-type ring 25, and the P-type ring 25 is typically connected to the back P-type gate, i.e., P-well, in region 1; a field plate dielectric film with a certain inclined angle is arranged in the region 2, a field plate 24 for alleviating the abrupt change of the surface electric field is also arranged in the region 2, the field plate 24 is a polycrystalline field plate or a metal field plate, and the P-type column 22; the metal field plate may not be provided in region 2.

Region 3 includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and in fig. 1, P-type columns 22 and N-type columns 23 in region 3 are respectively formed by extending and expanding P-type columns 22 and N-type columns 23 in region 1, and the alternately arranged directions are the same. In other configurations, the 3-zone P-type pillars 22 and N-type pillars 23 can also be in an end-to-end ring-type configuration.

A metal field plate is arranged in the region 3, and the metal field plate is not arranged in the region 3; there may or may not be a P-type ring 25 in the 3 region, where the P-type ring is not connected (floating) to the P-type back gate connection of the charge flow region in the presence of the P-type ring 25; and a terminal stop ring 21 is arranged at the outermost end of the 3 region, and the terminal stop ring 21 is composed of an N + injection region or an N + injection region and a medium formed on the N + injection region or the medium and a metal.

As shown in fig. 2, the prior art superjunction device is schematically shown along a cross section of line EF in fig. 1; the super junction device shown in fig. 2 is a planar gate super junction N-type MOSFET device as an example, and the device cell structure is as follows:

an N-type epitaxial layer 31 is formed on the N-type heavily doped silicon substrate 1, and an N-type column 3 and a P-type column 4 are formed in the N-type epitaxial layer 31. The N-type pillars 3 correspond to the N-type pillars 23 in fig. 1, and the P-type pillars 4 correspond to the P-type pillars 22 in fig. 1.

A P-type well 7 is formed at the top of the P-type column 4, a source region 8 consisting of an N + region and a P-well lead-out region 9 consisting of a P + region are formed in the P-type well 7, and a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7.

Further comprising: the interlayer film 10, the contact hole 11, the front metal layer 12 and the front metal layer 12 are patterned to respectively lead out a source electrode and a grid electrode. A back metal layer 13 is formed on the back surface of the silicon substrate 1, and the back metal layer 13 leads out the drain.

Since the silicon substrate 1 is heavily doped and the N-type epitaxial layer 31 is lightly doped, a concentration transition region is formed at the interface of the two.

In fig. 2, an interface E1E2 is the bottom surface of the thinned silicon substrate 1, an interface D1D2 is the top surface of the silicon substrate 1, an interface C1C2 is the bottom interface of the super junction structure, and an interface M1M2 is the top surface of the N-type epitaxial layer 31. The thickness between the interface E1E2 and the interface D1D2 is T00, the thickness between the interface E1E2 and the interface M1M2 is T10, the thickness between the interface C1C2 and the interface M1M2 is T20, and the thickness between the interface D1D2 and the interface C1C2 is T30.

The silicon substrate 1 is a high-concentration base plate, and the resistivity is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 31 is 1ohm cm-2 ohm cm, the thickness T30 is 5 micrometers-20 micrometers, and a P-N column region is a super junction structure region: the height T20 is 35-45 microns when the source-drain breakdown voltage BVds of the corresponding device is 600-700V.

As shown in fig. 2, a polysilicon gate 6 is disposed above each N-type column 3, the polysilicon gate 6 may partially cover the peripheral P-type columns 4 or not, a P-type well 7 is disposed above each P-type column 4, an N + source region 8 is disposed in the P-type well 7, a contact hole 11 is provided, source metal is connected to the source region 8 through the contact hole 11, and metal in the source region 8 is connected to the P-type well 7 through a high-concentration P-well lead-out region 9.

In the prior art, the upper part of a P-type column 4 of a device is connected to an electrode of a source region 8 through a contact hole 11, an N-type column 2 is connected to a drain electrode 13 through an N + substrate, namely a silicon substrate 11, under the condition of lower Vds, namely source-drain voltage, the Vds basically applies a transverse electric field between the P-type column 4 and the N-type column 3, so that under the condition of very low Vds, the alternately arranged P-type column 4 and the N-type column 3 are quickly depleted under the action of the transverse electric field, and capacitors Ciss, Crss and Coss of the device have very large nonlinearity under the condition of small Vds, wherein Ciss is an input capacitor and has the size of Cgs + Cgd; coss is an output circuit, and the size of the output circuit is Cds + Cgd; crss is a reverse transfer capacitance with a size Cgd; cgs is the gate-source capacitance of the device, Cgd is the gate-drain capacitance of the device, and Cds is the source-drain capacitance of the device. The super-junction unit comprises a P-type column 4 and an N-type column 3, the width sum of the P-type column 4 and the N-type column 3 of the super-junction unit is a step of the super-junction structure, the step corresponds to the super-junction structure with the step smaller than 12 microns, generally, when Vds changes from 0V to 10V, Ciss of the super-junction device has a sharp descending process, particularly, the maximum value of Ciss of the super-junction MOSFET is very small because the on-resistance of the super-junction device such as 1/4 to 1/10 of a common VDMOS with the same voltage, and the area of the super-junction MOSFET with the same on-resistance is far smaller than that of the VDMOS, and the maximum value of Ciss generally refers to the Ciss value when Vds is 0V. Due to the existence of the two factors, the super junction MOSFET is easy to generate overshoot of Vgs or too fast switching process due to too low Ciss in the switching process, so that the electromagnetic interference of an application system of the device is large; or the lifetime of the device is shortened due to the overshoot of Vgs.

As shown in fig. 2, during the switching process, except for the stage of the plateau voltage, where the gate voltage is equal to the plateau voltage and Vds is changed, Vgs of the device is substantially in terms of dgvgs/dt ═ Ig/ciss (Vd), where Vgs is the gate voltage (for example Vs ═ 0), Ig is the gate current, and Vd is the drain voltage; since Ciss of the device changes rapidly with Vds, the Ciss of the device becomes very small at a lower voltage Vds, and overshoot of Vgs caused by overlarge Vgs/dt can be caused, dId/dt caused by the overlarge change of Vgs can cause larger electromagnetic interference of a circuit or a system using the device, and the normal operation of the circuit or the system is influenced; in addition to causing ringing of the loop in the application, such an excessively high dgvgs/dt during switching may also cause excessive current and voltage overshoots in the application system, resulting in circuit damage.

Disclosure of Invention

The invention aims to solve the technical problem of providing a super junction device, which can obtain higher Ciss under very low Vds and can enable the Ciss to decline slowly in a larger Vds range, thereby slowing down the speed of a switching process, effectively reducing the electromagnetic interference performance of the device in an application circuit and reducing the overshoot of Vgs in the switching process from a conducting state to a stopping state. Therefore, the invention also provides a manufacturing method of the super junction device.

In order to solve the technical problem, the charge flowing area of the super junction device provided by the invention comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each of the N-type columns and the P-type column adjacent thereto constitute one super junction cell.

The super junction device includes first cells, each of the first cells including:

and the two sides of the plane gate correspond to one P-type column respectively in the width direction of the super junction structure, the P-type columns corresponding to the two sides of the plane gate are made to be P-type columns on the two sides, more than one P-type column is arranged between the two P-type columns on the two sides, and the P-type column is made to be a middle P-type column.

The top of each two sides of the P-type column is provided with a P-type trap, the P-type traps further extend to the tops of the adjacent N-type columns, the P-type traps are covered by the plane gate from the tops, the surface of the P-type traps covered by the plane gate is used for forming a channel, the surface of the P-type traps on the two sides of the plane gate is provided with a source region composed of an N + region, and the source region is self-aligned with the corresponding side face of the plane gate.

And a source region is not formed at the top of each middle P-type column, and the source region and the top of the corresponding P-type well are connected to a source electrode through the same contact hole.

The super junction unit is stepped to the sum of the widths of one N-type column and one P-type column included in the super junction unit, the step of the first primitive cell is the width between the center positions of the two P-type columns on two sides, the step of the first primitive cell is larger than the step of the super junction unit, the voltage withstanding capability of the super junction device is increased and the on-resistance is reduced through the smaller step of the super junction unit, and the area of a super junction structure covered by a plane gate of the first primitive cell is increased through the larger step of the first primitive cell, so that the input capacitance of the super junction device is improved.

The further improvement is that the stepping of the first primitive cell is more than 2 times of the stepping of the super junction unit.

In a further improvement, under the condition of ensuring the charge balance of each super junction unit, the widths of the two side P-type columns and the width of the middle P-type column are the same or different,

in a further improvement, under the condition of ensuring the charge balance of each super junction unit, the doping concentrations of the two side P-type columns and the middle P-type column are the same or different.

In a further improvement, in the width direction of the super junction structure, a P-type well is formed at the top of the middle P-type column of each first cell, and the P-type wells at the top of the middle P-type columns are all connected together in a transverse direction and connected to the P-type wells at the tops of the P-type columns on two sides; in the length direction of the super junction structure, the P-type wells at the tops of the middle P-type columns are in an interval arrangement structure; the interval between the adjacent P-type wells at the top of the middle P-type column of each first cell is greater than or equal to 12 micrometers.

In a further improvement, a plurality of contact holes are formed at the top of the middle P-type column of each first cell and connected to the source electrode through the contact holes; and the interval between two adjacent contact holes at the top of the middle P-type column of each first primitive cell is greater than or equal to 12 micrometers.

In order to solve the technical problem, the method for manufacturing the super junction device provided by the invention comprises the following steps:

forming a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns in a charge flowing region; each of the N-type columns and the P-type column adjacent thereto constitute one super junction cell.

And step two, forming a P-type well in the selected area of the super junction structure.

Forming a planar gate, and forming a source region consisting of an N + region on the surface of the P-type well at two sides of the planar gate; the source region and the corresponding side face of the planar gate are self-aligned.

The super junction device comprises a first cell, wherein the P-type trap and the planar gate are arranged according to the structure of the first cell:

in the width direction of the super junction structure, two sides of the planar gate respectively correspond to one P-type column, the P-type columns corresponding to the two sides of the planar gate are two-side P-type columns, more than one P-type column is arranged between the two-side P-type columns, and the P-type column is a middle P-type column.

And a P-type well is formed at the top of each two-side P-type column, the P-type well also extends to the top of the adjacent N-type column, the P-type well is covered by the planar gate from the top, and the surface of the P-type well covered by the planar gate is used for forming a channel.

And a source region is not formed at the top of each middle P-type column, and the source region and the top of the corresponding P-type well are connected to a source electrode through the same contact hole formed subsequently.

The further improvement is that the method also comprises the following steps:

and step four, forming an interlayer film.

Step five, forming a contact hole; the contact hole penetrates the interlayer film.

And sixthly, forming a front metal layer and patterning the front metal layer by adopting a photoetching process to form a source electrode and a grid electrode, wherein the source region and the P-type well are connected to the source electrode through contact holes with the same tops, and the planar grid is connected to the grid electrode through the contact hole on the top.

In a further improvement, under the condition of ensuring the charge balance of each super junction unit, the width of the middle P-type column is greater than or equal to the width of the two side P-type columns.

In a further improvement, under the condition of ensuring the charge balance of each super junction unit, the doping concentration of the middle P-type column is less than or equal to that of the two side P-type columns.

In the prior art, the structure of the super junction device with the cells stepped by the same step as that of the super junction unit, that is, the complete structure of a set of cells is formed at the top of each super junction unit, includes: the stepping of the primitive cell is limited by the stepping of the super junction unit, in order to improve the breakdown voltage of the super junction device and reduce the on-resistance, the stepping of the super junction unit needs to be smaller and smaller, and thus the whole super junction structure is more easily exhausted, so that the breakdown voltage can be improved and the on-resistance can be reduced; however, after the step of the primitive cell is reduced, the area covered by the polysilicon gate of the primitive cell is reduced, the super junction unit is more easily depleted after the step is reduced, that is, the super junction structure is depleted at a lower source-drain voltage, that is, Vds, the input voltage of the device, that is, Ciss, is related to the area of the polysilicon gate and the size of the depleted area of the super junction unit at the bottom, and the reduction in area and the rapid increase in depletion region of the low source-drain voltage make Ciss smaller and rapidly smaller.

The super junction device is provided with the first primitive cell, the stepping of the first primitive cell is not the same as the stepping of the super junction unit, but the stepping of the first primitive cell is set to be larger than the stepping of the super junction unit, so that the stepping size of the first primitive cell and the stepping size of the super junction unit can be set according to requirements.

According to the super junction device and the manufacturing method thereof, the step size of the super junction unit is reduced, so that the breakdown voltage of the super junction device can be improved, and the on-resistance can be reduced.

The area covered by the plane gate of the first primitive cell, namely the area covered by the polysilicon gate, can be increased by increasing the step of the first primitive cell, so that the area of Ciss can be increased, namely the value of Ciss of the first primitive cell can be increased.

For the whole super junction device, the first primitive cell is arranged, so that higher Ciss can be obtained under very low Vds, and Ciss can be slowly reduced in a larger Vds range, so that the speed of a switching process can be reduced, the electromagnetic interference performance of the device in an application circuit can be effectively reduced, and the overshoot of Vgs in the switching process from a conducting state to a stopping state can be reduced; and meanwhile, the breakdown voltage of the super junction device can be improved, and the on-resistance can be reduced.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

fig. 1 is a schematic top view of an existing superjunction device;

fig. 2 is a schematic cross-sectional view of an existing superjunction device;

fig. 3 is a schematic cross-sectional view of a superjunction device according to an embodiment of the present invention;

fig. 4 is a schematic top view of a superjunction device according to an embodiment of the present invention;

fig. 5 is a simulation curve of Ciss and Vds of a superjunction device in accordance with an embodiment of the present invention;

fig. 6 is a schematic cross-sectional view of a second superjunction device of an embodiment of the present invention;

fig. 7 is a schematic top view of a superjunction device according to a second embodiment of the present invention;

fig. 8 is a schematic top view of a six superjunction device of an embodiment of the present invention;

fig. 9 is a schematic top view of a seven superjunction device of an embodiment of the present invention.

Detailed Description

The embodiment of the invention discloses a super junction device:

fig. 3 is a schematic cross-sectional view of a superjunction device according to an embodiment of the present invention; fig. 4 is a schematic top view of a superjunction device according to an embodiment of the present invention; a super junction device according to an embodiment of the present invention also includes a charge flowing region, a terminal region that laterally bears a reverse bias voltage, and a transition region located between the charge flowing region and the terminal region, where the terminal region surrounds an outer periphery of the charge flowing region, and includes the entire charge flowing region, the transition region, and the terminal region, as shown in fig. 1, where region 1 in fig. 1 represents the charge flowing region, region 2 represents the transition region, and region 3 represents the terminal region. The first super junction device in the embodiment of the present invention is mainly characterized in that a structure in a charge flowing region is improved, the first super junction device in the embodiment of the present invention is described by taking an N-type super junction MOSFET device as an example, and in the first embodiment of the present invention:

the charge flowing region comprises a super junction structure consisting of a plurality of N-type columns 3 and P-type columns 4 which are alternately arranged; each of the N-type columns 3 and the P-type columns 4 adjacent thereto constitute one super junction cell. The super junction structure is formed in an N-type epitaxial layer 31, and the N-type epitaxial layer 31 is formed on an N-type heavily doped silicon substrate 1.

The silicon substrate 1 is a high-concentration base plate, and the resistivity is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 31 is 1-2 ohm cm, the thickness is 5-20 microns, and the P-N column region is a super junction structure region: when the source-drain breakdown voltage BVds of the corresponding device is 600V-700V, the height of the super junction structure is 35 micrometers-45 micrometers.

the planar gate 6 is a polysilicon gate, and a gate dielectric layer such as a gate oxide layer 5 is isolated between the planar gate 6 and the surface of the super junction structure at the bottom. In the width direction of the super junction structure, two sides of the planar gate 6 respectively correspond to one P-type column 4, the P-type columns 4 corresponding to the two sides of the planar gate 6 are the two P-type columns 4, one P-type column 4 is arranged between the two P-type columns 4 on the two sides, and the P-type column 4 is a middle P-type column 4 a. In fig. 3, for convenience of illustration, the middle P-type columns are individually marked with a mark 4a, and the two side P-type columns are also marked with a mark 4.

A P-type well 7 is formed at the top of each P-type column 4 on two sides, the P-type well 7 also extends to the top of the adjacent N-type column 3, the P-type well 7 is covered by the planar gate 6 from the top, the surface of the P-type well 7 covered by the planar gate 6 is used for forming a channel, a source region 8 consisting of an N + region is formed on the surface of the P-type well 7 on two sides of the planar gate 6, and the source region 8 is self-aligned with the corresponding side surface of the planar gate 6.

No source region 8 is formed on the top of each of the intermediate P-type columns 4a, and no P-type well 7 is formed. The source electrode composed of a front metal layer 12 is connected to the tops of the source regions 8 and the corresponding P-type wells 7 through the same contact holes 11; the contact hole 11 passes through the interlayer film 10. A contact hole 11 is also formed at the top of the planar gate 6 and connected to the gate electrode composed of the front metal layer 12 through the contact hole 11.

The super junction unit is stepped to the sum of the widths of the N-type column 3 and the P-type column 4, and the step of the first primitive cell is the width between the center positions of the two P-type columns 4 on the two sides. As known to those skilled in the art, the unit cell is a minimum period unit of the super junction device having a periodic arrangement structure, a super junction device according to an embodiment of the present invention may use the first unit cell to perform periodic arrangement, in fig. 3, a device unit cell region whose lateral position is located between dotted lines corresponding to

marks

101 and 102 corresponds to one first unit cell, and the

marks

101 and 102 are respectively located at central positions of two P-type pillars 4 on two sides of the same planar gate 6.

As shown in fig. 3, the step of the first primitive cell is larger than the step of the super junction unit, and the step of the first primitive cell in the first embodiment of the present invention is twice the step of the super junction unit, that is, the first primitive cell in the first embodiment of the present invention laterally covers two P-type pillars 4 and two N-type pillars 3. The voltage endurance capability of the super junction device is increased and the on-resistance is reduced by the smaller stepping of the super junction unit, and the area of the super junction structure covered by the planar gate 6 of the first cell is increased by the larger stepping of the first cell, so that the input capacitance of the super junction device is improved.

In the first embodiment of the present invention, under the condition that the charge balance of each super junction unit is ensured, the widths of the P-type columns 4 on the two sides are the same as the width of the middle P-type column 4a, and the doping concentrations of the P-type columns 4 on the two sides and the middle P-type column 4a are the same.

Fig. 3 is a cross-sectional view taken along line AA ' in fig. 4, and it can be seen also in the top view corresponding to fig. 4 that P-type columns 4 and N-type columns 3 are alternately arranged in the direction corresponding to the width direction AA ', N is marked in N-type columns 3 to represent N-type doping, one planar gate 6 corresponds to one first primitive cell, and it can be seen that the area of one planar gate 6 in the direction along AA ' is larger than the super junction unit composed of one N-type column 3 and one P-type column 4. In fig. 4, the P-type pillars 4 are subdivided into two side P-type pillars 4 and a middle P-type pillar 4a according to the overlay relationship with the planar gate 6, the two side P-type pillars 4 being P-type doped with P1, and the middle P-type pillar 4a being P-type doped with P2. In the first embodiment of the present invention, the planar gate 6 covers one middle P-type pillar 4a and the N-type pillars 3 on both sides of the middle P-type pillar 4a in the width direction, and extends to the P-type wells 7 formed on the tops of the two P-type pillars 4 on both sides, and covers the corresponding P-type wells 7 on both sides of the planar gate 6 and forms a channel on the surface of the P-type well 7. The P-type wells 7 on the tops of the two P-type columns 4 extend to the tops of the adjacent N-type columns 3, and source regions 8 and contact holes 11 are formed on the surfaces of the P-type wells 7 on the tops of the two P-type columns 4. The planar gate 6 is continuously distributed in the length direction of the super junction structure, i.e., in the direction perpendicular to the AA' line, and the wavy line 103 indicates that the continuously distributed portion is omitted in the middle. In the first embodiment of the present invention, a contact hole 11a for leading out the middle P-type column 4a is formed on the outer side of the super junction device, that is, the outer side of the planar gate 6.

As can be seen from fig. 3 and 4, Ciss of the device increases due to the increased coverage ratio of the planar gate 6; since the middle P-type pillar 4a is covered by the planar gate 6 and there is no P-well with relatively high concentration thereon, and the potential of the middle P-type pillar 4a is not fixed at the same potential as the source region by other means, the depletion rate of the middle P-type pillar 4a will be slow, and thus Ciss will change more slowly with Vds.

Fig. 5 shows simulation curves of Ciss and Vds of a superjunction device according to an embodiment of the present invention; curve 202 corresponds to the Ciss and Vds simulation curves for the superjunction device of the first embodiment of the present invention; for comparison, curve 201 corresponds to the simulation curves for Ciss and Vds for the existing superjunction device shown in fig. 2. The simulation parameters are as follows: the width of the P-type column 4 is 5 microns, the width of the N-type column 3 is 6 microns, the resistivity of the N-type column is 2 ohm-cm, the concentration of the P-type column 4 enables the P-type column 4 and the N-type column 3 to keep charge balance, and the thickness of the gate oxide layer 5 is 1000 angstroms. In fig. 2, the width of the planar gate 6 is 7 micrometers, in fig. 3, the width of the planar gate 6 is 18 micrometers, and a CV curve is simulated in a region with a width of 16.5 micrometers and a length of 1 micrometer, so as to obtain a dependence curve of Ciss and Vds shown in fig. 5, and it can be seen from fig. 5 that:

the Ciss for the first embodiment of the invention, corresponding to curve 202, is significantly larger than the Ciss of the prior art around Vds-0.

The Ciss of the first embodiment of the invention is larger than that of the prior art within the Vds range of 0V-20V, and the decrease of the Ciss of the first embodiment of the invention is basically linear, while the Ciss of the prior art has a sharp decrease range between 0V-10V.

For the simulation parameters corresponding to fig. 5, the P-N column, i.e., the super junction unit composed of one P-type column 4 and one N-type column 3, is completely depleted in charge by about 28 volts; or, in the process of Vds being 0V to 20V, the change of the depletion region in the switching process of the device is substantially completed physically, so that the structure of the first embodiment of the present invention has a larger Ciss in the region, i.e., the range of Vds being 0V to 20V, and therefore, the switching performance of the device can be improved well.

Second super junction device of the embodiment of the invention:

fig. 6 is a schematic cross-sectional view of a second superjunction device according to an embodiment of the present invention; fig. 7 is a schematic top view of a superjunction device according to a second embodiment of the present invention; the second super junction device of the embodiment of the present invention is different from the first super junction device of the embodiment of the present invention in that:

two middle P-type columns 4a are included between the two side P-type columns 4, that is, the planar gate 6 covers the two middle P-type columns 4a, and since the two middle P-type columns 4a further include one N-type column 3, the first primitive cell of the second superjunction device of the embodiment of the present invention includes 3P-type columns 4 and 3N-type columns 3, that is, the step of the first primitive cell is 3 times that of the superjunction unit. So that the area covered by the planar grating 6 is even larger.

The embodiment of the invention provides a triple super junction device:

the three-super-junction device of the embodiment of the invention is different from the one-super-junction device of the embodiment of the invention in that: under the condition of ensuring the charge balance of each super junction unit, the doping concentrations of the two side P-type columns 4 and the middle P-type column 4a are different. When the middle P-type columns 4a are plural, since a current of a channel does not flow through the N-type columns 2 between the middle P-type columns 4a, the influence of the middle P-type columns 4a on the on-resistance and the breakdown voltage of the super junction device is not large as compared with the two side P-type columns 4, and thus the doping concentration of the middle P-type columns 4a can be set to be different from the doping concentration of the two side P-type columns 4. Preferably, the doping concentration of the middle P-type column 4a can be set to be smaller than the doping concentrations of the two side P-type columns 4, so that a better withstand voltage can be realized without affecting on-resistance.

The four super junction devices of the embodiment of the invention:

the four super junction device of the embodiment of the present invention is different from the one super junction device of the embodiment of the present invention in that: under the condition that the charge balance of each super junction unit is ensured, the width of the two side P-type columns 4 and the width of the middle P-type column 4a are different. When the middle P-type column 4a has a plurality of columns, since a current of a channel does not flow through a region between the middle P-type columns 4a, the influence of the middle P-type column 4a on the on-resistance and breakdown voltage of the super junction device is not large as that of the two side P-type columns 4, so that the width of the middle P-type column 4a can be set to be different from the width of the two side P-type columns 4. Preferably, the width of the middle P-type pillar 4a can be set to be greater than the width of the two side P-type pillars 4, so that the formation process of the middle P-type pillar 4a is simpler.

The five super junction devices of the embodiment of the invention:

the five super junction device of the embodiment of the present invention is different from the one super junction device of the embodiment of the present invention in that: the P-type well 7 is formed in a partial region or in the entire region of the top of each of the intermediate P-type pillars 4 a.

The six super junction devices of the embodiment of the invention:

the six super junction device according to the embodiment of the present invention is different from the one super junction device according to the embodiment of the present invention in that, as shown in fig. 8, in the six super junction device according to the embodiment of the present invention:

in the width direction of the super junction structure, namely along the direction AA', a P-type well 7a is formed at the top of the middle P-type column 4a of each first cell, and the P-type wells 7a at the top of the middle P-type columns 4a are all connected together in the transverse direction and connected to the P-type wells 7 at the tops of the P-type columns 4 at two sides; in the length direction of the super junction structure, i.e., in the direction perpendicular to AA', the P-type wells 7a at the top of each of the intermediate P-type columns 4a are in a spaced arrangement. By providing the P-type well 7a connecting the P-type columns 4, the hole collecting capability can be improved, and the EAS capability, which is the single-pulse avalanche breakdown energy and represents the impact resistance, can be improved.

Preferably, a distance d1 in fig. 8 between the adjacent P-type wells 7a at the top of the middle P-type pillar 4a of each first cell is greater than or equal to 12 μm.

The seven super junction device of the embodiment of the invention comprises:

the seven super junction device according to the embodiment of the present invention is different from the one super junction device according to the embodiment of the present invention in that, as shown in fig. 9, in the seven super junction device according to the embodiment of the present invention:

a plurality of contact holes 11b are formed at the top of the middle P-type pillar 4a of each of the first cells and connected to the source electrode through the contact holes 11 b; this can improve the hole collecting capability and thus the EAS capability.

Preferably, the interval between two adjacent contact holes 11 on the top of the middle P-type pillar 4a of each first cell is greater than or equal to 12 μm.

The method for manufacturing the super junction device of the embodiment of the invention is used for manufacturing the super junction devices of the first to seventh embodiments of the invention, and comprises the following steps:

step one, forming a super junction structure consisting of a plurality of alternately arranged N-type columns 3 and P-type columns 4 in a charge flowing area; each of the N-type columns 3 and the P-type columns 4 adjacent thereto constitute one super junction cell.

And step two, forming a P-type well 7 in the selected area of the super junction structure.

Forming a planar gate 6, and forming a source region 8 consisting of an N + region on the surface of the P-type well 7 at two sides of the planar gate 6; the source region 8 and the corresponding side of the planar gate 6 are self-aligned;

the super junction device comprises a first cell, wherein the P-type well 7 and the plane gate 6 are arranged according to the structure of the first cell:

in the width direction of the super junction structure, two sides of the planar gate 6 respectively correspond to one P-type column 4, the P-type columns 4 corresponding to the two sides of the planar gate 6 are two-side P-type columns 4, more than one P-type column 4 is arranged between the two-side P-type columns 4, and the P-type column 4 is a middle P-type column 4 a.

A P-type well 7 is formed at the top of each two-side P-type column 4, the P-type well 7 further extends to the top of the adjacent N-type column 3, the P-type well 7 is covered by the planar gate 6 from the top, and the surface of the P-type well 7 covered by the planar gate 6 is used for forming a channel.

No source region 8 is formed on the top of each intermediate P-type column 4a, and the source region 8 and the corresponding P-type well 7 are connected to the source electrode through the same contact hole 11 formed later on the top.

The super junction unit is stepped to the sum of the widths of one N-type column 3 and one P-type column 4, the first primitive cell is stepped to the width between the center positions of the two P-type columns 4 on two sides, the stepping of the first primitive cell is larger than that of the super junction unit, the voltage withstanding capability of the super junction device is increased and the on resistance of the super junction device is reduced through the smaller stepping of the super junction unit, and the area of a super junction structure covered by a planar gate 6 of the first primitive cell is increased through the larger stepping of the first primitive cell, so that the input capacitance of the super junction device is improved.

Preferably, under the condition of ensuring the charge balance of each super junction unit, the width of the middle P-type column 4a is greater than or equal to the width of the two side P-type columns 4. The wider intermediate P-type columns 4a are more easily formed.

Under the condition of ensuring the charge balance of each super junction unit, the doping concentration of the middle P-type column 4a is less than or equal to that of the two side P-type columns 4.

Also comprises the following steps:

and step four, forming the interlayer film 10.

Step five, forming a contact hole 11; the contact hole 11 passes through the interlayer film 10.

And sixthly, forming a front metal layer 12 and patterning the front metal layer 12 by adopting a photoetching process to form a source electrode and a grid electrode, wherein the source region 8 and the P-type well 7 are connected to the source electrode through a contact hole 11 with the same top, and the planar grid 6 is connected to the grid electrode through the contact hole 11 with the same top.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. A super junction device, characterized in that:

the charge flowing region comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; on a plane of depression, each P-type column and each N-type column are in a strip structure;

the two sides of the plane gate correspond to one P-type column respectively in the width direction of the super junction structure, the P-type columns corresponding to the two sides of the plane gate are two-side P-type columns, more than one P-type column is arranged between the two-side P-type columns, and the P-type column is a middle P-type column;

a P-type well is formed at the top of each P-type column on two sides, the P-type well further extends to the top of the adjacent N-type column, the P-type well is covered by the planar gate from the top, the surface of the P-type well covered by the planar gate is used for forming a channel, a source region composed of an N + region is formed on the surface of the P-type well on two sides of the planar gate, and the source region is self-aligned with the corresponding side face of the planar gate;

connecting the source region and the top of the corresponding P-type well to a source electrode through the same contact hole; a source region is not formed at the top of each middle P-type column, and the potential of each middle P-type column is a floating structure which is not fixed relative to the potential of the source region;

2. The superjunction device of claim 1, wherein: the stepping of the first primitive cell is more than 2 times of that of the super junction unit.

3. The superjunction device of claim 1, wherein: under the condition of ensuring the charge balance of each super junction unit, the widths of the two side P-type columns and the width of the middle P-type column are the same or different.

4. The superjunction device of claim 1, wherein: under the condition of ensuring the charge balance of each super junction unit, the doping concentrations of the two side P-type columns and the middle P-type column are the same or different.

5. The superjunction device of claim 1, wherein: in the width direction of the super junction structure, a P-type well is formed at the top of the middle P-type column of each first unit cell, and the P-type wells at the tops of the middle P-type columns are transversely connected together and connected to the P-type wells at the tops of the P-type columns on two sides; in the length direction of the super junction structure, the P-type wells at the tops of the middle P-type columns are in an interval arrangement structure.

6. The superjunction device of claim 5, wherein: the interval between the adjacent P-type wells at the top of the middle P-type column of each first cell is greater than or equal to 12 micrometers.

7. The superjunction device of claim 1, wherein: a plurality of contact holes are formed at the top of the middle P-type pillar of each of the first cells and connected to the source electrode through the contact holes.

8. The superjunction device of claim 7, wherein: and the interval between two adjacent contact holes at the top of the middle P-type column of each first primitive cell is greater than or equal to 12 micrometers.

9. A method for manufacturing a super junction device is characterized by comprising the following steps:

forming a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns in a charge flowing region; each N-type column and the adjacent P-type column form a super junction unit; on a plane of depression, each P-type column and each N-type column are in a strip structure;

step two, forming a P-type well in a selected area of the super junction structure;

forming a planar gate, and forming a source region consisting of an N + region on the surface of the P-type well at two sides of the planar gate; the source region and the corresponding side surface of the planar gate are self-aligned;

in the width direction of the super junction structure, two sides of the planar gate respectively correspond to one P-type column, the P-type columns corresponding to the two sides of the planar gate are two-side P-type columns, more than one P-type column is arranged between the two-side P-type columns, and the P-type column is a middle P-type column;

a P-type well is formed at the top of each two-side P-type column, the P-type well further extends to the top of the adjacent N-type column, the P-type well is covered by the planar gate from the top, and the surface of the P-type well covered by the planar gate is used for forming a channel;

connecting the source region and the top of the corresponding P-type well to a source electrode through the same contact hole formed subsequently; a source region is not formed at the top of each middle P-type column, and the potential of each middle P-type column is a floating structure which is not fixed relative to the potential of the source region;

10. A method of manufacturing a superjunction device according to claim 9, further comprising the steps of:

step four, forming an interlayer film;

step five, forming a contact hole; the contact hole penetrates through the interlayer film;

11. A method of manufacturing a superjunction device of claim 9, wherein: under the condition of ensuring the charge balance of each super junction unit, the width of the middle P-type column is larger than or equal to the width of the P-type columns on the two sides.

12. A method of manufacturing a superjunction device of claim 9, wherein: under the condition of ensuring the charge balance of each super junction unit, the doping concentration of the middle P-type column is less than or equal to that of the P-type columns on the two sides.