CN107577965B - A kind of FPGA encryption method of gate delay difference - Google Patents

Abstract

The present invention relates to a kind of FPGA encryption methods of gate delay difference, are related to time and frequency measurement technical field.The invention proposes a kind of FPGA encryption method, this method is theoretical basis, realization to FPGA program encryption using FPGA itself gate delay difference, can not only save development cost, while improving circuit integration degree, reducing circuit power consumption.

Description

A kind of FPGA encryption method of gate delay difference

Technical field

The present invention relates to time and frequency measurement technical fields, and in particular to a kind of FPGA encryption method of gate delay difference.

Background technique

Semiconductor technology is constantly progressive, and has driven the fast development of chip technology, field programmable gate array (Field Programmable Gate Array, FPGA) become this field outstanding person, FPGA is as a kind of programmable logic device Part is the product further to grow up on the basis of the Programmables such as PAL, GAL, CPLD, is led as specific integrated circuit One of domain semi-custom circuit and occur.The birth of FPGA had not only solved the deficiency of custom circuit, but overcome it is original can The shortcomings that programming device gate circuit limited amount, has in fields such as computer hardware, communication, aerospace and automotive electronics It is widely applied.

Currently, occur many encryption methods for being directed to FPGA in industry, as based on SRAM encryption, based on CPLD Encryption [application number: 201410603250.4] [application number: 201420643533.7] etc., these encryption methods are all by borrowing Third party's Encryption Tool is helped to achieve the purpose that encryption.The introducing of third party's Encryption Tool not only increases development cost, and And circuit volume and power consumption are increased, in electronic circuit integrated higher and higher today, reduces circuit volume, reduces power consumption It has been trend of the times.

Summary of the invention

(1) technical problems to be solved

The technical problem to be solved by the present invention is how to realize the encryption to FPGA program.

(2) technical solution

In order to solve the above-mentioned technical problems, the present invention provides a kind of FPGA encryption methods of gate delay difference, including with Lower step:

Step 1 generates single pulse signal: after system electrification, FPGA generates a single pulse signal；

Step 2, pulse detection: the single pulse signal is divided into PULSE1 and PULSE2 two-way, and PULSE2 directly inputs arteries and veins It rushes detection module to detect pulse and record at the time of be detected, PULSE1 inputs another again after time delay module A pulse detection module is detected, and is recorded at the time of be detected；

Step 3, calculating pulse delay are poor: counter is calculated and is made to the time pulse signal difference detected twice Delay input comparison module is obtained after respective handling, the delay is compared with the delay that measuring instrument measures for comparison module, root Corresponding id signal is generated according to comparison result；

Step 4, encryption target program: the encrypted target program of id signal input, it is whether effective according to id signal Whether determination procedure runs, and achievees the purpose that encryption.

Preferably, in step 1, after system electrification, clock signal clk 0 is also generated by external crystal-controlled oscillation, CLK0 is through FPGA Sampling clock CLK is generated after internal PLL frequency multiplication, if its period is T_CLK；It is 100ns that FPGA, which generates a pulsewidth, at the same time The single pulse signal.

Preferably, in step 2, time delay module is made of several cascade NOT gates, is delayed to PULSE1；Detection The pulse detection module of PULSE2 constantly detects the rising edge of PULSE2 using sampling clock CLK, and rising edge is stood once arriving That is starting counter starts counting；And the pulse detection module for detecting PULSE1 is constantly detected using sampling clock CLK The rising edge of PULSE1, rising edge stop counter once arriving immediately, it is assumed that the count value of counter is N, then be delayed mould Delay T of the block to pulse signal_DIt indicates are as follows:

T_D=N × T_CLK (1)。

Preferably, in step 3, delay value T that counter obtains_DIt is input to and is measured with measuring instrument in comparison module, done Value T after correcting process_D’It is compared, judges whether two values are equal, if T_D=T_D’, then id signal Flag is effective, it is on the contrary then In vain.

Preferably, in step 4, control variable of the marking signal Flag as encrypted target program, when it is effective When, otherwise encrypted target program operation does not run, realizes the encryption to program.

(3) beneficial effect

The invention proposes a kind of FPGA encryption methods, and this method is using FPGA itself gate delay difference as theoretical basis, reality Now to FPGA program encryption, development cost can be not only saved, while improving circuit integration degree, reducing circuit power consumption.

Detailed description of the invention

Fig. 1 is method broad flow diagram of the invention；

Fig. 2 is Method And Principle block diagram of the invention；

Fig. 3 is the logical flow chart of the embodiment of the present invention；

Fig. 4 is delay figure of mono- NOT gate of FPGA1 to signal；

Fig. 5 is delay figure of the FPGA1 100 cascade NOT gates to signal；

Fig. 6 is delay figure of the FPGA1 1000 cascade NOT gates to signal；

Fig. 7 is delay figure of the FPGA2 1000 cascade NOT gates to signal；

Fig. 8 is delay figure of the FPGA3 1000 cascade NOT gates to signal.

Specific embodiment

To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention Specific embodiment is described in further detail.

Discovery is largely tested, a NOT gate is about 0.3ns-0.4ns to the delay of signal in FPGA, when in FPGA When several NOT gates of portion cascade, the delay to signal is not each non-simple linear superposition of gate delay, different FPGA The cascade NOT gate of internal identical quantity has differences the delay of signal, and the size of difference depends on the quantity of cascade NOT gate. Fig. 4-Fig. 8 is that the different FPGA measured using precise time-time-interval measuring instrument MTIM712 cascade NOT gate to the delay feelings of signal Condition.Three FPGA devices FPGA1, FPGA2 and FPGA3 used in experiment are all that altera corp's CycloneII series is same Batch chip one by one, measuring instrument MTIM712 measurement accuracy are 100ps.

From Fig. 6-Fig. 8 as it can be seen that FPGA1, FPGA2, FPGA3 are at 1000 if being delayed using the average value of delay as standard The delay measured under cascade NOT gate is respectively 371.3ns, 357.8ns, 365.6ns.It can be seen that identical series and batch, no Even if with FPGA inside possess the cascade NOT gate of identical quantity, it is also different to the delay of signal.

Based on above-mentioned discovery, the invention proposes one kind using FPGA itself gate delay difference as theoretical basis, realization pair The method of FPGA program encryption, encryption method implementation process is as shown in Fig. 1 to Fig. 3.

Step 1: system electrification, the clock signal clk 0 that external crystal-controlled oscillation generates generate height after the PLL frequency multiplication inside FPGA Frequency sampling clock CLK, if its period is T_CLK；FPGA generates the pulse signal that a pulsewidth is 100ns at the same time；

Step 2: pulse signal is divided into PULSE1 and PULSE2 two-way: PULSE1 input time delay module, if time delay module by Dry cascade NOT gate composition, is delayed to PULSE1；PULSE2 is then directly inputted to pulse detection module 1, pulse detection module 1 constantly detects the rising edge of PULSE2 using high frequency sampling clock CLK, and rising edge starts counter immediately and start once arriving It counts；

Step 3:PULSE1 is input to pulse detection module 2 and is detected after time delay module；2 benefit of pulse detection module The rising edge of PULSE1 is constantly detected with high frequency sampling clock CLK, rising edge stops counter once arriving immediately.Assuming that meter The count value of number device is N.Then delay T of the time delay module to pulse signal_DIt can indicate are as follows:

T_D=N × T_CLK (1)

Step 4: the delay value T that counter obtains_DBe input to it is being measured in judgment module with measuring instrument, do correcting process The value T obtained after (rounding up)_D’It is compared, judges whether two values are equal.If T_D=T_D’, then id signal Flag is effective, It is on the contrary then invalid.

Step 5: control variable of the marking signal Flag as encrypted target program, it is encrypted when it is effective Target program operation, does not otherwise run, and realizes the encryption to program.

Since same order connection NOT gate is different to the delay of signal inside any FPGA, and each FPGA corresponds to certain One unique delay value, therefore when being encrypted to different FPGA, encipheror can be variant.Such as cascading NOT gate is 1000 When, the delay of FPGA1, FPGA2, FPAGA3 are respectively 371.3ns, 357.8ns, 365.6ns, therefore when being encrypted, are sentenced It is used in disconnected module and T_DThe value T compared_D’It should be 371.3ns, 357.8ns, 365.6ns respectively.

The main reason for amendment delay is the limitation that any FPGA device has maximum operation frequency, sample clock frequency Can not be infinitely great, the amendment of delay will directly affect the success or failure of encryption.

It is above-mentioned to measure under 1000 cascade NOT gates, the delay of FPGA1, FPGA2, FPAGA3 be respectively 371.3ns, 357.8ns,365.6ns.If sampling clock is 500MHz, then its resolution ratio is 2ns, therefore the delay measured using the clock It can not be equal with delay 371.3ns, 357.8ns, 365.6ns that measuring instrument MTIM712 is measured.Therefore it is to the amendment of delay The essential link of this encryption method.By above-mentioned delay 371.3ns, 357.8ns, 365.6ns be modified to respectively 372ns, After 358ns, 366ns, the delay value counted to get using 500MHz sampling clock can be equal to it.

Encryption method of the invention can not only save development cost, while improving circuit integration degree, reducing electricity Road power consumption, encryption method of the invention are verified on a plurality of FPGA products, have important reality in field of engineering technology With value.

The success or failure of encryption will be influenced by certain objective factors, mainly there is following two o'clock:

1) sample clock frequency.Sample clock frequency is an important factor for influencing this encryption method.Work as sample clock frequency When for 100MHz, resolution ratio is only 10ns, can only distinguish between the delay of 10ns or more；When sample clock frequency is 1GHz, differentiate Rate is 1ns, then can distinguish the delay of 1ns or more.Therefore, sample clock frequency is higher, and resolution ratio is higher, then can more distinguish Small delay.

2) FPGA aging.FPGA aging is also to influence another potential factor of encryption success or failure, with the FPGA length of service Increase, internal circuit structure aging phenomenon will occurs, and also will appear a degree of offset to the delay of signal.Currently Encrypt successful program, after a certain time of operation, may due to device aging and lead to program cisco unity malfunction, Need re-encrypted.

The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improve and become Shape also should be regarded as protection scope of the present invention.

Claims (9)

1. a kind of FPGA encryption method of gate delay difference, which comprises the following steps:

Step 1 generates single pulse signal: after system electrification, FPGA generates a single pulse signal；

Step 2, pulse detection: the single pulse signal is divided into PULSE1 and PULSE2 two-way, and PULSE2 directly inputs pulse inspection It surveys module to detect pulse and record at the time of be detected, PULSE1 inputs another pulse again after time delay module Detection module is detected, and is recorded at the time of be detected；

Step 3, to calculate pulse delay poor: it is defeated that counter be calculated delay to the time pulse signal difference detected twice Enter comparison module, it is that comparison module measures the delay with measuring instrument, do the delay obtained after correcting process and be compared, according to Comparison result generates corresponding id signal；

Step 4, encryption target program: whether the encrypted target program of id signal input effectively determines according to id signal Whether program runs, and achievees the purpose that encryption.

2. the method as described in claim 1, which is characterized in that in step 1, after system electrification, also generated by external crystal-controlled oscillation Clock signal clk 0, CLK0 generate sampling clock CLK after the PLL frequency multiplication inside FPGA, if its period is T_CLK；At the same time FPGA generates the single pulse signal that a pulsewidth is 100ns.

3. method according to claim 2, which is characterized in that in step 2, time delay module is made of several cascade NOT gates, right PULSE1 is delayed；The pulse detection module of detection PULSE2 constantly detects the rising edge of PULSE2 using sampling clock CLK, Rising edge starts counter immediately and starts counting once arriving；And the pulse detection module for detecting PULSE1 utilizes sampling clock CLK constantly detects the rising edge of PULSE1, and rising edge stops counter once arriving immediately, it is assumed that the count value of counter is N, then delay T of the time delay module to pulse signal_DIt indicates are as follows:

T_D=N × T_CLK (1)。

4. method as claimed in claim 3, which is characterized in that in step 3, delay value T that counter obtains_DIt is input to and compares It is measured in module with measuring instrument, is the value T obtained after correcting process_D’It is compared, judges whether two values are equal, if T_D= T_D’, then id signal Flag is effective, on the contrary then invalid.

5. method as claimed in claim 4, which is characterized in that in step 4, marking signal Flag is as encrypted target journey The control variable of sequence, when it is effective, otherwise encrypted target program operation does not run, realizes the encryption to program.

6. the method as described in any one of claims 1 to 5, which is characterized in that the measuring instrument is MTIM712.

7. the method as described in any one of claims 1 to 5, which is characterized in that the time delay module is by 100 cascade NOT gates Composition.

8. the method as described in any one of claims 1 to 5, the time delay module is made of 1000 cascade NOT gates.

9. method as claimed in claim 4, which is characterized in that the correcting process is to round up.