CN107577965A

CN107577965A - A kind of FPGA encryption methods of gate delay difference

Info

Publication number: CN107577965A
Application number: CN201710887955.7A
Authority: CN
Inventors: 张华波
Original assignee: Tianjin Jinhang Computing Technology Research Institute
Current assignee: Tianjin Jinhang Computing Technology Research Institute
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2018-01-12
Anticipated expiration: 2037-09-27
Also published as: CN107577965B

Abstract

The present invention relates to a kind of FPGA encryption methods of gate delay difference, it is related to time and frequency measurement technical field.The present invention proposes a kind of FPGA encryption methods, and this method using FPGA itself gate delay difference is theoretical foundation, realized to FPGA program encryptions, can not only save development cost, while improve circuit integration degree, reduce circuit power consumption.

Description

A kind of FPGA encryption methods of gate delay difference

Technical field

The present invention relates to time and frequency measurement technical field, and in particular to a kind of FPGA encryption methods of gate delay difference.

Background technology

The continuous progress of semiconductor technology, the fast development of chip technology, field programmable gate array (Field are driven Programmable Gate Array, FPGA) as the outstanding person in this field, FPGA is as a kind of programmable logic device Part, it is the product further to grow up on the basis of the Programmables such as PAL, GAL, CPLD, is led as application specific integrated circuit A kind of semi-custom circuit in domain and occur.FPGA birth, had both solved the deficiency of custom circuit, overcome again it is original can The shortcomings that programming device gate circuit limited amount, have in fields such as computer hardware, communication, Aero-Space and automotive electronics It is widely applied.

Currently, occur many encryption methods for being directed to FPGA in industry, such as the encryption based on SRAM, based on CPLD Encrypt [application number：201410603250.4] [application number：201420643533.7] etc., these encryption methods be all by by means of Third party's Encryption Tool is helped to reach the purpose of encryption.The introducing of third party's Encryption Tool, development cost is not only added, and And circuit volume and power consumption are increased, in electronic circuit integrated higher and higher today, reduce circuit volume, reduce power consumption It has been trend of the times.

The content of the invention

(1) technical problems to be solved

The technical problem to be solved in the present invention is：How encryption to FPGA program is realized.

(2) technical scheme

In order to solve the above-mentioned technical problem, the invention provides a kind of FPGA encryption methods of gate delay difference, including with Lower step：

Step 1, produce single pulse signal：After system electrification, FPGA produces a single pulse signal；

Step 2, pulse detection：The single pulse signal is divided into PULSE1 and PULSE2 two-way, and PULSE2 directly inputs arteries and veins Rush detection module to detect pulse and record at the time of be detected, PULSE1 inputs another again after time delay module Individual pulse detection module is detected, and is recorded at the time of be detected；

Step 3, calculating pulse delay are poor：Counter is calculated and made to the time pulse signal difference detected twice Delay input comparison module is obtained after respective handling, the delay is compared comparison module with the delay that measuring instrument measures, root Corresponding id signal is produced according to comparative result；

Step 4, encryption target program：The encrypted target program of id signal input, it is whether effective according to id signal Whether determination procedure runs, and reaches the purpose of encryption.

Preferably, in step 1, after system electrification, clock signal clk 0 is also produced by external crystal-controlled oscillation, CLK0 is through FPGA Sampling clock CLK is produced after internal PLL frequencys multiplication, if its cycle is T_CLK；At the same time it is 100ns that FPGA, which produces a pulsewidth, The single pulse signal.

Preferably, in step 2, time delay module is made up of some cascade NOT gates, enters line delay to PULSE1；Detection PULSE2 pulse detection module constantly detects PULSE2 rising edge using sampling clock CLK, and rising edge is stood once arriving Start counter to start counting up；And the pulse detection module for detecting PULSE1 is constantly detected using sampling clock CLK PULSE1 rising edge, rising edge stop counter, it is assumed that the count value of counter is N, then be delayed mould immediately once arriving The delay T of block pulse signals_DIt is expressed as：

T_D=N × T_CLK (1)。

Preferably, in step 3, delay value T that counter obtains_DIt is input to what is measured in comparison module with measuring instrument, does Value T after correcting process_D’It is compared, judges whether two values are equal, if T_D=T_D’, then id signal Flag is effective, it is on the contrary then It is invalid.

Preferably, in step 4, control variables of the marking signal Flag as encrypted target program, when it is effective When, the operation of encrypted target program, otherwise do not run, realize the encryption to program.

(3) beneficial effect

The present invention proposes a kind of FPGA encryption methods, and this method is using FPGA itself gate delay difference as theoretical foundation, reality Now to FPGA program encryptions, development cost can be not only saved, while improves circuit integration degree, reduce circuit power consumption.

Brief description of the drawings

Fig. 1 is the method broad flow diagram of the present invention；

Fig. 2 is the Method And Principle block diagram of the present invention；

Fig. 3 is the logical flow chart of the embodiment of the present invention；

Fig. 4 is delay figure of mono- NOT gate of FPGA1 to signal；

Fig. 5 is delay figure of the 100 cascade NOT gates of FPGA1 to signal；

Fig. 6 is delay figure of the 1000 cascade NOT gates of FPGA1 to signal；

Fig. 7 is delay figure of the 1000 cascade NOT gates of FPGA2 to signal；

Fig. 8 is delay figure of the 1000 cascade NOT gates of FPGA3 to signal.

Embodiment

To make the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the present invention's Embodiment is described in further detail.

Find that delay of the NOT gate to signal is about 0.3ns-0.4ns in FPGA, when in FPGA through a large amount of tests During the cascade of portion several NOT gates, its delay to signal is not each non-simple linear superposition of gate delay, different FPGA Delay of the cascade NOT gate of internal identical quantity to signal has differences, and the size of difference depends on the quantity of cascade NOT gate. Fig. 4-Fig. 8 is delay feelings of the different FPGA cascade NOT gates measured using precise time-time-interval measuring instrument MTIM712 to signal Condition.Three FPGA devices FPGA1, FPGA2 and FPGA3 used in experiment, it is all that altera corp CycloneII series is same Batch chip one by one, measuring instrument MTIM712 measurement accuracy are 100ps.

From Fig. 6-Fig. 8, if being delayed using the average value of delay as standard, FPGA1, FPGA2, FPGA3 are at 1000 The delay measured under cascade NOT gate is respectively 371.3ns, 357.8ns, 365.6ns.As can be seen here, identical series and batch, no Even if with FPGA inside possess the cascade NOT gate of identical quantity, its delay to signal is also different.

Based on above-mentioned discovery, the present invention proposes a kind of using FPGA itself gate delay difference as theoretical foundation, realization pair The method of FPGA program encryptions, its encryption method implementation process is as shown in Fig. 1 to Fig. 3.

Step 1：System electrification, clock signal clk 0 caused by external crystal-controlled oscillation produce height after the PLL frequencys multiplication inside FPGA Frequency sampling clock CLK, if its cycle is T_CLK；At the same time FPGA produces the pulse signal that a pulsewidth is 100ns；

Step 2：Pulse signal is divided into PULSE1 and PULSE2 two-way：PULSE1 input time delay modules, if time delay module by Dry cascade NOT gate composition, enters line delay to PULSE1；PULSE2 is then directly inputted to pulse detection module 1, pulse detection module 1 constantly detects PULSE2 rising edge using high frequency sampling clock CLK, and rising edge starts counter and started immediately once arriving Count；

Step 3：PULSE1 is input to pulse detection module 2 and detected after time delay module；The profit of pulse detection module 2 PULSE1 rising edge is constantly detected with high frequency sampling clock CLK, rising edge stops counter immediately once arriving.Assuming that meter The count value of number device is N.The then delay T of time delay module pulse signals_DIt can be expressed as：

T_D=N × T_CLK (1)

Step 4：The delay value T that counter obtains_DBe input to it is being measured in judge module with measuring instrument, do correcting process The value T obtained after (rounding up)_D’It is compared, judges whether two values are equal.If T_D=T_D’, then id signal Flag is effective, It is on the contrary then invalid.

Step 5：Control variables of the marking signal Flag as encrypted target program, it is encrypted when it is effective Target program is run, and is not otherwise run, is realized the encryption to program.

Because delay of the same order connection NOT gate to signal is different inside any FPGA, and each FPGA corresponds to certain One unique delay value, therefore when different FPGA are encrypted, encipheror can be variant.NOT gate is such as cascaded as 1000 When, FPGA1, FPGA2, FPAGA3 delay are respectively 371.3ns, 357.8ns, 365.6ns, therefore when being encrypted, are sentenced It is used in disconnected module and T_DThe value T compared_D’Should be 371.3ns, 357.8ns, 365.6ns respectively.

The main reason for amendment delay is limitation that any FPGA device has maximum operation frequency, sample clock frequency Can not possibly be infinitely great, the amendment of delay will directly affect the success or failure of encryption.

It is above-mentioned to measure in the case where 1000 cascade NOT gate, FPGA1, FPGA2, FPAGA3 delay be respectively 371.3ns, 357.8ns、365.6ns.If sampling clock is 500MHz, then its resolution ratio is 2ns, therefore the delay measured using the clock Can not possibly be equal with delay 371.3ns, 357.8ns, 365.6ns that measuring instrument MTIM712 is measured.Therefore the amendment to delay is The essential link of this encryption method.By above-mentioned delay 371.3ns, 357.8ns, 365.6ns be modified to respectively 372ns, After 358ns, 366ns, the delay value counted to get using 500MHz sampling clocks can be equal therewith.

The encryption method of the present invention can not only save development cost, while improve circuit integration degree, reduce electricity Road power consumption, encryption method of the invention are verified on more money FPGA products, have important reality in field of engineering technology With value.

The success or failure of encryption will be influenceed by some objective factors, mainly there is at following 2 points：

1) sample clock frequency.Sample clock frequency is an important factor for influenceing this encryption method.Work as sample clock frequency For 100MHz when, its resolution ratio is only 10ns, can only distinguish between more than 10ns delay；When sample clock frequency is 1GHz, differentiate Rate is 1ns, then can distinguish more than 1ns delay.Therefore, sample clock frequency is higher, and resolution ratio is higher, then can more distinguish Small delay.

2) FPGA agings.FPGA agings are also to influence another latency of encryption success or failure, with the FPGA lengths of service Increase, its internal circuit structure will appear from aging phenomenon, and a certain degree of skew also occurs in its delay to signal.Currently Successful program is encrypted, after a certain time of operation, program cisco unity malfunction may be caused due to the aging of device, Need re-encrypted.

Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and become Shape also should be regarded as protection scope of the present invention.

Claims

1. a kind of FPGA encryption methods of gate delay difference, it is characterised in that comprise the following steps：

Step 2, pulse detection：The single pulse signal is divided into PULSE1 and PULSE2 two-way, and PULSE2 directly inputs pulse inspection Survey module to detect pulse and record at the time of be detected, PULSE1 inputs another pulse again after time delay module Detection module is detected, and is recorded at the time of be detected；

Step 3, calculating pulse delay are poor：Counter is calculated the time pulse signal difference detected twice and makees corresponding position Delay input comparison module is obtained after reason, the delay is compared comparison module with the delay that measuring instrument measures, according to comparing As a result corresponding id signal is produced；

Step 4, encryption target program：Whether the encrypted target program of id signal input, effectively determine according to id signal Whether program is run, and reaches the purpose of encryption.

2. the method as described in claim 1, it is characterised in that in step 1, after system electrification, also produced by external crystal-controlled oscillation Clock signal clk 0, CLK0 produce sampling clock CLK after the PLL frequencys multiplication inside FPGA, if its cycle is T_CLK；At the same time FPGA produces the single pulse signal that a pulsewidth is 100ns.

3. method as claimed in claim 2, it is characterised in that in step 2, time delay module is made up of some cascade NOT gates, right PULSE1 enters line delay；Detection PULSE2 pulse detection module constantly detects PULSE2 rising edge using sampling clock CLK, Rising edge starts counter and started counting up immediately once arriving；And the pulse detection module for detecting PULSE1 utilizes sampling clock CLK constantly detects PULSE1 rising edge, and rising edge stops counter immediately once arriving, it is assumed that the count value of counter is N, then time delay module pulse signals delay T_DIt is expressed as：

T_D=N × T_CLK (1)。

4. method as claimed in claim 3, it is characterised in that in step 3, delay value T that counter obtains_DIt is input to and compares Measured in module with measuring instrument, be the value T obtained after correcting process_D’It is compared, judges whether two values are equal, if T_D= T_D’, then id signal Flag is effective, on the contrary then invalid.

5. method as claimed in claim 4, it is characterised in that in step 4, marking signal Flag is as encrypted target journey The control variable of sequence, when it is effective, the operation of encrypted target program, does not otherwise run, realize the encryption to program.

6. the method as any one of claim 1 to 5, it is characterised in that the measuring instrument is MTIM712.

7. the method as any one of claim 1 to 5, it is characterised in that the time delay module is by 100 cascade NOT gates Composition.

8. the method as any one of claim 1 to 5, the time delay module is made up of 1000 cascade NOT gates.

9. method as claimed in claim 4, it is characterised in that the correcting process is to round up.