CN203069747U - Phase-locked loop on-chip jitter measuring circuit - Google Patents
Phase-locked loop on-chip jitter measuring circuit Download PDFInfo
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- CN203069747U CN203069747U CN 201220746557 CN201220746557U CN203069747U CN 203069747 U CN203069747 U CN 203069747U CN 201220746557 CN201220746557 CN 201220746557 CN 201220746557 U CN201220746557 U CN 201220746557U CN 203069747 U CN203069747 U CN 203069747U
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Abstract
The utility model discloses a phase-locked loop on-chip jitter measuring circuit. The phase-locked loop on-chip jitter measuring circuit is realized by a digital circuit, comprising a calibration module (1), a pre-judging module (2), a delay chain module (3) and a storage module (4). The circuit can be used for calibration, and has the features of high measuring speed, high and adjustable measuring precision, and large measuring range. According to the utility model, four measuring resolutions are provided, and different measuring resolutions can be selected based on the size of the jitter of the phase-locked loop; the calibration module (1) is used for reducing the circuit output deviation for zero-jitter input, improving the reliability of the jitter measuring circuit; and the measuring range of the delay chain module (3) is reduced by half by the pre-judging module (2), and the calibration module (1) is combined with the pre-judging module (2) (excluding a first buffer group and a second buffer group), so that the area and power consumption of the phase-locked loop on-chip jitter measuring circuit are effectively reduced.
Description
Technical field
The utility model relates to dithering measuring circuit on a kind of phase-locked ring plate, belongs to the electronic circuit technology field.
Background technology
Along with the continuous development of semiconductor technology, the performance of integrated circuit improves constantly, and System on Chip/SoC is more and more higher to the requirement of clock frequency.Phaselocked loop is as an important module of System on Chip/SoC, for entire chip provides high-frequency clock.Clock jitter is an important parameter of phaselocked loop, and the size of high-speed communication system clock jitter must be within the scope of design specifications regulation, otherwise can cause a series of problems such as system performance reduction, so the measurement of phaselocked loop shake is extremely important.
Traditional phaselocked loop jitter measurement method mainly is the sheet external pelivimetry---the use test instrument is analyzed pll output signal outside chip.But along with the development of technology, working frequency of chip improves constantly, and common testing tool can not meet the demands, and more accurate testing tool can increase considerably testing cost; Because (Input/Output, restriction I/O) use the external testing instrument can only measure low frequency signal to chip input and output pin performance, therefore can cause Measuring Time to increase; The output probe of testing tool can bring extra load to circuit under test, distorts measured signal, thereby influences the accuracy of jitter measurements; In addition, need increase extra dedicated pin when chip design to use to testing tool.Therefore, traditional jitter measurement method has many restrictions and shortcoming.
When using the shake of built-in self-test circuit measuring phaselocked loop, it is integrated in chip internal with phaselocked loop to be measured, in chip, finish the measurement of shake, I/O pin by chip outputs to the external testing instrument with measurement result then, so only need some cheaply testing apparatus just can analyze measured result easily, greatly reduce test duration and testing cost.On the at present comparatively common phase-locked ring plate there be dithering measuring circuit: time delay chain circuit, time voltage conversion circuit, time interval amplifying circuit, pulse reduction circuit, counter circuit, vernier time delay chain circuit and vernier pierce circuit etc.Wherein time voltage conversion circuit, time interval amplifying circuit measuring accuracy are higher, but use analog element, and it is difficult to realize, are subjected in the chip digital signal simultaneously easily and disturb; Time delay chain circuit, counter process circuit utilize digital circuit to realize easily, but measuring accuracy is not high; The pulse reduction circuit does not need reference clock, but is subjected to process deviation, power supply noise influence easily; Vernier time delay chain circuit measuring precision height can be realized continuous coverage, can utilize digital circuit to realize, but influenced by process deviation, and circuit area is bigger; Vernier pierce circuit measuring accuracy is higher, and area is little, but ring oscillator is introduced time dependent noise easily, and Measuring Time is long.
The utility model content
At the deficiency that prior art exists, the utility model purpose provides dithering measuring circuit on a kind of phase-locked ring plate with advantages such as high reliability, measuring speed are fast, measuring accuracy is high, measuring accuracy is adjustable, measurement range is big.
To achieve these goals, the utility model is to realize by the following technical solutions:
The utility model comprises calibration module and the anticipation module, time delay chain module and the memory module that are connected successively with the calibration module output terminal;
Calibration module has reference clock signal and phaselocked loop sub-frequency clock signal to be measured input, and is subjected to the control of mode of operation signal;
The time delay chain module is subjected to the control of precision control signal;
The time delay chain module comprises second control circuit, first time delay chain, second time delay chain and phase detector array;
First time delay chain and second time delay chain include a plurality of second adjustable time delay units of series connection successively; The phase detector array comprises a plurality of second phase detectors, in first time delay chain in the number of second adjustable time delay unit and second time delay chain in the number of second adjustable time delay unit, the phase detector array number of second phase detector all identical;
Each second phase detector first input end and second phase detector, second input end are connected the correspondence second adjustable time delay unit output terminal in first time delay chain and second time delay chain respectively;
The precision control signal applies first control signal and second control signal, first control signal by second control circuit to first time delay chain and second time delay chain] with second control signal] be connected first control end, second control end, the 3rd control end and the 4th control end of second adjustable time delay unit in first time delay chain and second time delay chain respectively;
Second adjustable delay unit comprises the 3rd impact damper and four Sheffer stroke gates;
The 3rd impact damper input termination the 3rd data selector or the 4th data selector output terminal, the 3rd buffer output end is connected to an input end of four Sheffer stroke gates, another input end of four Sheffer stroke gates connects first control end, second control end, the 3rd control end and the 4th control end respectively, and the output terminal of the 3rd impact damper also connects the second phase detector first input end or second phase detector, second input end.
Above-mentioned calibration module comprises first data selector, second data selector, the first adjustable delay circuit that is connected with the first data selector output terminal, second adjustable delay circuit and the first control circuit that is connected with the second data selector output terminal;
The first adjustable delay circuit comprises first impact damper and first adjustable time delay unit that is connected with first buffer output end, and the second adjustable delay circuit comprises second impact damper and first adjustable time delay unit that is connected with second buffer output end; First adjustable time delay unit is controlled by first control circuit;
Phaselocked loop sub-frequency clock signal to be measured connects second data selector and imports 0 end, and reference clock signal connects that first data selector is imported 0 end, first data selector imports 1 end and second data selector is imported 1 end;
The mode of operation signal connects the first data selector data selecting side and the second data selector data selecting side.
Above-mentioned anticipation module comprises first phase detector, the 3rd data selector and the 4th data selector;
Calibration module first output terminal is connected to that the 3rd data selector is imported 1 end and the 4th data selector is imported 0 end;
Calibration module second output terminal is connected to that the 3rd data selector is imported 0 end and the 4th data selector is imported 1 end;
Reference clock signal and phaselocked loop sub-frequency clock signal to be measured are connected respectively to the first phase detector first input end and first phase detector, second input end, and the output terminal of first phase detector connects the 3rd data selector data selecting side and the 4th data selector data selecting side.
The beneficial effects of the utility model are as follows:
(1) controls the time delay of second adjustable time delay unit in first time delay chain and second time delay chain by the precision control signal of time delay chain module, thereby can select four kinds of Measurement Resolution and its corresponding measurement range;
(2) utilize calibration module to reduce zero and shake the deviation that circuit is exported when importing, improved the reliability of dithering measuring circuit on the phase-locked ring plate;
(3) when the independent anticipation module of design, comprise first buffer pool and second buffer pool, but in the side circuit, increased driving force by the adjustable time delay unit of calibration module, so do not need to add again first buffer pool and second buffer pool.In addition owing to adopted the anticipation module, can make the time delay chain module scale down half.They have reduced area and the power consumption of dithering measuring circuit on the phase-locked ring plate effectively.
Description of drawings
Fig. 1 is dithering measuring circuit entire block diagram on the phase-locked ring plate of the present utility model;
Fig. 2 is the calibration module circuit diagram of dithering measuring circuit on the phase-locked ring plate of the present utility model;
Fig. 3 is the anticipation module circuit diagram of dithering measuring circuit on the phase-locked ring plate of the present utility model;
Fig. 4 is the calibration module of dithering measuring circuit on the phase-locked ring plate of the present utility model and the combinational circuit diagram of anticipation module;
Fig. 5 is the time delay chain module circuit diagram of dithering measuring circuit on the phase-locked ring plate of the present utility model;
Fig. 6 is the second adjustable time delay unit circuit diagram of dithering measuring circuit on the phase-locked ring plate of the present utility model;
Fig. 7 is first phase detector and the second phase detector circuit figure;
Fig. 8 is storage unit circuit figure.
Embodiment
For technological means, creation characteristic that the utility model is realized, reach purpose and effect is easy to understand, below in conjunction with embodiment, further set forth the utility model.
As shown in Figure 1, the general frame for dithering measuring circuit on the phase-locked ring plate of the present utility model comprises calibration module 1, anticipation module 2, time delay chain module 3 and memory module 4.
The design of first adjustable time delay unit, second adjustable time delay unit is the basis of entire circuit, first time delay chain 71, second time delay chain 72 are linked to each other step by step by N second adjustable time delay unit and form, and the first adjustable delay circuit 16 and the second adjustable delay circuit 17 in the calibration module 1 have comprised first adjustable time delay unit.
As shown in Figure 6, second adjustable time delay unit comprises that the 3rd impact damper 51 and four Sheffer stroke gates 52,53,54,55 form.The output terminal of the 3rd impact damper 51 i.e. the second adjustable time delay unit output signal O, be connected to four Sheffer stroke gates 52, an input pin of 53,54,55 simultaneously, another input pin connects the first control end C51, the second control end C52, the 3rd control end C53 and the 4th control end C54, by changing the level of the first control end C51, the second control end C52, the 3rd control end C53 and the 4th control end C54, change the electric capacity of output terminal O, thereby change the output load size of the 3rd impact damper 51, and then changed the time-delay of the 3rd impact damper 51.When the first control end C51, the second control end C52, the 3rd control end C53 and the 4th control end C54 are high level entirely, the load capacitance maximum of the 3rd impact damper 51, the time-delay maximum of second adjustable time delay unit; Input control signal C51, when C52, C53, C54 are low level entirely, the load capacitance minimum of the 3rd impact damper 51, the time-delay minimum of second adjustable time delay unit.Therefore can pass through input control signal C51, C52, C53, C54 adjusts the time-delay of second adjustable time delay unit.Because the pin electric capacity change of Sheffer stroke gate value is less, therefore the time-delay of the 3rd impact damper 51 change is very little, thereby for realizing higher measuring accuracy.
First adjustable time delay unit has only lacked an output terminal Z who draws than second adjustable time delay unit, and other places are all identical.
As shown in Figure 7, first phase detector and second phase detector are realized the discriminating of phase place precedence to measured signal in the dithering measuring circuit on phase-locked ring plate, and it has determined the full accuracy that circuit can be measured.The realization of first phase detector and second phase detector is a kind of common practice, academic dissertation: research and the design of quick lock in numerical control phaselocked loop, in carried out concrete elaboration, repeat no more herein.
As shown in Figure 2, calibration module 1 comprises first data selector 11, second data selector 12, the first adjustable delay circuit 16, the second adjustable delay circuit 17 and first control circuit 18.Phaselocked loop sub-frequency clock signal C2 to be measured need connect the single input pin of two Sheffer stroke gates 13, thereby the electric capacity of realizing two input ports that C1 and C2 signal connect is consistent.When mode of operation signal S1 is high level, dithering measuring circuit is in calibration mode, 1 of calibration module is passed to the first adjustable delay circuit 16 and the second adjustable delay circuit 17 with reference clock signal C1, by observing the output result of dithering measuring circuit, the deviation of circuit output in the time of just can obtaining zero input jiffer, and then utilize the first adjustable delay circuit 16 and the second adjustable delay circuit 17 to reduce this deviation.
As shown in Figure 3, anticipation module 2 comprises first phase detector 29, the 3rd data selector 21, the 4th data selector 22, first buffer pool (comprising impact damper 23, impact damper 25 and impact damper 27) and second buffer pool (comprising impact damper 24, impact damper 26 and impact damper 28).Reference clock signal C1 is connected first phase detector, 29 first input end A1 and the second input end B1 with phaselocked loop sub-frequency clock signal C2 to be measured, and the output terminal S2 of first phase detector 29 is its inner Q signal.Calibration module 1 first output terminal O1 is connected on the impact damper 23, by being connected to the 3rd data selector 21 input 1 ends and the 4th data selector 22 inputs 0 end after impact damper 23,25, the 27 increase drivings, calibration module 1 second output terminal O2 is connected on the impact damper 24, increases to drive by impact damper 24,26,28 to be connected to the 3rd data selector 21 input 0 ends and the 4th data selector 22 inputs 1 end.If reference clock signal C1 is leading phaselocked loop sub-frequency clock signal C2 to be measured, then the output terminal S2 of first phase detector 29 is high level, and then output O3, the O4 of the 3rd data selector 21, the 4th data selector 22 are respectively calibration module 1 first output terminal O1, the second output terminal O2; If phaselocked loop sub-frequency clock signal C2 to be measured is leading, then the output terminal S2 of first phase detector 29 is low level, the output O3 of the 3rd data selector 21, the 4th data selector 22 then, and O4 is respectively calibration module 1 second output terminal O2, the first output terminal O1.The output O3 of such the 3rd data selector 21 is leading signal always, and the output O4 of the 4th data selector 22 is the signal for lagging behind always.
As shown in Figure 4, in order further to save area, calibration module 1 and anticipation module 2 are combined, utilize the first adjustable delay circuit 16 and the second adjustable delay circuit 17 in the calibration module 1, save the impact damper 23 ~ 28 of anticipation module 2.
As shown in Figure 5, time delay chain module 3 by second control circuit 30,2N second adjustable time delay unit (31,32 ..., 3(2N)) and N phase detector (61,62 ... 6N) form.The measuring accuracy of dithering measuring circuit is by precision control signal S6[2:0] control.Second control circuit 30 has been realized the time-delay adjustment to second adjustable time delay unit in two one time delay chains.To the control signal difference that two one time delay chains 71,72 second adjustable time delay unit apply, making the delay unit of two one time delay chains produce delay difference is △ t.This delay difference is the measuring accuracy of time delay chain module.By adjusting the delay difference of first time delay chain 71, second time delay chain 72, can select different measuring accuracy and measurement range.The time-delay of second adjustable time delay unit of first time delay chain 71 is t+ Δ t, and the time-delay of second adjustable time delay unit of second time delay chain 72 is t, and △ t is far smaller than t.Therefore allow leading signal O3 be transferred to first time delay chain 71, the signal O4 that falls behind removes to catch up with the O3 signal by second time delay chain 72, second adjustable time delay unit step by step.The output O of each grade second adjustable time delay unit gives second phase detector and detects, before O4 catches up with O3, and second phase detector output Q[1], Q[2] ... Q[i-1] be high; After the leading O3 of O4, second phase detector output Q[i], Q[i+1] ..., Q[N] and be low.The second adjustable time delay unit number that experiences by the record process of catching up with is weighed the mistiming of two input signals.Suppose i phase detector 6(i) be output as low level, (i-1) individual phase detector 6 (i-1) is output as high level, and then the mistiming of two input signals is i* Δ t.Second adjustable time delay unit on first time delay chain 71 is subjected to the first control signal S61[4:1] control, second adjustable time delay unit on second time delay chain 72 be subjected to the second control signal S62[4:1] control, S61[4:1] and the second control signal S62[4:1] by precision control signal S60[2:0] control is as following table 1:
Table 1
| S6[2:0] | The first control signal S61[4:1] | The second control signal S62[4:1] |
| 001 | 0001 | 0000 |
| 010 | 0011 | 0000 |
| 011 | 0111 | 0000 |
| 100 | 1111 | 0000 |
Precision control signal S6[2:0] can be made as 001,010,011,100.The second control signal S62[4:1 of second time delay chain 72] be low level, its time-delay is minimum like this, is t, and the time-delay size of second adjustable time delay unit by adjusting first time delay chain 71 changes measuring accuracy.As S6[2:0] when being made as 001, the delay unit of first time delay chain 71 (31,33,35 ..., 3(2N-1) the control end C51 of) Sheffer stroke gate 53 connects high level, the change value △ t minimum of therefore delaying time, and measuring accuracy is the highest, the measurement range minimum; S6[2:0] be 100 o'clock, second adjustable time delay unit (31 of first time delay chain 71,33,35,, 3(2N-1)) four Sheffer stroke gates 52,53,54,55 control end C51, C52, C53, C54 connect high level, the change value △ t maximum of therefore delaying time, measuring accuracy is minimum, the measurement range maximum.
Output Q[1 because of phase detector array 73], Q[2], Q[3] ..., Q[N] and contain shake, in order to eliminate shake, realize numeral output, need be with the output Q[1 of second phase detector], Q[2], Q[3] ... Q[N] store register 81,82 into ..., 8(N) in, call in order to subsequent conditioning circuit.Find that by the post-simulation waveform of observing time delay chain module 3 when next rising edge arrived, there was the not shake of output Q of second phase detector in the big time front and back.Be implemented as follows: time delay chain module 3, when circuit is in mode of operation, the time-delay of second adjustable time delay unit of the first time delay chain 71 all time-delay than second time delay chain 72 is big, the C51 control end of each second adjustable time delay unit on first time delay chain 71 is high level always, a so input pin one direct high level of the Sheffer stroke gate 53 of these second adjustable time delay units, so when second adjustable time delay unit output O was rising edge, the output Z of this Sheffer stroke gate 53 was negative edge.Therefore as shown in Figure 8, adopt the output Z of Sheffer stroke gate 53 as clock signal, remove to drive the register 81,82 that negative edge triggers,, 8N, the output Q[1 of second phase detector simultaneously], Q[2], Q[3] ... Q[N] connection register 81,82 ... the data input D end of 8N finally is kept at output Q4[1 to the result], Q4[2], Q4[3] ..., Q4[N].
The post-simulation experimental result confirms that the resolution of dithering measuring circuit is 1.36ps, and measuring error is less than 3.03ps, but the frequency of measuring-signal is greater than 200MHz.See the following form 2 in detail.
Table 2
| S6[2:0] | Measurement Resolution/ps | Measuring error/ps | The linearity | N | Measurement range/ps |
| 001 | 1.36 | 3.03 | 0.9962 | 44 | -60~60 |
| 010 | 2.87 | 4.54 | 0.9979 | 43 | -120~120 |
| 011 | 4.44 | 8.28 | 0.9983 | 45 | -200~200 |
| 100 | 5.92 | 8.35 | 0.9989 | 52 | -300~300 |
Principle of work of the present utility model is: input signal is clock reference signal C1 and phaselocked loop sub-frequency clock signal C2 to be measured, and dithering measuring circuit is weighed the jitter value of C2 by the time difference between measurement C1 and the C2.When mode of operation signal S1 is high level, circuit is in calibration mode, reference clock signal C1 is input to the first adjustable delay circuit 16, the second adjustable delay circuit 17, by observing the output result of dithering measuring circuit, the deviation of circuit output in the time of just can obtaining zero input jiffer, and then the time-delay of adjusting the first adjustable delay circuit 16, the second adjustable delay circuit 17 circuit output bias when reducing zero shake input; When mode of operation signal S1 is low level, circuit is in mode of operation, clock reference signal C1 and phaselocked loop sub-frequency clock signal C2 to be measured are by the calibration of calibration module 1, through anticipation module 2, determine leading and delay signal, select the first suitable time delay chain 71, second time delay chain 72, leading signal is selected the first big time delay chain 71 of time-delay, the signal that lags behind is selected the second little time delay chain 72 of time-delay, the signal that lags behind constantly removes to catch up with leading signal by the difference of two one time delay chains, and the process of catching up with can embody by the output of phase detector array 73.The output Q[1 of phase detector array 73], Q[2], Q[3] ..., Q[N], by register 81,82,83 ..., 8N storage treats that subsequent conditioning circuit handles.
More than show and described ultimate principle of the present utility model and principal character and advantage of the present utility model.The technician of the industry should understand; the utility model is not restricted to the described embodiments; that describes in above-described embodiment and the instructions just illustrates principle of the present utility model; under the prerequisite that does not break away from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall in claimed the utility model scope.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (3)
1. dithering measuring circuit on the phase-locked ring plate is characterized in that, comprises calibration module (1) and the anticipation module (2), time delay chain module (3) and the memory module (4) that are connected successively with calibration module (1) output terminal;
Described calibration module (1) has reference clock signal and phaselocked loop sub-frequency clock signal to be measured input, and is subjected to the control of mode of operation signal;
Described time delay chain module (3) is subjected to the control of precision control signal;
Described time delay chain module (3) comprises second control circuit (30), first time delay chain (71), second time delay chain (72) and phase detector array (73);
Described first time delay chain (71) and second time delay chain (72) include a plurality of second adjustable time delay units of series connection successively; Described phase detector array (73) comprises a plurality of second phase detectors, in described first time delay chain (71) in the number of second adjustable time delay unit and second time delay chain (72) in the number of second adjustable time delay unit, the phase detector array (73) number of second phase detector all identical;
Each described second phase detector first input end and second phase detector, second input end are connected the correspondence second adjustable time delay unit output terminal in first time delay chain (71) and second time delay chain (72) respectively;
Described precision control signal applies first control signal and second control signal by second control circuit (30) to first time delay chain (71) and second time delay chain (72), and described first control signal and second control signal are connected first control end, second control end, the 3rd control end and the 4th control end of second adjustable time delay unit in first time delay chain (71) and second time delay chain (72) respectively;
Described second adjustable delay unit comprises the 3rd impact damper (51) and four Sheffer stroke gates (52,53,54,55);
Described the 3rd impact damper (51) input termination the 3rd data selector (21) or the 4th data selector (22) output terminal, the 3rd impact damper (51) output terminal is connected to an input end of four Sheffer stroke gates (52,53,54,55), another input end of four described Sheffer stroke gates connects first control end, second control end, the 3rd control end and the 4th control end respectively, and the output terminal of described the 3rd impact damper (51) also connects the second phase detector first input end or second phase detector, second input end.
2. dithering measuring circuit on the phase-locked ring plate according to claim 1 is characterized in that,
Described calibration module (1) comprises first data selector (11), second data selector (12), the first adjustable delay circuit (16) that is connected with first data selector (11) output terminal, the second adjustable delay circuit (17) and the first control circuit (18) that are connected with second data selector (12) output terminal;
The described first adjustable delay circuit (16) comprises first impact damper (14) and first adjustable time delay unit that is connected with first impact damper (14) output terminal, and the described second adjustable delay circuit (17) comprises second impact damper (15) and first adjustable time delay unit that is connected with second impact damper (15) output terminal; Described first adjustable time delay unit is controlled by first control circuit (18);
Described phaselocked loop sub-frequency clock signal to be measured connects second data selector (12) input, 0 end, and described reference clock signal connects first data selector (11) input, 0 end, first data selector (11) input 1 end and second data selector (12) input, 1 end;
Described mode of operation signal connects first data selector (11) data selecting side and second data selector (12) data selecting side.
3. dithering measuring circuit on the phase-locked ring plate according to claim 2 is characterized in that,
Described anticipation module (2) comprises first phase detector (29), the 3rd data selector (21) and the 4th data selector (22);
Described calibration module (1) first output terminal is connected to the 3rd data selector (21) input 1 end and the 4th data selector (22) input 0 end;
Described calibration module (1) second output terminal is connected to the 3rd data selector (21) input 0 end and the 4th data selector (22) input 1 end;
Described reference clock signal and phaselocked loop sub-frequency clock signal to be measured are connected respectively to first phase detector (29) first input end and first phase detector (29) second input ends, and the output terminal of described first phase detector (29) connects the 3rd data selector (21) data selecting side and the 4th data selector (22) data selecting side.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220746557 CN203069747U (en) | 2012-12-29 | 2012-12-29 | Phase-locked loop on-chip jitter measuring circuit |
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|---|---|---|---|
| CN 201220746557 CN203069747U (en) | 2012-12-29 | 2012-12-29 | Phase-locked loop on-chip jitter measuring circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076554A (en) * | 2012-12-29 | 2013-05-01 | 江苏东大集成电路系统工程技术有限公司 | Phase-locked loop on-chip jitter measurement circuit |
| CN115268247A (en) * | 2022-08-11 | 2022-11-01 | 上海华力微电子有限公司 | Digital-analog mixed high-precision establishment holding time measuring circuit and implementation method thereof |
-
2012
- 2012-12-29 CN CN 201220746557 patent/CN203069747U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076554A (en) * | 2012-12-29 | 2013-05-01 | 江苏东大集成电路系统工程技术有限公司 | Phase-locked loop on-chip jitter measurement circuit |
| CN115268247A (en) * | 2022-08-11 | 2022-11-01 | 上海华力微电子有限公司 | Digital-analog mixed high-precision establishment holding time measuring circuit and implementation method thereof |
| CN115268247B (en) * | 2022-08-11 | 2023-11-24 | 上海华力微电子有限公司 | High-precision establishment holding time measuring circuit for digital-analog mixing and implementation method thereof |
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