CN105067896A - Pilot frequency phase coincidence fuzzy region characteristic pulse detection system and detection method - Google Patents
Pilot frequency phase coincidence fuzzy region characteristic pulse detection system and detection method Download PDFInfo
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Abstract
The invention discloses a pilot frequency phase coincidence fuzzy region characteristic pulse detection system which comprises an FPGA module, a fuzzy region pulse generation circuit, a first difference vernier delayer, an XOR gate circuit module, a second difference vernier delayer, a third difference vernier delayer, a NOT gate circuit module and an AND gate circuit module, which are connected in sequence. The fuzzy region pulse generation circuit is directly connected with the XOR gate circuit module; and the second difference vernier delayer is directly connected with the AND gate circuit module. The detection system and detection method can realize pilot frequency phase coincidence fuzzy region characteristic pulse detection effectively, and has the advantages of high precision and high reliability.
Description
Technical field
The present invention relates to a kind of pulse detection system and detection method, particularly relate to a kind of alien frequencies phase coincidence confusion region characteristic pulse detection system and detection method.
Background technology
At present, under complex frequency relation or large frequency difference frequency relation, the formation of confusion region is random, and the width of confusion region is change, and measure gate if set up based on this confusion region in theory, its measuring accuracy not easily ensures.In the alien frequencies phase coincidence pulse detection of reality, the measurement of accurate time-frequency multiparameter depends on the constancy of confusion region and confusion region with group's cycle be interval repeatability or stringent synchronization, and the principal element affecting measuring accuracy is the randomness of the trigger pulse impelling knife switch in confusion region.And existing alien frequencies phase coincidence confusion region characteristic pulse detection system, there is the shortcoming of accuracy of detection difference, poor reliability.Traditional phase coincidence confusion region detection technique, on the one hand due to the uncertainty of reference signal and measured signal frequency relation, usually cause the uncertainty of its confusion region width, this uncertain major effect is counted as the measuring accuracy of the time-frequency multiparameter on basis with gate; On the other hand due to reference signal and the complicacy of the frequency relation of measured signal, phase coincidence confusion region usually can be caused to be difficult to formation, to cause measuring speed to slow down, even measure difficulty.
Summary of the invention
The object of this invention is to provide a kind of alien frequencies phase coincidence confusion region characteristic pulse detection system and detection method, effectively can realize the detection of alien frequencies phase coincidence confusion region characteristic pulse, there is the advantage of high precision, high reliability.
The present invention adopts following technical proposals:
A kind of alien frequencies phase coincidence confusion region characteristic pulse detection system, comprises FPGA module, confusion region pulse-generating circuit, the first difference vernier delayer, NOR gate circuit module, the second difference vernier delayer, the 3rd difference vernier delayer, not circuit module and AND circuit module;
Described FPGA module, for utilizing the phaselocked loop of FPGA module inside as frequency source and frequency division produces 10MHz frequency signal and 10.23MHz frequency signal is delivered to confusion region pulse-generating circuit respectively;
Described confusion region pulse-generating circuit, carry out filtering, analog signal processing and signal level standard handovers respectively for the 10MHz frequency signal carried FPGA module and 10.23MHz frequency signal, the two-way frequency signal of input is converted to two ways of digital signals after filtering; Then signal level standard handovers is realized to two ways of digital signals, to produce enough voltage to drive late-class circuit; Again the two ways of digital signals changed through level standard is carried out meticulous time delay, and phase-locking detection is carried out to the two ways of digital signals after meticulous time delay, the confusion region pulse of final output two ways of digital signals, and the confusion region pulse of two ways of digital signals is delivered to the first difference vernier delayer and NOR gate circuit module respectively;
The first described difference vernier delayer, confusion region pulse for exporting confusion region pulse-generating circuit is carried out delay and is realized phase place adjustment, make the confusion region pulse after delay and the pulse of former confusion region phase place or on the time after move some delay resolutions, then will postpone the confusion region pulse signal transmission after adjustment to NOR gate circuit module;
Described NOR gate circuit module, XOR process is carried out for the confusion region pulse after the delay adjustment of the confusion region pulse transmitted by confusion region pulse-generating circuit and the transmission of the first difference vernier delayer, phase delay width position produces the bilateral characteristic pulse in confusion region, then bilateral for the confusion region of generation characteristic pulse is transferred to the second difference vernier delayer;
The second described difference vernier delayer, carries out pulse width adjustment for the bilateral characteristic pulse in confusion region carried NOR gate circuit module, makes the bilateral characteristic pulse in confusion region become confusion region unilateral characteristic pulse; Then the confusion region unilateral characteristic pulse of generation is delivered to the 3rd difference vernier delayer and AND circuit module respectively;
The 3rd described difference vernier delayer, postpone for carrying out high-resolution difference vernier to the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying, the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying is become can flip-flop number gate and the confusion region unilateral characteristic pulse narrower than confusion region unilateral characteristic pulse, is called confusion region unilateral characteristic burst pulse; Then the confusion region unilateral characteristic ultra-narrow pulse of generation is delivered to not circuit module;
Described not circuit module, for carrying out phase place negate to the confusion region unilateral characteristic ultra-narrow pulse of the 3rd difference vernier delayer conveying, and is delivered to AND circuit module by the confusion region unilateral characteristic ultra-narrow pulse after the phase place negate of generation;
Described AND circuit module, for the confusion region unilateral characteristic ultra-narrow pulse after the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying and the phase place negate of not circuit module conveying is carried out and logical process, and using the part of confusion region unilateral characteristic pulse and confusion region unilateral characteristic ultra-narrow pulse phase coincidence as the final best confusion region characteristic pulse exported.
Described 10MHz frequency signal is that the frequency signal of standard is produced by atomic frequency standard.
Described confusion region pulse-generating circuit is made up of filtering circuit, analog signal processing circuit, signal level standard handovers circuit, signal delay circuit and gate circuit successively;
Filtering circuit, carries out filtering process for the 10MHz frequency signal that produces FPGA module and 10.23MHz frequency signal, and by the 10MHz frequency signal after process and 10.23MHz frequency signal transmission to analog signal processing circuit;
Analog signal processing circuit, for being converted to two ways of digital signals by through the 10MHz frequency signal of voltage transformation and 10.23MHz frequency signal; And the two ways of digital signals after conversion is transferred to signal level standard handovers circuit;
Signal level standard handovers circuit, for realizing signal level standard handovers, voltage transformation process is carried out to the 10MHz frequency signal after filtering process and 10.23MHz frequency signal, the ECL level translation of 1.1V is become the Transistor-Transistor Logic level of 4.5V, to produce enough voltage driven late-class circuits; And the two ways of digital signals after signal level standard handovers is transferred to signal delay circuit;
Signal delay circuit, for carrying out signal delay to two ways of digital signals; And the two ways of digital signals through signal delay is sent to gate circuit;
Gate circuit, for carrying out phase-locking detection to two ways of digital signals, the final confusion region pulse exporting two ways of digital signals, and the first difference vernier delayer and NOR gate circuit module are sent in the phase coincidence confusion region pulse of generation.
Described gate circuit adopts AND circuit.
The detection method utilizing the alien frequencies phase coincidence confusion region characteristic pulse detection system described in claim 1 to 4 any one to carry out, comprises the following steps successively:
A: utilize the phaselocked loop of FPGA module inside as frequency source and frequency division produces 10MHz frequency signal and 10.23MHz frequency signal is delivered to confusion region pulse-generating circuit respectively;
B: utilize confusion region pulse-generating circuit, the 10MHz frequency signal carry FPGA module and 10.23MHz frequency signal carry out filtering, analog signal processing and signal level standard handovers respectively, and the two-way frequency signal of input is converted to two ways of digital signals after filtering; Then signal level standard handovers is realized to two ways of digital signals, to produce enough voltage to drive late-class circuit; Again the two ways of digital signals changed through level standard is carried out meticulous time delay, and phase-locking detection is carried out to the two ways of digital signals after meticulous time delay, the confusion region pulse of final output two ways of digital signals, and the confusion region pulse of two ways of digital signals is delivered to the first difference vernier delayer and NOR gate circuit module respectively;
C: utilize the first difference vernier delayer, confusion region pulse for exporting confusion region pulse-generating circuit is carried out delay and is realized phase place adjustment, make the confusion region pulse after delay and the pulse of former confusion region phase place or on the time after move some delay resolutions, then will postpone the confusion region pulse signal transmission after adjustment to NOR gate circuit module;
D: utilize NOR gate circuit module, XOR process is carried out in confusion region pulse after the delay adjustment of the confusion region pulse transmit confusion region pulse-generating circuit and the transmission of the first difference vernier delayer, phase delay width position produces the bilateral characteristic pulse in confusion region, then bilateral for the confusion region of generation characteristic pulse is transferred to the second difference vernier delayer;
E: utilize the second difference vernier delayer, carries out pulse width adjustment to the bilateral characteristic pulse in confusion region of NOR gate circuit module conveying, makes the bilateral characteristic pulse in confusion region become confusion region unilateral characteristic pulse; Then the confusion region unilateral characteristic pulse of generation is delivered to the 3rd difference vernier delayer and AND circuit module respectively;
F: utilize the 3rd difference vernier delayer, carry out high-resolution difference vernier to the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying to postpone, the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying is become can flip-flop number gate and the confusion region unilateral characteristic pulse narrower than confusion region unilateral characteristic pulse, is called confusion region unilateral characteristic burst pulse; Then the confusion region unilateral characteristic ultra-narrow pulse of generation is delivered to not circuit module;
G: utilize not circuit module, carries out phase place negate to the confusion region unilateral characteristic ultra-narrow pulse of the 3rd difference vernier delayer conveying, and the confusion region unilateral characteristic ultra-narrow pulse after the phase place negate of generation is delivered to AND circuit module;
H: utilize AND circuit module, confusion region unilateral characteristic ultra-narrow pulse after the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying and the phase place negate of not circuit module conveying is carried out and logical process, and using the part of confusion region unilateral characteristic pulse and confusion region unilateral characteristic ultra-narrow pulse phase coincidence as the final best confusion region characteristic pulse exported.
In described step B, the procurement process of phase coincidence confusion region pulse is as follows:
The first step: before generation coincidence confusion region pulse, the 10MHz frequency signal carry FPGA module and 10.23MHz frequency signal carry out filtering process, with garbage signals such as filtering noises, retain its useful signal; Then to after filtering process FPGA module conveying 10MHz frequency signal and 10.23MHz frequency signal carry out digitized processing obtain digital signal; The 10MHz frequency signal carried due to FPGA module and 10.23MHz frequency signal are level is 1.1V, late-class circuit cannot be driven, therefore need to carry out signal level standard handovers circuit, make the output level of two paths of signals after voltage transformation be 4.5V, and power amplification is carried out to this two ways of digital signals;
Second step, utilizes signal delay circuit to carry out signal delay respectively to two ways of digital signals; And each railway digital signal all carries out and logic analysis with this railway digital signal after carrying out fine delay, produces the phase-locking pulse signal of this road synchronous digital signal; Again the phase-locking pulse signal that the two-way of production is parallel is sent to gate circuit;
3rd step, the phase-locking pulse signal that two-way is parallel utilizes gate circuit to carry out and logic analysis, carries out, with logic analysis process, can obtaining the pulse of phase coincidence confusion region at the phase-locking pulse signal parallel to two-way.
In described step e, the implementation method that the bilateral characteristic pulse in confusion region becomes confusion region unilateral characteristic pulse is as follows:
The bilateral characteristic pulse in confusion region carries out the delay of difference vernier through the second difference vernier delayer, its phase place is by delay delay resolution size, impulse cluster wherein on the right side of edge, confusion region is overflowed confusion region because of delay, and then the bilateral characteristic pulse in confusion region becomes confusion region unilateral characteristic pulse, confusion region width reduces half, becomes confusion region unilateral characteristic pulse.
In described step F, the implementation method that confusion region unilateral characteristic pulse becomes confusion region unilateral characteristic ultra-narrow pulse is as follows:
Confusion region unilateral characteristic pulse carries out the delay of difference vernier through the 3rd difference vernier delayer, its phase place is by delay delay resolution size, confusion region pulse entirety moves to the right, confusion region porch pulse is overflowed confusion region because of delay, and then confusion region unilateral characteristic pulse width diminishes, become confusion region unilateral characteristic ultra-narrow pulse.
The present invention utilizes the delay resolution of ultrastability effectively to form stable, rule and the extremely narrow phase coincidence confusion region of width, avoid the randomness of confusion region and knife switch trigger pulse, ensure that the consistance of knife switch signal in do not caused in the same time measuring error.
The present invention can eliminate the error that inconsistency and mismatch due to system hardware are brought, increasing substantially of time-frequency measuring multiple parameters precision is made to become possibility on physical realizability, thus make the precision that present invention greatly enhances time-frequency measuring multiple parameters, effectively realize the detection of alien frequencies phase coincidence confusion region characteristic pulse.
Accompanying drawing explanation
Fig. 1 is the theory diagram of alien frequencies phase coincidence confusion region of the present invention characteristic pulse detection system.
Embodiment
Below in conjunction with drawings and Examples, the present invention is done with detailed description:
As shown in Figure 1, alien frequencies phase coincidence confusion region of the present invention characteristic pulse detection system, comprises FPGA module, confusion region pulse-generating circuit, the first difference vernier delayer, NOR gate circuit module, the second difference vernier delayer, the 3rd difference vernier delayer, not circuit module and AND circuit module;
Described FPGA module, for utilizing the phaselocked loop of FPGA module inside as frequency source and frequency division produces 10MHz frequency signal and 10.23MHz frequency signal is delivered to confusion region pulse-generating circuit respectively;
10MHz frequency signal is the frequency signal of standard, can be produced by atomic frequency standard, and 10.23MHz frequency signal is the standard signal of spaceborne atomic frequency standard, L1 and the L2 wave band on Navsat is all integral multiples of standard signal 10.23MHz, has and represents meaning.In addition, 10MHz frequency signal and 10.23MHz frequency signal have certain frequency departure and frequency relation relative complex, have the phase place comparison meaning of general frequency relation.Meanwhile, 10MHz frequency signal and 10.23MHz frequency signal are homologous signal, can effective stress release treatment, improve the stability of phase place comparison.
Described confusion region pulse-generating circuit, carry out filtering, analog signal processing and signal level standard handovers respectively for the 10MHz frequency signal carried FPGA module and 10.23MHz frequency signal, the two-way frequency signal of input is converted to two ways of digital signals after filtering; Then signal level standard handovers is realized to two ways of digital signals, to produce enough voltage to drive late-class circuit; Again the two ways of digital signals changed through level standard is carried out meticulous time delay, and phase-locking detection is carried out to the two ways of digital signals after meticulous time delay, the confusion region pulse of final output two ways of digital signals, and the confusion region pulse of two ways of digital signals is delivered to the first difference vernier delayer and NOR gate circuit module respectively;
Confusion region pulse-generating circuit is made up of filtering circuit, analog signal processing circuit, signal level standard handovers circuit, signal delay circuit and gate circuit successively.
Filtering circuit, carries out filtering process for the 10MHz frequency signal that produces FPGA module and 10.23MHz frequency signal, and by the 10MHz frequency signal after process and 10.23MHz frequency signal transmission to analog signal processing circuit;
Analog signal processing circuit, for being converted to two ways of digital signals by through the 10MHz frequency signal of voltage transformation and 10.23MHz frequency signal; And the two ways of digital signals after conversion is transferred to signal level standard handovers circuit;
Signal level standard handovers circuit, for realizing signal level standard handovers, voltage transformation process is carried out to the 10MHz frequency signal after filtering process and 10.23MHz frequency signal, the ECL level translation of 1.1V is become the Transistor-Transistor Logic level of 4.5V, to produce enough voltage driven late-class circuits; And the two ways of digital signals after signal level standard handovers is transferred to signal delay circuit;
Signal delay circuit, for carrying out signal delay to two ways of digital signals; And the two ways of digital signals through signal delay is sent to gate circuit;
Gate circuit, for carrying out phase-locking detection to two ways of digital signals, the final confusion region pulse exporting two ways of digital signals, and the first difference vernier delayer and NOR gate circuit module are sent in the phase coincidence confusion region pulse of generation;
After above-mentioned module processes successively, confusion region pulse-generating circuit can obtain the phase coincidence confusion region pulse corresponding with frequency relation between 10MHz and 10.23MHz according to the 10MHz frequency signal of FPGA module conveying and 10.23MHz frequency signal.
The procurement process of phase coincidence confusion region pulse is as follows:
The first step: before generation coincidence confusion region pulse, the 10MHz frequency signal carry FPGA module and 10.23MHz frequency signal carry out filtering process, with garbage signals such as filtering noises, retain its useful signal; Then to after filtering process FPGA module conveying 10MHz frequency signal and 10.23MHz frequency signal carry out digitized processing obtain digital signal; The 10MHz frequency signal carried due to FPGA module and 10.23MHz frequency signal are level is 1.1V, late-class circuit cannot be driven, therefore need to carry out signal level standard handovers circuit, make the output level of two paths of signals after voltage transformation be 4.5V, and power amplification is carried out to this two ways of digital signals;
Second step, utilizes signal delay circuit to carry out signal delay respectively to two ways of digital signals; And each railway digital signal all carries out and logic analysis with this railway digital signal after carrying out fine delay, produces the phase-locking pulse signal of this road synchronous digital signal; Again the phase-locking pulse signal that the two-way of production is parallel is sent to gate circuit;
3rd step, the phase-locking pulse signal that two-way is parallel utilizes gate circuit to carry out and logic analysis, carries out, with logic analysis process, can obtaining the pulse of phase coincidence confusion region at the phase-locking pulse signal parallel to two-way.
The first described difference vernier delayer, confusion region pulse for exporting confusion region pulse-generating circuit is carried out delay and is realized phase place adjustment, make the confusion region pulse after delay and the pulse of former confusion region phase place or on the time after move some delay resolutions, its size is about several ps, then will postpone the confusion region pulse signal transmission after adjusting to NOR gate circuit module;
Described NOR gate circuit module, XOR process is carried out for the confusion region pulse after the delay adjustment of the confusion region pulse transmitted by confusion region pulse-generating circuit and the transmission of the first difference vernier delayer, phase delay width position produces the bilateral characteristic pulse in confusion region, then bilateral for the confusion region of generation characteristic pulse is transferred to the second difference vernier delayer;
The second described difference vernier delayer, carries out pulse width adjustment for the bilateral characteristic pulse in confusion region carried NOR gate circuit module, makes the bilateral characteristic pulse in confusion region become confusion region unilateral characteristic pulse; Then the confusion region unilateral characteristic pulse of generation is delivered to the 3rd difference vernier delayer and AND circuit module respectively;
The implementation method that the bilateral characteristic pulse in confusion region becomes confusion region unilateral characteristic pulse is as follows:
The bilateral characteristic pulse in confusion region carries out the delay of difference vernier through the second difference vernier delayer, its phase place is by delay delay resolution size, impulse cluster wherein on the right side of edge, confusion region is overflowed confusion region because of delay, and then the bilateral characteristic pulse in confusion region becomes confusion region unilateral characteristic pulse, confusion region width reduces half.Using confusion region unilateral characteristic pulse signal as signal strobe during time-frequency measuring multiple parameters, the precision of its time-frequency measuring multiple parameters will improve 2-3 magnitude.
The 3rd described difference vernier delayer, postpone for carrying out high-resolution difference vernier to the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying, the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying is become can flip-flop number gate and the confusion region unilateral characteristic pulse narrower than confusion region unilateral characteristic pulse, is called confusion region unilateral characteristic burst pulse; Then the confusion region unilateral characteristic ultra-narrow pulse of generation is delivered to not circuit module; Wherein, high-resolution difference vernier postpones to refer to that two ways of digital signals enters the different delay chain of two-way length simultaneously, the length difference of two-way delay chain represents delay resolution, the length difference of two-way delay chain is less, delay resolution is higher, by the adjustment of the similar length cursor type to two-way delay chain length difference, the high measurement resolution of system can be obtained.
The implementation method of confusion region unilateral characteristic ultra-narrow pulse is as follows:
Confusion region unilateral characteristic pulse carries out the delay of difference vernier through the 3rd difference vernier delayer, its phase place is by delay delay resolution size, confusion region pulse entirety moves to the right, confusion region porch pulse is overflowed confusion region because of delay, and then confusion region unilateral characteristic pulse width diminishes, become confusion region unilateral characteristic ultra-narrow pulse.
Described not circuit module, for carrying out phase place negate to the confusion region unilateral characteristic ultra-narrow pulse of the 3rd difference vernier delayer conveying, and is delivered to AND circuit module by the confusion region unilateral characteristic ultra-narrow pulse after the phase place negate of generation;
Described AND circuit module, for the confusion region unilateral characteristic ultra-narrow pulse after the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying and the phase place negate of not circuit module conveying is carried out and logical process, and using the part of confusion region unilateral characteristic pulse and confusion region unilateral characteristic ultra-narrow pulse phase coincidence as the final best confusion region characteristic pulse exported.
Alien frequencies phase coincidence confusion region of the present invention characteristic pulse detection method, comprises the following steps:
A: utilize the phaselocked loop of FPGA module inside as frequency source and frequency division produces 10MHz frequency signal and 10.23MHz frequency signal is delivered to confusion region pulse-generating circuit respectively;
B: utilize confusion region pulse-generating circuit, the 10MHz frequency signal carry FPGA module and 10.23MHz frequency signal carry out filtering, analog signal processing and signal level standard handovers respectively, and the two-way frequency signal of input is converted to two ways of digital signals after filtering; Then signal level standard handovers is realized to two ways of digital signals, to produce enough voltage to drive late-class circuit; Again the two ways of digital signals changed through level standard is carried out meticulous time delay, and phase-locking detection is carried out to the two ways of digital signals after meticulous time delay, the confusion region pulse of final output two ways of digital signals, and the confusion region pulse of two ways of digital signals is delivered to the first difference vernier delayer and NOR gate circuit module respectively;
C: utilize the first difference vernier delayer, confusion region pulse for exporting confusion region pulse-generating circuit is carried out delay and is realized phase place adjustment, make the confusion region pulse after delay and the pulse of former confusion region phase place or on the time after move some delay resolutions, then will postpone the confusion region pulse signal transmission after adjustment to NOR gate circuit module;
D: utilize NOR gate circuit module, XOR process is carried out in confusion region pulse after the delay adjustment of the confusion region pulse transmit confusion region pulse-generating circuit and the transmission of the first difference vernier delayer, phase delay width position produces the bilateral characteristic pulse in confusion region, then bilateral for the confusion region of generation characteristic pulse is transferred to the second difference vernier delayer;
E: utilize the second difference vernier delayer, carries out pulse width adjustment to the bilateral characteristic pulse in confusion region of NOR gate circuit module conveying, makes the bilateral characteristic pulse in confusion region become confusion region unilateral characteristic pulse; Then the confusion region unilateral characteristic pulse of generation is delivered to the 3rd difference vernier delayer and AND circuit module respectively;
F: utilize the 3rd difference vernier delayer, carry out high-resolution difference vernier to the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying to postpone, the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying is become can flip-flop number gate and the confusion region unilateral characteristic pulse narrower than confusion region unilateral characteristic pulse, is called confusion region unilateral characteristic burst pulse; Then the confusion region unilateral characteristic ultra-narrow pulse of generation is delivered to not circuit module;
G: utilize not circuit module, carries out phase place negate to the confusion region unilateral characteristic ultra-narrow pulse of the 3rd difference vernier delayer conveying, and the confusion region unilateral characteristic ultra-narrow pulse after the phase place negate of generation is delivered to AND circuit module;
H: utilize AND circuit module, confusion region unilateral characteristic ultra-narrow pulse after the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying and the phase place negate of not circuit module conveying is carried out and logical process, and using the part of confusion region unilateral characteristic pulse and confusion region unilateral characteristic ultra-narrow pulse phase coincidence as the final best confusion region characteristic pulse exported.
In the present invention, the first difference vernier delayer, the second difference vernier delayer and the 3rd difference vernier delayer form by the fixed delay unit of FPGA inside, are made up of two-way differential delay chain.Because the retardation of fixed delay unit is stablized, the first difference vernier delayer be made up of it, the second difference vernier delayer and the 3rd difference vernier delayer also have very high degree of stability.For the confusion region that alien frequencies phase coincidence produces, utilize the difference vernier delayer be made up of fixed delay unit to postpone, greatly ensure that edge, confusion region is delayed by the stability of position.The pulse that this stable delay position produces, in the open and close trigger pip as counting gate, can increase substantially the reliability of time-frequency measuring multiple parameters.
Under complex frequency relation or large frequency difference frequency relation, the formation of confusion region is random, and the width of confusion region is change, and measure gate if set up based on this confusion region in theory, its measuring accuracy not easily ensures.In the alien frequencies phase coincidence pulse detection of reality, the measurement of accurate time-frequency multiparameter depends on the constancy of confusion region and confusion region with group's cycle be interval repeatability or stringent synchronization, and the principal element affecting measuring accuracy is the randomness of the trigger pulse impelling knife switch in confusion region.Retardation due to fixed delay unit represents the minimum value of delay, is called as delay resolution.The delay resolution of ultrastability can effectively be formed stable, rule and the extremely narrow phase coincidence confusion region of width, avoid the randomness of confusion region and knife switch trigger pulse, that is, the stability of delay resolution ensure that the consistance of knife switch signal in do not caused in the same time measuring error, the i.e. stringent synchronization of knife switch signal, this stringent synchronization eliminates the error that inconsistency and mismatch due to system hardware are brought just, increasing substantially of time-frequency measuring multiple parameters precision is made to become possibility on physical realizability, thus make the precision that present invention greatly enhances time-frequency measuring multiple parameters.
Claims (8)
1. an alien frequencies phase coincidence confusion region characteristic pulse detection system, is characterized in that: comprise FPGA module, confusion region pulse-generating circuit, the first difference vernier delayer, NOR gate circuit module, the second difference vernier delayer, the 3rd difference vernier delayer, not circuit module and AND circuit module;
Described FPGA module, for utilizing the phaselocked loop of FPGA module inside as frequency source and frequency division produces 10MHz frequency signal and 10.23MHz frequency signal is delivered to confusion region pulse-generating circuit respectively;
Described confusion region pulse-generating circuit, carry out filtering, analog signal processing and signal level standard handovers respectively for the 10MHz frequency signal carried FPGA module and 10.23MHz frequency signal, the two-way frequency signal of input is converted to two ways of digital signals after filtering; Then signal level standard handovers is realized to two ways of digital signals, to produce enough voltage to drive late-class circuit; Again the two ways of digital signals changed through level standard is carried out meticulous time delay, and phase-locking detection is carried out to the two ways of digital signals after meticulous time delay, the confusion region pulse of final output two ways of digital signals, and the confusion region pulse of two ways of digital signals is delivered to the first difference vernier delayer and NOR gate circuit module respectively;
The first described difference vernier delayer, confusion region pulse for exporting confusion region pulse-generating circuit is carried out delay and is realized phase place adjustment, make the confusion region pulse after delay and the pulse of former confusion region phase place or on the time after move some delay resolutions, then will postpone the confusion region pulse signal transmission after adjustment to NOR gate circuit module;
Described NOR gate circuit module, XOR process is carried out for the confusion region pulse after the delay adjustment of the confusion region pulse transmitted by confusion region pulse-generating circuit and the transmission of the first difference vernier delayer, phase delay width position produces the bilateral characteristic pulse in confusion region, then bilateral for the confusion region of generation characteristic pulse is transferred to the second difference vernier delayer;
The second described difference vernier delayer, carries out pulse width adjustment for the bilateral characteristic pulse in confusion region carried NOR gate circuit module, makes the bilateral characteristic pulse in confusion region become confusion region unilateral characteristic pulse; Then the confusion region unilateral characteristic pulse of generation is delivered to the 3rd difference vernier delayer and AND circuit module respectively;
The 3rd described difference vernier delayer, postpone for carrying out high-resolution difference vernier to the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying, the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying is become can flip-flop number gate and the confusion region unilateral characteristic pulse narrower than confusion region unilateral characteristic pulse, is called confusion region unilateral characteristic burst pulse; Then the confusion region unilateral characteristic ultra-narrow pulse of generation is delivered to not circuit module;
Described not circuit module, for carrying out phase place negate to the confusion region unilateral characteristic ultra-narrow pulse of the 3rd difference vernier delayer conveying, and is delivered to AND circuit module by the confusion region unilateral characteristic ultra-narrow pulse after the phase place negate of generation;
Described AND circuit module, for the confusion region unilateral characteristic ultra-narrow pulse after the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying and the phase place negate of not circuit module conveying is carried out and logical process, and using the part of confusion region unilateral characteristic pulse and confusion region unilateral characteristic ultra-narrow pulse phase coincidence as the final best confusion region characteristic pulse exported.
2. alien frequencies phase coincidence confusion region according to claim 1 characteristic pulse detection system, is characterized in that: described 10MHz frequency signal is that the frequency signal of standard is produced by atomic frequency standard.
3. alien frequencies phase coincidence confusion region according to claim 1 characteristic pulse detection system, is characterized in that: described confusion region pulse-generating circuit is made up of filtering circuit, analog signal processing circuit, signal level standard handovers circuit, signal delay circuit and gate circuit successively;
Filtering circuit, carries out filtering process for the 10MHz frequency signal that produces FPGA module and 10.23MHz frequency signal, and by the 10MHz frequency signal after process and 10.23MHz frequency signal transmission to analog signal processing circuit;
Analog signal processing circuit, for being converted to two ways of digital signals by through the 10MHz frequency signal of voltage transformation and 10.23MHz frequency signal; And the two ways of digital signals after conversion is transferred to signal level standard handovers circuit;
Signal level standard handovers circuit, for realizing signal level standard handovers, voltage transformation process is carried out to the 10MHz frequency signal after filtering process and 10.23MHz frequency signal, the ECL level translation of 1.1V is become the Transistor-Transistor Logic level of 4.5V, to produce enough voltage driven late-class circuits; And the two ways of digital signals after signal level standard handovers is transferred to signal delay circuit;
Signal delay circuit, for carrying out signal delay to two ways of digital signals; And the two ways of digital signals through signal delay is sent to gate circuit;
Gate circuit, for carrying out phase-locking detection to two ways of digital signals, the final confusion region pulse exporting two ways of digital signals, and the first difference vernier delayer and NOR gate circuit module are sent in the phase coincidence confusion region pulse of generation.
4. alien frequencies phase coincidence confusion region according to claim 3 characteristic pulse detection system, is characterized in that: described gate circuit adopts AND circuit.
5. the detection method utilizing the alien frequencies phase coincidence confusion region characteristic pulse detection system described in claim 1 to 4 any one to carry out, is characterized in that, comprise the following steps successively:
A: utilize the phaselocked loop of FPGA module inside as frequency source and frequency division produces 10MHz frequency signal and 10.23MHz frequency signal is delivered to confusion region pulse-generating circuit respectively;
B: utilize confusion region pulse-generating circuit, the 10MHz frequency signal carry FPGA module and 10.23MHz frequency signal carry out filtering, analog signal processing and signal level standard handovers respectively, and the two-way frequency signal of input is converted to two ways of digital signals after filtering; Then signal level standard handovers is realized to two ways of digital signals, to produce enough voltage to drive late-class circuit; Again the two ways of digital signals changed through level standard is carried out meticulous time delay, and phase-locking detection is carried out to the two ways of digital signals after meticulous time delay, the confusion region pulse of final output two ways of digital signals, and the confusion region pulse of two ways of digital signals is delivered to the first difference vernier delayer and NOR gate circuit module respectively;
C: utilize the first difference vernier delayer, confusion region pulse for exporting confusion region pulse-generating circuit is carried out delay and is realized phase place adjustment, make the confusion region pulse after delay and the pulse of former confusion region phase place or on the time after move some delay resolutions, then will postpone the confusion region pulse signal transmission after adjustment to NOR gate circuit module;
D: utilize NOR gate circuit module, XOR process is carried out in confusion region pulse after the delay adjustment of the confusion region pulse transmit confusion region pulse-generating circuit and the transmission of the first difference vernier delayer, phase delay width position produces the bilateral characteristic pulse in confusion region, then bilateral for the confusion region of generation characteristic pulse is transferred to the second difference vernier delayer;
E: utilize the second difference vernier delayer, carries out pulse width adjustment to the bilateral characteristic pulse in confusion region of NOR gate circuit module conveying, makes the bilateral characteristic pulse in confusion region become confusion region unilateral characteristic pulse; Then the confusion region unilateral characteristic pulse of generation is delivered to the 3rd difference vernier delayer and AND circuit module respectively;
F: utilize the 3rd difference vernier delayer, carry out high-resolution difference vernier to the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying to postpone, the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying is become can flip-flop number gate and the confusion region unilateral characteristic pulse narrower than confusion region unilateral characteristic pulse, is called confusion region unilateral characteristic burst pulse; Then the confusion region unilateral characteristic ultra-narrow pulse of generation is delivered to not circuit module;
G: utilize not circuit module, carries out phase place negate to the confusion region unilateral characteristic ultra-narrow pulse of the 3rd difference vernier delayer conveying, and the confusion region unilateral characteristic ultra-narrow pulse after the phase place negate of generation is delivered to AND circuit module;
H: utilize AND circuit module, confusion region unilateral characteristic ultra-narrow pulse after the confusion region unilateral characteristic pulse of the second difference vernier delayer conveying and the phase place negate of not circuit module conveying is carried out and logical process, and using the part of confusion region unilateral characteristic pulse and confusion region unilateral characteristic ultra-narrow pulse phase coincidence as the final best confusion region characteristic pulse exported.
6. the alien frequencies phase coincidence confusion region according to claim 5 characteristic pulse detection system detection method of carrying out, it is characterized in that, in described step B, the procurement process of phase coincidence confusion region pulse is as follows:
The first step: before generation coincidence confusion region pulse, the 10MHz frequency signal carry FPGA module and 10.23MHz frequency signal carry out filtering process, with garbage signals such as filtering noises, retain its useful signal; Then to after filtering process FPGA module conveying 10MHz frequency signal and 10.23MHz frequency signal carry out digitized processing obtain digital signal; The 10MHz frequency signal carried due to FPGA module and 10.23MHz frequency signal are level is 1.1V, late-class circuit cannot be driven, therefore need to carry out signal level standard handovers circuit, make the output level of two paths of signals after voltage transformation be 4.5V, and power amplification is carried out to this two ways of digital signals;
Second step, utilizes signal delay circuit to carry out signal delay respectively to two ways of digital signals; And each railway digital signal all carries out and logic analysis with this railway digital signal after carrying out fine delay, produces the phase-locking pulse signal of this road synchronous digital signal; Again the phase-locking pulse signal that the two-way of production is parallel is sent to gate circuit;
3rd step, the phase-locking pulse signal that two-way is parallel utilizes gate circuit to carry out and logic analysis, carries out, with logic analysis process, can obtaining the pulse of phase coincidence confusion region at the phase-locking pulse signal parallel to two-way.
7. the alien frequencies phase coincidence confusion region according to claim 5 characteristic pulse detection system detection method of carrying out, it is characterized in that, in described step e, the implementation method that the bilateral characteristic pulse in confusion region becomes confusion region unilateral characteristic pulse is as follows:
The bilateral characteristic pulse in confusion region carries out the delay of difference vernier through the second difference vernier delayer, its phase place is by delay delay resolution size, impulse cluster wherein on the right side of edge, confusion region is overflowed confusion region because of delay, and then the bilateral characteristic pulse in confusion region becomes confusion region unilateral characteristic pulse, confusion region width reduces half, becomes confusion region unilateral characteristic pulse.
8. the alien frequencies phase coincidence confusion region according to claim 5 characteristic pulse detection system detection method of carrying out, it is characterized in that, in described step F, the implementation method that confusion region unilateral characteristic pulse becomes confusion region unilateral characteristic ultra-narrow pulse is as follows:
Confusion region unilateral characteristic pulse carries out the delay of difference vernier through the 3rd difference vernier delayer, its phase place is by delay delay resolution size, confusion region pulse entirety moves to the right, confusion region porch pulse is overflowed confusion region because of delay, and then confusion region unilateral characteristic pulse width diminishes, become confusion region unilateral characteristic ultra-narrow pulse.
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