CN113093517A - Precise short-time interval measurement system and measurement method based on Beidou clock - Google Patents
Precise short-time interval measurement system and measurement method based on Beidou clock Download PDFInfo
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- CN113093517A CN113093517A CN202110387568.3A CN202110387568A CN113093517A CN 113093517 A CN113093517 A CN 113093517A CN 202110387568 A CN202110387568 A CN 202110387568A CN 113093517 A CN113093517 A CN 113093517A
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
- G04R20/04—Tuning or receiving; Circuits therefor
Abstract
The invention discloses a precision short time interval measuring system and a measuring method based on a Beidou clock, and the system comprises a satellite receiver module, a first time delay module, a second time delay module, a first phase coincident point module, a second phase coincident point module, a third phase coincident point module, a logic door system module, a gate signal generating module, a time interval generating module, a display module and a power supply module; according to the method, the width of the phase coincident point pulse is reduced by a differential phase synchronous detection method to extract the phase coincident point edge pulse as a gate switch signal, so that the accuracy of gate time measurement is improved, the measurement resolution of a short time interval and the detection resolution and stability of a Beidou time-frequency system are greatly improved, high-precision time synchronization between satellite and ground is realized, and the centimeter-millimeter-level Beidou satellite positioning service capability is enhanced.
Description
Technical Field
The invention relates to a time interval measuring system and a measuring method, in particular to a precise short time interval measuring system and a measuring method based on a Beidou clock.
Background
In the Beidou time-frequency system, a short time interval between a satellite clock and a receiver clock is an important determining factor of Beidou high-precision positioning, Beidou precision time service and communication, the short time interval is a clock error generated by different time scales of a frequency standard signal and a measured signal, and is called time difference for short, and the short time interval represents the time synchronization precision between a space-based system and a foundation-based system.
Traditional short time interval measurement method based on big dipper clock establishes on the time processing basis more, in the time digital processing process, there is the count error of 1 word on the one hand, on the other hand because the change of receiver service environment and satellite signal receive the influence of complicated air ground background, the jitter nature at gate border is strengthened, simultaneously because the system error that inconsistency and the mismatching nature of big dipper time frequency system hardware caused, the stability of gate time has been reduced, can't guarantee the high accuracy time synchronization between satellite and the ground, hardly realize centimetre level to millimeter level's big dipper satellite positioning service ability.
Disclosure of Invention
The invention aims to provide a precision short-time interval measurement system and a measurement method based on a Beidou clock, which can effectively eliminate the influence of Beidou time-frequency hardware errors on measurement precision, greatly improve short-time interval measurement resolution, realize high-precision time synchronization between a satellite and the ground and strengthen centimeter-millimeter-level Beidou satellite positioning service capability.
In order to achieve the purpose, the invention adopts the following technical scheme:
a precise short time interval measuring system based on a Beidou clock comprises a satellite receiver module, a first time delay module, a second time delay module, a first phase coincidence point module, a second phase coincidence point module, a third phase coincidence point module, a logic door system module, a gate signal generating module, a time interval generating module, a display module and a power supply module; the signal output end of the satellite receiver module is respectively connected with the signal input end of a first phase coincidence point module, the signal input end of a first time delay module and the signal input end of a second time delay module, the signal output end of the first time delay module is connected with the signal input end of a second phase coincidence point module, the signal output end of the second time delay module is connected with the signal input end of a third phase coincidence point module, the signal output end of the first phase coincidence point module and the signal output end of the second phase coincidence point module are simultaneously connected with the signal input end of a gate signal generation module, the signal output end of the third phase coincidence point module is connected with the signal input end of a logic gate system module, the signal output end of the logic gate system module is connected with the signal input end of the gate signal generation module, and the signal output end of the gate signal generation module is connected with the signal input end, the signal output end of the time interval generating module is connected with the signal input end of the display module;
the satellite receiver module adopts a Beidou receiver and is used for providing satellite frequency signals and receiver oscillator signals, namely detected signals and beacon signals;
the first time delay module adopts a first edge type D trigger with a clock cycle being a first clock cycle and is used for time delay of the first clock cycle of a measured signal and a standard signal; the second time delay module adopts a second edge type D trigger with a clock period as a second clock period and is used for time delay of the second clock period of the measured signal and the standard signal, the first clock period and the second clock period have different sizes, and the absolute value of the difference value between the first clock period and the second clock period is defined as a time differential;
the first phase coincidence point module adopts a first pilot frequency phase detection circuit and is used for generating a first phase coincidence point pulse between a detected signal and a standard signal; the second phase coincidence point module adopts a second pilot frequency phase detection circuit and is used for generating a second phase coincidence point pulse between the detected signal and the beacon signal after the second phase coincidence point pulse is delayed by the first time delay module; the third phase coincidence point module adopts a third difference frequency phase detection circuit and is used for generating a third phase coincidence point pulse between the measured signal and the beacon signal after being delayed by the second time delay module;
the logic gate system module adopts an inverter and is used for inverting the phase of the third phase coincident point pulse;
the gate signal generation module adopts a three-input AND gate circuit and is used for generating gate switch pulse signals, namely switch signals of a counting gate;
the time interval generating module adopts a programmable counter and is used for measuring the clock difference between a measured signal and a beacon signal;
and the display module is used for receiving and displaying the measurement result of the time interval generation module.
The Beidou receiver adopts an XHTF7107-B type.
The first edge type D trigger and the second edge type D trigger both adopt 74LS175 chips.
The first pilot frequency phase detection circuit, the second pilot frequency phase detection circuit and the third pilot frequency phase detection circuit all adopt pilot frequency phase detection circuits, each pilot frequency phase detection circuit consists of a first D trigger, a second D trigger, a first logic AND gate, a second logic AND gate, a third logic AND gate, a first logic NOT gate and a second logic NOT gate, the D1 input end and the D2 input end of the first D trigger are respectively connected with the A1 input end of the first logic AND gate and the Q1 output end of the first D trigger, the Q2 output end of the first D trigger is connected with the input end of the first logic NOT gate, the output end of the first logic NOT gate is connected with the B1 input end of the first logic AND gate, the D3 input end and the D4 input end of the second D trigger are respectively connected with the A2 input end of the second logic AND gate and the Q3 output end of the second D trigger, the Q4 output end of the second D trigger is connected with the input end of the second logic NOT gate, the output end of the second logical not gate is connected with the B2 input end of the second logical AND gate, and the output end Y1 of the second logical AND gate and the output end Y2 of the second logical AND gate are respectively connected with the A3 input end and the B3 input end of the third logical AND gate; the output end Y3 of the third logic AND gate is the output end of the pilot frequency phase coincidence detection circuit; the D1 input end of the first D flip-flop of the first pilot frequency phase detection circuit and the D3 input end of the second D flip-flop are respectively used as the input ends of a frequency scale signal and a detected signal, the D1 input end of the first D flip-flop of the second pilot frequency phase detection circuit and the D3 input end of the second D flip-flop are respectively used as the input ends of the frequency scale signal delayed by the first delay module and the detected signal, and the D1 input end of the first D flip-flop of the third pilot frequency phase detection circuit and the D3 input end of the second D flip-flop are respectively used as the input ends of the frequency scale signal delayed by the second delay module and the detected signal.
The inverter adopts a 74LS04 chip.
The three-input AND circuit adopts a 74LS11 chip.
The programmable counter is realized by FPGA hardware description language through programming, and the FPGA adopts a Cyclone IV chip EP4CE 75.
A precise short-time interval measurement method based on a Beidou clock comprises the following steps:
step 1: the frequency scale signal and the detected signal provided by the satellite receiver module are sent to a first phase coincidence point module for performing different frequency phase discrimination to generate a first phase coincidence point pulse, wherein the first phase coincidence point pulse is composed of a series of phase difference pulses which cannot be identified by the system detection resolution, and the envelope of the first phase coincidence point pulse is in Gaussian random distribution;
step 2: the frequency standard signal and the measured signal provided by the satellite receiver module are sent to a first time delay module, the time delay amount of the time delay of the first clock cycle is determined by the first clock cycle of a first edge type D trigger, the frequency standard signal and the measured signal after the time delay of the first clock cycle are sent to a second phase coincidence point module for different frequency phase discrimination to generate a second phase coincidence point pulse, and compared with the first phase coincidence point pulse, the second phase coincidence point pulse has the same pulse width and is delayed by one first clock cycle in phase;
and step 3: the frequency scale signal and the measured signal provided by the satellite receiver module are sent to a second time delay module, the time delay amount of the time delay of the second clock cycle is determined by the second clock cycle of a second edge type D trigger, the frequency scale signal and the measured signal after the time delay of the second clock cycle are sent to a third phase coincidence point module for different frequency phase discrimination to generate a third phase coincidence point pulse, then the third phase coincidence point pulse is sent to a logic gate system module, namely a phase inverter for phase inversion to obtain an inverted third phase coincidence point pulse, and the inverted third phase coincidence point pulse has the same pulse width and is inverted in phase and delayed by a second clock cycle compared with the first phase coincidence point pulse;
and 4, step 4: simultaneously sending the first phase coincident point pulse, the second phase coincident point pulse and the inverted third phase coincident point pulse into a gate signal generation module, namely a three-input and logic gate circuit, and generating a gate switch pulse signal, wherein the width of the gate switch pulse signal is the same as the width of a time differential;
and 5: the gate switch pulse signal is sent to the time interval generation module to form a programmable counter, the programmable counter is used as a gate switch of the programmable counter, the frequency scale signal is counted without gaps in the gate time, and the measurement result of the clock difference between the frequency scale signal and the measured signal is obtained through the size of the count value.
Compared with the prior art, the invention has the beneficial effects that:
the precise short-time interval measuring system based on the Beidou clock disclosed by the invention utilizes the FPGA technology to realize the chip integration and the integration of the measuring system, and has the advantages of simple system structure, low phase noise and strong stability and functionality;
furthermore, the precise short-time interval measurement method based on the Beidou clock reduces the width of the phase coincident point pulse through a differential phase synchronous detection method to extract the phase coincident point edge pulse as a gate switch signal, so that the stability of the gate signal is enhanced, and the accuracy of gate time measurement is improved; based on the method, the precision short-time interval measurement method based on the Beidou clock is different from the existing short-time interval measurement method, the measurement resolution of the short-time interval and the detection resolution and stability of the Beidou time-frequency system are greatly improved, the high-precision time synchronization between the satellite and the ground is realized, and the centimeter-millimeter-level Beidou satellite positioning service capability is enhanced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1: the invention relates to a precision short time interval measuring system based on a Beidou clock, which comprises a satellite receiver module, a first time delay module, a second time delay module, a first phase coincidence point module, a second phase coincidence point module, a third phase coincidence point module, a logic door system module, a gate signal generating module, a time interval generating module, a display module and a power supply module, wherein the first time delay module is connected with the first phase coincidence point module; the signal output end of the satellite receiver module is respectively connected with the signal input end of a first phase coincidence point module, the signal input end of a first time delay module and the signal input end of a second time delay module, the signal output end of the first time delay module is connected with the signal input end of a second phase coincidence point module, the signal output end of the second time delay module is connected with the signal input end of a third phase coincidence point module, the signal output end of the first phase coincidence point module and the signal output end of the second phase coincidence point module are simultaneously connected with the signal input end of a gate signal generation module, the signal output end of the third phase coincidence point module is connected with the signal input end of a logic gate system module, the signal output end of the logic gate system module is connected with the signal input end of the gate signal generation module, and the signal output end of the gate signal generation module is connected with the signal input end, the signal output end of the time interval generating module is connected with the signal input end of the display module;
the satellite receiver module adopts a Beidou receiver, preferably, the Beidou receiver adopts an XHTF7107-B type Beidou receiver and is used for providing satellite frequency signals and receiver oscillator signals, namely, measured signals and beacon signals; the measured signal and the frequency mark signal are pulse signals with the frequency of 1575.42MHz (L1 wave band frequency), the measured signal adopts a satellite time mark, the frequency mark signal adopts a receiver time mark, the two signals generate clock errors, namely clock difference, due to different time marks, and the clock difference is a short time interval;
the first time delay module adopts a first edge type D trigger with a clock cycle being a first clock cycle and is used for time delay of the first clock cycle of a measured signal and a standard signal; the second time delay module adopts a second edge type D trigger with a clock period as a second clock period and is used for time delay of the second clock period of the measured signal and the standard signal, the first clock period and the second clock period have different sizes, and the absolute value of the difference value between the first clock period and the second clock period is defined as a time differential; preferably, the first edge type D flip-flop and the second edge type D flip-flop both use 74LS175 chips;
the first phase coincidence point module adopts a first pilot frequency phase detection circuit and is used for generating a first phase coincidence point pulse between a detected signal and a standard signal; the second phase coincidence point module adopts a second pilot frequency phase detection circuit and is used for generating a second phase coincidence point pulse between the detected signal and the beacon signal after the second phase coincidence point pulse is delayed by the first time delay module; the third phase coincidence point module adopts a third difference frequency phase detection circuit and is used for generating a third phase coincidence point pulse between the measured signal and the beacon signal after being delayed by the second time delay module; preferably, the first pilot frequency phase detection circuit, the second pilot frequency phase detection circuit and the third pilot frequency phase detection circuit all adopt pilot frequency phase detection circuits, each pilot frequency phase detection circuit is composed of a first D flip-flop, a second D flip-flop, a first logic and gate, a second logic and gate, a third logic and gate, a first logic not gate and a second logic not gate, a D1 input end and a D2 input end of the first D flip-flop are respectively connected with an a1 input end of the first logic and gate and a Q1 output end of the first D flip-flop, a Q2 output end of the first D flip-flop is connected with an input end of the first logic not gate, an output end of the first logic not gate is connected with a B1 input end of the first logic and gate, a D3 input end and a D4 input end of the second D flip-flop are respectively connected with an a2 input end of the second logic and gate and a Q3 output end of the second D flip-flop, a Q4 output end of the second D flip-flop is connected with an input end of the second logic not gate, the output end of the second logical not gate is connected with the B2 input end of the second logical AND gate, and the output end Y1 of the second logical AND gate and the output end Y2 of the second logical AND gate are respectively connected with the A3 input end and the B3 input end of the third logical AND gate; the output end Y3 of the third logic AND gate is the output end of the pilot frequency phase coincidence detection circuit; the D1 input end of a first D trigger and the D3 input end of a second D trigger of the first pilot frequency phase detection circuit are respectively used as the input ends of a frequency standard signal and a detected signal, the frequency standard signal and the detected signal are sent to the first pilot frequency phase detection circuit for pilot frequency phase discrimination, a first phase coincidence point pulse is output by the output end Y3 of a third logic AND gate of the first pilot frequency phase detection circuit, the first phase coincidence point pulse is composed of a series of phase difference pulses which cannot be identified by system detection resolution, and the envelope of the first phase coincidence point pulse is Gaussian-shaped and randomly distributed; the input end of the D1 of the first D trigger and the input end of the D3 of the second D trigger of the second pilot frequency phase detection circuit are respectively used as the input ends of a frequency standard signal delayed by the first delay module and a detected signal, the frequency standard signal delayed by the first delay module and the detected signal are sent to the second pilot frequency phase detection circuit for pilot frequency phase discrimination, a second phase coincidence point pulse is output by the output end Y3 of the third logic AND gate of the second pilot frequency phase detection circuit, and compared with the first phase coincidence point pulse, the second phase coincidence point pulse has the same pulse width and is delayed by a first clock period in phase; the D1 input end of the first D flip-flop and the D3 input end of the second D flip-flop of the third differential frequency phase detection circuit are respectively used as the input ends of the frequency scale signal delayed by the second delay module and the signal to be detected, the frequency scale signal delayed by the second delay module and the signal to be detected are sent to the third differential frequency phase detection circuit for differential frequency phase detection, a third phase coincidence point pulse is output by the output end Y3 of the third logic and gate of the third differential frequency phase detection circuit, and the third phase coincidence point pulse is sent to the logic gate system module, preferably, the logic gate system module adopts an inverter which adopts a 74LS04 chip and is used for inverting the phase of the third phase coincidence point pulse; in the process, the time of the frequency scale signal and the time of the measured signal which are respectively sent to the first phase coincidence point module, the first time delay module and the second time delay module are the same, the first clock period and the second clock period are different in size, a time differential exists, the time differential is the measurement resolution of the system, and better system measurement resolution can be obtained by adjusting the first clock frequency and the second clock frequency;
the gate signal generating module adopts a three-input AND gate circuit, preferably, the three-input AND gate circuit adopts a 74LS11 chip and is used for generating a gate switch pulse signal, namely a switch signal of a counting gate of a programmable counter;
the time interval generating module adopts a programmable counter, preferably, the programmable counter is realized by FPGA hardware description language through programming, the FPGA adopts a Cyclone IV chip EP4CE75 for measuring the clock difference between the measured signal and the standard signal, namely the short time interval;
the display module adopts an LCD and is used for receiving and displaying the measurement result of the time interval generation module;
furthermore, the power module supplies power to the whole system, can adopt a switch power supply, and has the advantage of stable output compared with an analog power supply.
The invention relates to a precise short-time interval measurement method based on a Beidou clock, which comprises the following steps of:
step 1: the frequency scale signal and the detected signal provided by the satellite receiver module are sent to a first phase coincidence point module for performing different frequency phase discrimination to generate a first phase coincidence point pulse, wherein the first phase coincidence point pulse is composed of a series of phase difference pulses which cannot be identified by the system detection resolution, and the envelope of the first phase coincidence point pulse is in Gaussian random distribution;
step 2: the frequency standard signal and the measured signal provided by the satellite receiver module are sent to a first time delay module, the time delay amount of the time delay of the first clock cycle is determined by the first clock cycle of a first edge type D trigger, the frequency standard signal and the measured signal after the time delay of the first clock cycle are sent to a second phase coincidence point module for different frequency phase discrimination to generate a second phase coincidence point pulse, and compared with the first phase coincidence point pulse, the second phase coincidence point pulse has the same pulse width and is delayed by one first clock cycle in phase;
and step 3: the frequency scale signal and the measured signal provided by the satellite receiver module are sent to a second time delay module, the time delay amount of the time delay of the second clock cycle is determined by the second clock cycle of a second edge type D trigger, the frequency scale signal and the measured signal after the time delay of the second clock cycle are sent to a third phase coincidence point module for different frequency phase discrimination to generate a third phase coincidence point pulse, then the third phase coincidence point pulse is sent to a logic gate system module, namely a phase inverter for phase inversion to obtain an inverted third phase coincidence point pulse, and the inverted third phase coincidence point pulse has the same pulse width and is inverted in phase and delayed by a second clock cycle compared with the first phase coincidence point pulse;
in the process, the time of the frequency scale signal and the time of the measured signal which are respectively sent to the first phase coincidence point module, the first time delay module and the second time delay module are the same, the first clock period and the second clock period are different in size, a time differential exists, the time differential is the system measurement resolution, and the better system measurement resolution can be obtained by adjusting the first clock frequency and the second clock frequency;
and 4, step 4: simultaneously sending the first phase coincident point pulse, the second phase coincident point pulse and the inverted third phase coincident point pulse into a gate signal generation module, namely a three-input and logic gate circuit, and generating a gate switch pulse signal, wherein the width of the gate switch pulse signal is the same as the width of a time differential;
and 5: the gate switch pulse signal is sent to the time interval generation module to form a programmable counter, the programmable counter is used as a gate switch of the programmable counter, the frequency scale signal is counted without gaps in the gate time, and the measurement result of the clock difference between the frequency scale signal and the measured signal is obtained through the size of the count value.
Compared with the prior art, the precision short-time interval measuring system and method based on the Beidou clock have the beneficial effects that:
in the existing Beidou time-frequency system, a frequency scale tracking circuit ensures the stability of the frequency relation between a frequency scale signal and a measured signal, namely the stability of the measurement resolution of the system, under the stable measurement resolution, the measurement precision of the system is mainly influenced by a detection device, a series of phase coincidence point pulses can be generated when the different-frequency phase is detected by high measurement resolution and low detection resolution, the resolutions of the detection devices are different, the edge characteristics of the phase coincidence point pulses are also different, an opening signal and a closing signal in a reference gate are not strictly synchronous at corresponding moments, and the measurement precision of the actual gate time is influenced;
according to the invention, the width of the phase coincident point pulse is reduced by a differential phase synchronous detection method to extract the phase coincident point edge pulse as a gate switch signal, so that the stability of the gate signal is enhanced, and the accuracy of gate time measurement is improved; based on the method, the method is different from the existing short-time interval measuring method, the measuring resolution of the short-time interval and the detection resolution and the stability of the Beidou time-frequency system are greatly improved, the high-precision time synchronization between the satellite and the ground is realized, and the centimeter-millimeter-level Beidou satellite positioning service capability is enhanced; furthermore, the invention utilizes the FPGA technology to realize the chip integration and the integration of the measurement system, and the system has simple structure, low phase noise and strong stability and functionality.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. The utility model provides a precision short time interval measurement system based on big dipper clock which characterized in that: the system comprises a satellite receiver module, a first time delay module, a second time delay module, a first phase coincidence point module, a second phase coincidence point module, a third phase coincidence point module, a logic gate system module, a gate signal generation module, a time interval generation module, a display module and a power supply module; the signal output end of the satellite receiver module is respectively connected with the signal input end of a first phase coincidence point module, the signal input end of a first time delay module and the signal input end of a second time delay module, the signal output end of the first time delay module is connected with the signal input end of a second phase coincidence point module, the signal output end of the second time delay module is connected with the signal input end of a third phase coincidence point module, the signal output end of the first phase coincidence point module and the signal output end of the second phase coincidence point module are simultaneously connected with the signal input end of a gate signal generation module, the signal output end of the third phase coincidence point module is connected with the signal input end of a logic gate system module, the signal output end of the logic gate system module is connected with the signal input end of the gate signal generation module, and the signal output end of the gate signal generation module is connected with the signal input end, the signal output end of the time interval generating module is connected with the signal input end of the display module;
the satellite receiver module adopts a Beidou receiver and is used for providing satellite frequency signals and receiver oscillator signals, namely detected signals and beacon signals;
the first time delay module adopts a first edge type D trigger with a clock cycle being a first clock cycle and is used for time delay of the first clock cycle of a measured signal and a standard signal; the second time delay module adopts a second edge type D trigger with a clock period as a second clock period and is used for time delay of the second clock period of the measured signal and the standard signal, the first clock period and the second clock period have different sizes, and the absolute value of the difference value between the first clock period and the second clock period is defined as a time differential;
the first phase coincidence point module adopts a first pilot frequency phase detection circuit and is used for generating a first phase coincidence point pulse between a detected signal and a standard signal; the second phase coincidence point module adopts a second pilot frequency phase detection circuit and is used for generating a second phase coincidence point pulse between the detected signal and the beacon signal after the second phase coincidence point pulse is delayed by the first time delay module; the third phase coincidence point module adopts a third difference frequency phase detection circuit and is used for generating a third phase coincidence point pulse between the measured signal and the beacon signal after being delayed by the second time delay module;
the logic gate system module adopts an inverter and is used for inverting the phase of the third phase coincident point pulse;
the gate signal generation module adopts a three-input AND gate circuit and is used for generating gate switch pulse signals, namely switch signals of a counting gate;
the time interval generating module adopts a programmable counter and is used for measuring the clock difference between a measured signal and a beacon signal;
and the display module is used for receiving and displaying the measurement result of the time interval generation module.
2. The precise short time interval measuring system based on the Beidou clock according to claim 1, is characterized in that: the Beidou receiver adopts an XHTF7107-B type.
3. The precise short time interval measuring system based on the Beidou clock according to claim 1, is characterized in that: the first edge type D trigger and the second edge type D trigger both adopt 74LS175 chips.
4. The precise short time interval measuring system based on the Beidou clock according to claim 1, is characterized in that: the first pilot frequency phase detection circuit, the second pilot frequency phase detection circuit and the third pilot frequency phase detection circuit all adopt pilot frequency phase detection circuits, each pilot frequency phase detection circuit consists of a first D trigger, a second D trigger, a first logic AND gate, a second logic AND gate, a third logic AND gate, a first logic NOT gate and a second logic NOT gate, the D1 input end and the D2 input end of the first D trigger are respectively connected with the A1 input end of the first logic AND gate and the Q1 output end of the first D trigger, the Q2 output end of the first D trigger is connected with the input end of the first logic NOT gate, the output end of the first logic NOT gate is connected with the B1 input end of the first logic AND gate, the D3 input end and the D4 input end of the second D trigger are respectively connected with the A2 input end of the second logic AND gate and the Q3 output end of the second D trigger, the Q4 output end of the second D trigger is connected with the input end of the second logic NOT gate, the output end of the second logical not gate is connected with the B2 input end of the second logical AND gate, and the output end Y1 of the second logical AND gate and the output end Y2 of the second logical AND gate are respectively connected with the A3 input end and the B3 input end of the third logical AND gate; the output end Y3 of the third logic AND gate is the output end of the pilot frequency phase coincidence detection circuit; the D1 input end of the first D flip-flop of the first pilot frequency phase detection circuit and the D3 input end of the second D flip-flop are respectively used as the input ends of a frequency scale signal and a detected signal, the D1 input end of the first D flip-flop of the second pilot frequency phase detection circuit and the D3 input end of the second D flip-flop are respectively used as the input ends of the frequency scale signal delayed by the first delay module and the detected signal, and the D1 input end of the first D flip-flop of the third pilot frequency phase detection circuit and the D3 input end of the second D flip-flop are respectively used as the input ends of the frequency scale signal delayed by the second delay module and the detected signal.
5. The precise short time interval measuring system based on the Beidou clock according to claim 1, is characterized in that: the inverter adopts a 74LS04 chip.
6. The precise short time interval measuring system based on the Beidou clock according to claim 1, is characterized in that: the three-input AND circuit adopts a 74LS11 chip.
7. The precise short time interval measuring system based on the Beidou clock according to claim 1, is characterized in that: the programmable counter is realized by FPGA hardware description language through programming, and the FPGA adopts a Cyclone IV chip EP4CE 75.
8. The measurement method of the precise short time interval measurement system based on the Beidou clock according to any one of claims 1 to 7, characterized by comprising the following steps:
step 1: the frequency scale signal and the detected signal provided by the satellite receiver module are sent to a first phase coincidence point module for performing different frequency phase discrimination to generate a first phase coincidence point pulse, wherein the first phase coincidence point pulse is composed of a series of phase difference pulses which cannot be identified by the system detection resolution, and the envelope of the first phase coincidence point pulse is in Gaussian random distribution;
step 2: the frequency standard signal and the measured signal provided by the satellite receiver module are sent to a first time delay module, the time delay amount of the time delay of the first clock cycle is determined by the first clock cycle of a first edge type D trigger, the frequency standard signal and the measured signal after the time delay of the first clock cycle are sent to a second phase coincidence point module for different frequency phase discrimination to generate a second phase coincidence point pulse, and compared with the first phase coincidence point pulse, the second phase coincidence point pulse has the same pulse width and is delayed by one first clock cycle in phase;
and step 3: the frequency scale signal and the measured signal provided by the satellite receiver module are sent to a second time delay module, the time delay amount of the time delay of the second clock cycle is determined by the second clock cycle of a second edge type D trigger, the frequency scale signal and the measured signal after the time delay of the second clock cycle are sent to a third phase coincidence point module for different frequency phase discrimination to generate a third phase coincidence point pulse, then the third phase coincidence point pulse is sent to a logic gate system module, namely a phase inverter for phase inversion to obtain an inverted third phase coincidence point pulse, and the inverted third phase coincidence point pulse has the same pulse width and is inverted in phase and delayed by a second clock cycle compared with the first phase coincidence point pulse;
and 4, step 4: simultaneously sending the first phase coincident point pulse, the second phase coincident point pulse and the inverted third phase coincident point pulse into a gate signal generation module, namely a three-input and logic gate circuit, and generating a gate switch pulse signal, wherein the width of the gate switch pulse signal is the same as the width of a time differential;
and 5: the gate switch pulse signal is sent to the time interval generation module to form a programmable counter, the programmable counter is used as a gate switch of the programmable counter, the frequency scale signal is counted without gaps in the gate time, and the measurement result of the clock difference between the frequency scale signal and the measured signal is obtained through the size of the count value.
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