CN107564855A - Array base palte and preparation method thereof, display device - Google Patents
Array base palte and preparation method thereof, display device Download PDFInfo
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- CN107564855A CN107564855A CN201710736777.8A CN201710736777A CN107564855A CN 107564855 A CN107564855 A CN 107564855A CN 201710736777 A CN201710736777 A CN 201710736777A CN 107564855 A CN107564855 A CN 107564855A
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Abstract
The invention belongs to display technology field, and in particular to a kind of array base palte and preparation method thereof, display device.The step of preparation method of the array base palte includes forming material film layer in the side of substrate using etching technics, substrate is located in etching cavity by thimble, before material film layer is formed, in addition to：Substrate material film layer to be formed opposite side formed etch-protecting layer, etch-protecting layer cause substrate back correspond to thimble area etch rate it is consistent with the etch rate that correspond to non-thimble area.On the one hand the array base palte is reduced the 9Mask techniques of existing array base palte turns into 8Mask techniques using one of mask plate, can effectively reduce the technology difficulty in preparation process；On the other hand, by eliminating difference caused by etching inequality in the backside deposition layer of sin x of glass substrate, and then etching Pin Mura generation is eliminated.Etching difference of the etch-protecting layer therein especially suitable for eliminating the substrate back in material etching technics.
Description
Technical field
The invention belongs to display technology field, and in particular to a kind of array base palte and preparation method thereof, display device.
Background technology
At present, LCD (Liquid Crystal Display：Liquid crystal display device) and OLED (Organic Light-
Emitting Diode:Organic Light Emitting Diode) display device has become the main flow of FPD, and the two is brilliant using film
It is inevitable as display control, thin film transistor (TFT) that body pipe (Thin FilmTransistor, abbreviation TFT) forms array base palte
Use material.With the development of Display Technique, there are low temperature polycrystalline silicon (Low Temperature Poly-
Silicon, abbreviation LTPS) backplane technology of array base palte is formed, the high aperture brought due to high mobility and it can realize
The reasons such as GOA (Gate on Array) so that based on the display panel of the backplane technology compared to non-crystalline silicon a-Si backplane technologies
Display panel there is more excellent display effect
Material film layer generally use inductively coupled plasma (Inductive Couple in backboard
Plasmas, abbreviation ICP) dry etching (Dry Etch) technique patterned.Under normal circumstances, a-Si backboards use 4-5
Road mask plate (Mask)；And LTPS backboards need more than 9 mask plates, wherein forming light shielding layer (Light using Mo materials
Shield Layer, abbreviation LS), patterned by patterning processes, then carry out cushion (Buffer) and active layer
(Active), the problems such as complex process, cost is higher be present in patterning.Mask plate is saved according to siliceous light screening material,
Then because the patterning processes of LTPS backboards include dry etch process, because needing to suspend in etching process by more thimbles (Pin)
In etching cavity, abnormal female drawing (Pin Mura) can be caused bad in the region that correspond to thimble.
A kind of array base palte and its corresponding preparation method are designed, reduces the mask plate number used in LTPS backboard processing procedures
Amount, while it is bad to eliminate abnormal female drawing, turns into technical problem urgently to be resolved hurrily at present.
The content of the invention
The technical problems to be solved by the invention are for above-mentioned deficiency in the prior art, there is provided a kind of array base palte and its
Preparation method, display device, the mask plate quantity used in LTPS backboard processing procedures can be effectively reduced, while eliminate abnormal female drawing not
It is good, cost is prepared so as to effectively reduce, while lift production capacity.
Technical scheme is the preparation method of the array base palte used by solving present invention problem, including uses etching
The step of technique forms material film layer in the side of substrate, the substrate in etching cavity, is being formed by thimble
Before material film layer, in addition to：Etching is formed in the opposite side of the substrate material film layer to be formed
Protective layer, the etch-protecting layer cause the substrate back to correspond to the etch rate in thimble area and correspond to non-thimble area
Etch rate is consistent.
Preferably, before the etch-protecting layer is formed, in addition to：With described in the etch-protecting layer homonymy
Substrate side forms the step of auxiliary etch protective layer, and the auxiliary etch protective layer is relative to the etch-protecting layer closer to institute
State substrate, the protective layer used stress influence in the release etch-protecting layer to the substrate of the auxiliary etch.
Preferably, the etch-protecting layer is formed using depositing operation, or, the auxiliary etch protective layer is using heavy
Product technique is formed.
Preferably, the etch-protecting layer is formed using transparent material, or, the auxiliary etch protective layer is using saturating
Bright material is formed, and the transparent material includes any of silicon nitride, silica or silicon oxynitride.
Preferably, the material film layer is amorphous silicon film layer, polycrystalline silicon membrane, silicon nitride film layer, silicon oxide film
Layer or silicon oxynitride film.
Preferably, the array base palte includes thin film transistor (TFT), and the thin film transistor (TFT) includes active layer, the array
Substrate also includes the cushion and light shielding layer that are disposed adjacent successively with the active layer homonymy, the light shielding layer, described slow
Rush layer and the active layer is formed in same patterning processes, the light shielding layer is formed using amorphous silicon material.
A kind of array base palte, including the material film layer of the side of substrate is arranged on, in addition to it is arranged on the substrate
The etch-protecting layer of the opposite side of the material film layer is not provided with, the etch-protecting layer is used to cause the substrate back of the body
The etch rate in face is consistent.
Preferably, between the substrate and the etch-protecting layer, auxiliary etch protective layer is additionally provided with, it is described auxiliary
Help etch-protecting layer protective layer used in described in release closer to the substrate, the auxiliary etch relative to the etch-protecting layer
Stress influence of the etch-protecting layer to the substrate.
Preferably, thin film transistor (TFT) is included in the array base palte, the thin film transistor (TFT) includes active layer, the battle array
Row substrate also includes the cushion and light shielding layer being disposed adjacent successively with the active layer homonymy.
A kind of display device, including above-mentioned array base palte.
The beneficial effects of the invention are as follows：On the one hand the array base palte is reduced the 9Mask techniques of existing array base palte makes
Turn into 8Mask techniques with one of mask plate, the technology difficulty in preparation process can be effectively reduced；On the other hand, by
The backside deposition layer of sin x of glass substrate etches difference caused by inequality to eliminate, and then eliminates etching PinMura generation,
So as to effectively reduce cost, production capacity is improved.
Brief description of the drawings
Fig. 1 is the schematic surface in thimble area and normal area in the array base palte for be not provided with etch-protecting layer；
Fig. 2 is the roughness Variant statistical figure in thimble area and normal area in the array base palte for be not provided with etch-protecting layer；
Fig. 3 is the lateral partial structurtes sectional view of array base palte in the embodiment of the present invention 1；
Fig. 4 is the lateral partial structurtes sectional view of array base palte in the embodiment of the present invention 2；
In accompanying drawing mark：
1- substrates；2- first buffer layers；3- second buffer layers；4- light shielding layers；5- three buffer layers；6- active layers；7-
Etch-protecting layer；8- auxiliary etch protective layers.
Embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
Formula array substrate and preparation method thereof, display device are described in further detail.
In the present invention, photoetching process, refer to include the utilization for exposing the technical process such as (Photo), development, etching (Etch)
Photoresist, mask plate, exposure machine etc. perform etching the technique to form figure；Patterning processes, including photoetching process, in addition to beat
Print, ink-jet etc. other be used for form predetermined pattern technique.
The technical concept of the present invention is：In liquid crystal display device, for LTPS backboards, Mo materials form light screening
The effect of barrier simply carries out the effect of blocking of backlight to active layer, can equally be risen being formed using A-Si materials when backlight is blocked
To the effect of blocking, and if light shielding layer, cushion and active layer can be integrated together, light is carried out with one of mask plate
Carving technology, it will can effectively reduce the cost of production.
The present invention with the application of liquid crystal display as an example, in the 8Mask of array of designs substrate preparation technology, a side
Face uses the mask plate with along with to carry out photoetching process formation figure using a-Si as light shielding layer, by light shielding layer with active layer,
So as to reduce the use of one of mask plate；On the other hand, by setting etch-protecting layer, moreover it is possible to avoid in etching process
In, the etching process that same etching technics carries out cushion has Pin Mura generation the problem of, and then avoid causing most
Whole display Mura.
Embodiment 1：
The present embodiment provides a kind of preparation method of array base palte, and the preparation method can reduce LTPS backboard preparation technologies
While using mask plate quantity, moreover it is possible to ensure good preparation quality, so as to effectively reduce cost, improve production capacity.
The preparation method of the array base palte of the present embodiment, including material is formed in the side of substrate using etching technics
The step of film layer, substrate in etching cavity, are also included by thimble before material film layer is formed：Treated in substrate
The opposite side for forming material film layer forms etch-protecting layer, and etch-protecting layer causes substrate back to correspond to thimble area
Etch rate is consistent with the etch rate that correspond to non-thimble area.
In the present embodiment, material film layer is amorphous silicon film layer (a-Si), polycrystalline silicon membrane (p-Si), silicon nitride film
Layer (SiNx), membranous layer of silicon oxide (SiO2) or silicon oxynitride film (SiON).Light shielding layer, cushion in array base palte and have
Active layer can be formed for material, and be formed in same patterning processes.
In LTPS 8Mask techniques, for array base palte as shown in Figure 3, wherein needing the structure etched, include
Active layer 6 (p-Si), (SiO of three buffer layer 52) and light shielding layer 4 (a-Si), etching technics of above-mentioned Rotating fields progress
Finishing patterns, it is possible to achieve reduce the purpose of one of mask plate.It is not provided with existing in the preparation method of etch-protecting layer,
Although figure (Profile) etching for the trilamellar membrane angle can be realized, etching Pin Mura are had in etching process
It is bad.Especially in liquid crystal display device, light shielding layer, cushion and active layer are being performed etching in same patterning processes
During, can thimble area produce etching Pin Mura, and then influence device finally through rate.
Discovery is conscientiously researched and analysed to Pin Mura by inventor, it is bad for dry etching Pin Mura, such as Fig. 1
It is shown, the thickness etch critical dimension (Critical Dimension, abbreviation CD) of the film layer in thimble area (Pin areas) and normal area
Respectively 3.21 μm and 3.17 μm, and notable difference is not present, illustrate Pin Mura generation be not from substrate 1 set it is thin
The etch critical dimension difference of film transistor side.By the AFM that the back side is carried out to Pin Mura areas and normal area
Point of (Atomic Force Microscope, abbreviation AFM, the outward appearance roughness for array substrate carry out analysis test)
Result is analysed it can be found that the roughness in Pin Mura areas and normal area has larger difference.As shown in Fig. 2 the back side pair of substrate 1
The roughness in thimble area and normal area is answered to have larger difference, the average value of the roughness in normal area is 2 times of left sides in thimble area
The right side, therefore judge that macroscopic Pin Mura should come from the difference of the roughness at the back side of substrate 1.
Inventor has found that Pin Mura generation is due to material film layer by further studying Pin Mura,
Especially to SiO2Caused by etching difference in the etching process of film layer, thus infer in the etching process and etch SiO2Gas
Body produces different influences, and because the etching bar in thimble area and normal area to the back side of substrate 1 in thimble area and non-thimble area
Part is different (for example, because the gas flow rates in thimble area and normal area are different, to cause temperature difference, therefore thimble area and just
The etch rate in normal area is different), the difference of roughness its structure is caused, result in Pin Mura generation.That is, every quarter
Lose material film layer structure or similar film layer structure, thimble area and be not provided with thimble normal area film layer etching difference
It is not Pin Mura Producing reasons, Pin Mura come from the etching difference at the back side of substrate 1.Therefore, the present embodiment is
Solve Pin Mura generation, etch-protecting layer is set using at the back side of substrate 1, such as certain thickness SiNx films are set
Layer influences to eliminate etching Pin Mura.
Wherein, etch-protecting layer 7 uses transparent material, without graphical, therefore can be formed by depositing operation, such as adopt
With plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, abbreviation
PECVD) technique is formed.Preferably, etch-protecting layer 7 is using silicon nitride (SiNx), silica (SiO2) or silicon oxynitride
Any of (SiON) formed.For example, etch-protecting layer 7 can be deposited as in the back side of substrate 1 progress individual layer SiNx,
The thickness range of the etch-protecting layer 7 is 500A-5000A.Etch-protecting layer 7 includes but is not limited to SiNx, SiO2Or SiON, only
For transparent material and protection can be performed etching to the back side of substrate 1, do not limited here.
After SiNx film depositions formation etch-protecting layer is carried out at the back side of substrate 1, substrate 1 is subjected to reverse side rotation
Carry out the preparation of follow-up thin film transistor (TFT).In Fig. 3, thin film transistor (TFT) includes active layer 6, before active layer 6 is formed：In battle array
Light shielding layer 4 and three buffer layer 5 are also formed with row substrate, light shielding layer 4, three buffer layer 5 and active layer 6 are in same structure
Formed in figure technique, thin film transistor (TFT) therein is adopted using low temperature polycrystalline silicon (LTPS) material as active layer 6, light shielding layer 4
Formed with a-Si materials.
Accordingly, the present embodiment also provides a kind of array base palte, including is arranged on the material film layer of substrate 1, also wraps
The etch-protecting layer 7 for being arranged on the opposite side that substrate 1 is not provided with material film layer is included, etch-protecting layer 7 is used to cause substrate 1
The back side etch rate it is consistent.
In the present embodiment, array base palte includes thin film transistor (TFT), and thin film transistor (TFT) includes active layer 6, and array base palte is also
Including the three buffer layer 5 and light shielding layer 4 being disposed adjacent successively with the homonymy of active layer 6.Substrate 1 therein is transparent material,
For example, glass substrate.With reference to figure 3, the top of substrate 1 is first buffer layer 2, second buffer layer 3, light shielding layer 4, successively
Three buffer layer 5 and active layer 6, the lower section of substrate 1 is etch-protecting layer 7.Wherein, first buffer layer 2 is formed using SiNx materials,
For preventing granule foreign from entering in glass substrate 1；Second buffer layer 3 uses SiO2Material, for stay on it is square into
The a-Si lattices of light shielding layer 4 match；Light shielding layer 4 uses a-Si materials, and backlight is blocked for realizing；3rd is slow
Rush layer 5 and use SiO2Material is formed, for a-Si lattices below and stay on it is square into active layer 6 P-Si it is brilliant
Lattice match.Certainly, the complete structure as thin film transistor (TFT), array base palte also includes source electrode, drain and gate etc., and other are tied
Structure, corresponding hierarchical relationship is set according to top-gate type structure or bottom-gate type configuration, I will not elaborate.
The array base palte of the present embodiment, on the one hand the 9Mask techniques of existing array base palte are reduced and use one of mask
Plate turns into 8Mask techniques, can effectively reduce the technology difficulty in preparation process；On the other hand, by glass substrate
Backside deposition layer of sin x etches difference caused by inequality to eliminate, and then eliminates etching Pin Mura generation.
Here it will be understood that array base palte in the present embodiment and preparation method thereof, just for liquid crystal display
Preparation and effect of the structure to etch-protecting layer with light shielding layer are illustrated in part, the array base palte of the present embodiment and
The core of its preparation method is etch-protecting layer for material film layer (especially SiO2Material) it is right in etching process
The effect of the etch rate uniformity at the back side of substrate.In the same way, simply by the presence of the preparation technology of material film layer,
Using the etch-protecting layer exemplified by the present embodiment, do not limit here.
Embodiment 2：
The present embodiment provides a kind of preparation method of array base palte, and the preparation method can reduce LTPS backboard preparation technologies
While using mask plate quantity, moreover it is possible to ensure good preparation quality, so as to effectively reduce cost, improve production capacity.
The difference of the array base palte of the present embodiment and the array base palte of embodiment 1 is, as shown in figure 4, in the present embodiment
Array base palte except forming etch-protecting layer 7, also form auxiliary etch protective layer 8.In the system of the array base palte of the present embodiment
In Preparation Method, before etch-protecting layer 7 is formed, in addition to：Carved forming auxiliary with the side of substrate 1 of the homonymy of etch-protecting layer 7
The step of losing protective layer 8, auxiliary etch protective layer 8 is used relative to etch-protecting layer 7 closer to substrate 1, auxiliary etch protective layer 8
Stress influence in release etch-protecting layer 7 to substrate 1.
Wherein, etch-protecting layer 7 and auxiliary etch protective layer 8 are formed using depositing operation.It is same as Example 1, etching
Protective layer 7 and auxiliary etch protective layer 8 are formed using transparent material.It is preferred that etch-protecting layer 7, auxiliary etch protective layer 8 use
SiNx、SiO2Or any of SiON formation.Here, when depositing the etch-protecting layer 7 at the back side of the substrate 1, in order to not increase
The stress of plus substrate 1, by depositing one layer of SiO below the SiNx film layers of etch-protecting layer 72, sunk with the back side of release liners 1
The influence for the stress that integrated membrane layer is brought.
Accordingly, the present embodiment also provides a kind of array base palte, and with reference to figure 4, the array base palte is protected in substrate 1 and etching
Between layer 7, auxiliary etch protective layer 8 is additionally provided with, auxiliary etch protective layer 8 is used to discharge the answering to substrate 1 of etch-protecting layer 7
Power influences.
In Fig. 4, the top of substrate 1 is first buffer layer 2, second buffer layer 3, light shielding layer 4, three buffer layer 5 successively
With active layer 6, the lower section of substrate 1 is etch-protecting layer 7.Wherein, first buffer layer 2 is formed using SiNx materials, for preventing
Granule foreign enters in glass substrate 1；Second buffer layer 3 uses SiO2Material, for stay on it is square into light block
The a-Si lattices of layer 4 match；Light shielding layer 4 uses a-Si materials, and backlight is blocked for realizing；Three buffer layer 5 is adopted
Use SiO2Material is formed, for a-Si lattices below and stay on it is square into active layer 6 P-Si lattice phases
Match somebody with somebody.
Similarly, will after SiNx is carried out to the back side of substrate 1 and deposits and to form auxiliary etch protective layer 8 and etch-protecting layer 7
Substrate 1 carries out the preparation that reverse side rotation can be carried out follow-up thin film transistor (TFT).
In the array base palte of the present embodiment, the material and preparation technology of other Rotating fields correspond to Rotating fields with embodiment 1
Material it is identical with preparation technology, repeat no more here.
The preparation method of the array base palte of embodiment 1- embodiments 2 and its corresponding array base palte, by least provided with quarter
Protective layer is lost, can effectively solve etch rate difference problem of the material film layer in etching technics, LTPS is reduced realizing
While backboard preparation technology uses mask plate quantity, Pin Mura generation is also further obviated, so as to effectively reduce into
This, improves production capacity.
Embodiment 3：
The present embodiment provides a kind of display device, and the display device includes array base any in embodiment 1- embodiments 2
Plate.
The display device can be：Desktop computer, tablet personal computer, notebook computer, mobile phone, PDA, GPS, car-mounted display,
Projection Display, video camera, digital camera, electronic watch, calculator, electronic instrument and meter, liquid crystal panel, Electronic Paper, TV
Any product or part with display function such as machine, display, DPF, navigator, can be applied to public display and void
The multiple fields such as unreal display.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, but the invention is not limited in this.For those skilled in the art, the essence of the present invention is not being departed from
In the case of refreshing and essence, various changes and modifications can be made therein, and these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of preparation method of array base palte, including the step of material film layer is formed in the side of substrate using etching technics
Suddenly, the substrate is located in etching cavity by thimble, it is characterised in that before material film layer is formed, in addition to：
Etch-protecting layer is formed in the opposite side of the substrate material film layer to be formed, the etch-protecting layer causes institute
State substrate back correspond to thimble area etch rate it is consistent with the etch rate that correspond to non-thimble area.
2. preparation method according to claim 1, it is characterised in that before the etch-protecting layer is formed, in addition to：
Form auxiliary etch protective layer with the substrate side of the etch-protecting layer homonymy the step of, the auxiliary etch protective layer
It is protective layer used in the release etch-protecting layer pair closer to the substrate, the auxiliary etch relative to the etch-protecting layer
The stress influence of the substrate.
3. preparation method according to claim 1 or 2, it is characterised in that the etch-protecting layer uses depositing operation shape
Into, or, the auxiliary etch protective layer is formed using depositing operation.
4. preparation method according to claim 1 or 2, it is characterised in that the etch-protecting layer uses transparent material shape
Into, or, the auxiliary etch protective layer is formed using transparent material, and the transparent material includes silicon nitride, silica or nitrogen
Any of silica.
5. preparation method according to claim 1 or 2, it is characterised in that the material film layer be amorphous silicon film layer,
Polycrystalline silicon membrane, silicon nitride film layer, membranous layer of silicon oxide or silicon oxynitride film.
6. preparation method according to claim 1 or 2, it is characterised in that the array base palte includes thin film transistor (TFT), institute
Stating thin film transistor (TFT) includes active layer, and the array base palte also includes the cushion being disposed adjacent successively with the active layer homonymy
And light shielding layer, the light shielding layer, the cushion and the active layer are formed in same patterning processes, the light blocks
Layer is formed using amorphous silicon material.
7. a kind of array base palte, including it is arranged on the material film layer of the side of substrate, it is characterised in that also include being arranged on
The substrate is not provided with the etch-protecting layer of the opposite side of the material film layer, and the etch-protecting layer is used to cause institute
The etch rate for stating substrate back is consistent.
8. array base palte according to claim 8, it is characterised in that between the substrate and the etch-protecting layer,
Be additionally provided with auxiliary etch protective layer, the auxiliary etch protective layer relative to the etch-protecting layer closer to the substrate,
The protective layer used stress influence in the release etch-protecting layer to the substrate of the auxiliary etch.
9. the array base palte according to claim 7 or 8, it is characterised in that include thin film transistor (TFT) in the array base palte,
The thin film transistor (TFT) includes active layer, and the array base palte also includes the buffering being disposed adjacent successively with the active layer homonymy
Layer and light shielding layer.
10. a kind of display device, it is characterised in that including the array base palte described in claim any one of 7-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710736777.8A CN107564855B (en) | 2017-08-24 | 2017-08-24 | Array substrate, preparation method thereof and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710736777.8A CN107564855B (en) | 2017-08-24 | 2017-08-24 | Array substrate, preparation method thereof and display device |
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| CN107564855A true CN107564855A (en) | 2018-01-09 |
| CN107564855B CN107564855B (en) | 2020-05-26 |
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Cited By (1)
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| CN111583883A (en) * | 2020-05-29 | 2020-08-25 | 上海中航光电子有限公司 | Integrated drive board, display device and manufacturing method |
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| CN105226029A (en) * | 2014-06-25 | 2016-01-06 | 环球晶圆股份有限公司 | The silicon substrate of tool compression and manufacture method thereof |
| CN105304446A (en) * | 2015-09-18 | 2016-02-03 | 京东方科技集团股份有限公司 | Lower electrode base platform of dry etching device and dry etching device |
| US20160111682A1 (en) * | 2014-10-20 | 2016-04-21 | Samsung Display Co., Ltd. | Display device |
| CN106033289A (en) * | 2015-03-19 | 2016-10-19 | 河北冀雅电子有限公司 | Black-white lattice touch liquid crystal screen and manufacturing method thereof |
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| CN105226029A (en) * | 2014-06-25 | 2016-01-06 | 环球晶圆股份有限公司 | The silicon substrate of tool compression and manufacture method thereof |
| US20160111682A1 (en) * | 2014-10-20 | 2016-04-21 | Samsung Display Co., Ltd. | Display device |
| CN106033289A (en) * | 2015-03-19 | 2016-10-19 | 河北冀雅电子有限公司 | Black-white lattice touch liquid crystal screen and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111583883A (en) * | 2020-05-29 | 2020-08-25 | 上海中航光电子有限公司 | Integrated drive board, display device and manufacturing method |
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